LLVM / project - FreshBSD

LLVM/project 7ee82b6 — llvm/docs AMDGPUUsage.rst, llvm/test/Analysis/CostModel/RISCV cast.ll

Sep 12, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-blocks-with-pseudo-probes

Move matchInlineTrees into InlineTreeNodeMapTy

Created using spr 1.3.4

Delta		File
+2,311	-3,013	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+3,407	-2	llvm/test/Analysis/CostModel/RISCV/cast.ll
+1,558	-1,475	llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+1,530	-1,468	llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+975	-1,835	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+2,259	-14	llvm/docs/AMDGPUUsage.rst
+12,040	-7,807	3,332 files not shown
+148,078	-55,972	3,338 files

LLVM/project 41e1fa0 — llvm/docs AMDGPUUsage.rst, llvm/test/Analysis/CostModel/RISCV cast.ll

Sep 12, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-blocks-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+2,311	-3,013	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+3,407	-2	llvm/test/Analysis/CostModel/RISCV/cast.ll
+1,558	-1,475	llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+1,530	-1,468	llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+975	-1,835	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+2,259	-14	llvm/docs/AMDGPUUsage.rst
+12,040	-7,807	3,329 files not shown
+147,985	-55,917	3,335 files

LLVM/project a1a651f — llvm/docs AMDGPUUsage.rst, llvm/test/Analysis/CostModel/RISCV cast.ll

Sep 11, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/main.bolt-drop-blocks-without-profile-in-bat-yaml

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+2,311	-3,013	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+3,407	-2	llvm/test/Analysis/CostModel/RISCV/cast.ll
+1,558	-1,475	llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+1,530	-1,468	llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+975	-1,835	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+2,259	-14	llvm/docs/AMDGPUUsage.rst
+12,040	-7,807	3,085 files not shown
+127,405	-47,554	3,091 files

LLVM/project 0f640d9 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 11, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/bolt-only-parse-probes-for-profiled-functions-in-profile-write-pseudo-probes-mode

rebase

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	5,903 files not shown
+532,673	-540,540	5,909 files

LLVM/project eeb2051 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 11, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/main.bolt-only-parse-probes-for-profiled-functions-in-profile-write-pseudo-probes-mode

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	5,903 files not shown
+532,671	-540,538	5,909 files

LLVM/project 732cf03 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 11, 2024 by Jason Molenda via Amir Ayupov on ⎇

users/aaupov/spr/main.boltnfc-rename-profile-use-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	5,902 files not shown
+532,586	-540,488	5,908 files

LLVM/project 1c8b150 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 11, 2024 by shawbyoung via Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-functions-with-pseudo-probes

Less naive pseudo probe function matching: for each non-matching YamlBF, determine best matching binary inline subtrees, find corresponding binary functions, attach the profile to binary function without a profile and most probes

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	13,020 files not shown
+1,054,256	-818,251	13,026 files

LLVM/project 836f08b — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 11, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-functions-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	13,020 files not shown
+1,054,117	-818,226	13,026 files

LLVM/project b1c9a23 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 9, 2024 by Justin Bogner on ⎇

users/bogner/sprdirectx-lower-llvmdxtypedbufferstore-to-dxil-ops

Clean up tests, add docs

Created using spr 1.3.5-bogner

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	8,446 files not shown
+688,006	-612,420	8,452 files

LLVM/project ae6e0b8 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 9, 2024 by Justin Bogner on ⎇

users/bogner/sprmain.directx-lower-llvmdxtypedbufferstore-to-dxil-ops

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5-bogner

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	8,445 files not shown
+687,943	-612,405	8,451 files

LLVM/project c0c5546 — clang/test/Sema/aarch64-neon-immediate-ranges vector-shift-right.c, llvm/docs AMDGPUUsage.rst

Sep 9, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpvectorize-of-gathered-loads

Rebase

Created using spr 1.3.5

Delta		File
+2,241	-0	llvm/docs/AMDGPUUsage.rst
+1,296	-564	llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
+1,763	-0	llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
+1,265	-0	llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
+1,083	-0	clang/test/Sema/aarch64-neon-immediate-ranges/vector-shift-right.c
+61	-697	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+7,709	-1,261	1,049 files not shown
+38,224	-11,085	1,055 files

LLVM/project 02812ed — clang/test/Sema/aarch64-neon-immediate-ranges vector-shift-right.c vector-load.c, llvm/test/CodeGen/RISCV memcmp.ll atomicrmw-cond-sub-clamp.ll

Sep 9, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-add-initial-support-of-memcmp-expansion

Rebase on tests

Created using spr 1.3.6-beta.1

Delta		File
+3,491	-498	llvm/test/CodeGen/RISCV/memcmp.ll
+1,763	-0	llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
+1,265	-0	llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
+1,083	-0	clang/test/Sema/aarch64-neon-immediate-ranges/vector-shift-right.c
+692	-0	clang/test/Sema/aarch64-neon-immediate-ranges/vector-load.c
+675	-0	llvm/test/CodeGen/RISCV/inline-asm-mem-constraint.ll
+8,969	-498	625 files not shown
+29,877	-7,518	631 files

LLVM/project 24dc612 — clang/test/Sema/aarch64-neon-immediate-ranges vector-shift-right.c vector-load.c, llvm/test/CodeGen/RISCV memcmp.ll atomicrmw-cond-sub-clamp.ll

Sep 9, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/main.riscv-add-initial-support-of-memcmp-expansion

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+1,763	-0	llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
+1,669	-0	llvm/test/CodeGen/RISCV/memcmp.ll
+1,265	-0	llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
+1,083	-0	clang/test/Sema/aarch64-neon-immediate-ranges/vector-shift-right.c
+692	-0	clang/test/Sema/aarch64-neon-immediate-ranges/vector-load.c
+675	-0	llvm/test/CodeGen/RISCV/inline-asm-mem-constraint.ll
+7,147	-0	625 files not shown
+28,055	-7,020	631 files

LLVM/project 63e2f09 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 7, 2024 by Justin Bogner on ⎇

users/bogner/sprdirectx-lower-llvmdxtypedbufferload-to-dxil-ops

Rework to match llvm/wg-hlsl#59

Created using spr 1.3.5-bogner

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	8,525 files not shown
+692,028	-613,469	8,531 files

LLVM/project 3e7a95c — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 7, 2024 by Mircea Trofin via Justin Bogner on ⎇

users/bogner/sprmain.directx-lower-llvmdxtypedbufferload-to-dxil-ops

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5-bogner

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	8,524 files not shown
+691,802	-613,298	8,530 files

LLVM/project b8b1527 — clang/lib/Analysis UnsafeBufferUsage.cpp, compiler-rt/include/sanitizer rtsan_interface.h

Sep 6, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpinitial-support-for-non-power-of-2-but-still-whole-register-number-of-elements-in-operands-1

Rebase, address comments

Created using spr 1.3.5

Delta		File
+374	-6	llvm/test/CodeGen/X86/select.ll
+151	-154	llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+148	-154	compiler-rt/test/builtins/Unit/divsc3_test.c
+53	-31	clang/lib/Analysis/UnsafeBufferUsage.cpp
+75	-0	compiler-rt/include/sanitizer/rtsan_interface.h
+68	-6	llvm/include/llvm/Support/Compiler.h
+869	-351	70 files not shown
+1,577	-505	76 files

LLVM/project 2e9b331 — compiler-rt/lib/rtsan rtsan_flags.cpp rtsan_flags.h, compiler-rt/lib/rtsan/tests rtsan_test_context.cpp

Sep 6, 2024 by Chris Apple via GitHub on ⎇

main

[compiler-rt][rtsan] Introduce RTSAN_OPTIONS and flags (#107174)

This matches much of the boilerplate found in the other sanitizers.

Delta		File
+58	-0	compiler-rt/lib/rtsan/rtsan_flags.cpp
+28	-0	compiler-rt/lib/rtsan/rtsan_flags.h
+16	-10	compiler-rt/lib/rtsan/tests/rtsan_test_context.cpp
+20	-0	compiler-rt/lib/rtsan/rtsan_flags.inc
+0	-12	compiler-rt/lib/rtsan/rtsan_stack.cpp
+11	-0	compiler-rt/test/rtsan/unrecognized_flags.cpp
+133	-22	6 files not shown
+149	-23	12 files

LLVM/project 0f455d0 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 4, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-blocks-with-pseudo-probes

rebase

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	13,304 files not shown
+1,065,629	-822,709	13,310 files

LLVM/project bfa0afc — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 4, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-blocks-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	13,305 files not shown
+1,065,625	-823,010	13,311 files

LLVM/project 5179f0c — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 3, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvinitial-support-for-safe-distance-in-predicated-datawithevl-vectorization-mode

Rebase

Created using spr 1.3.5

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	3,530 files not shown
+384,801	-494,872	3,536 files

LLVM/project 01d6dd3 — llvm/lib/Target/AMDGPU AMDGPUSplitModule.cpp, llvm/test/CodeGen/AArch64 atomicrmw-fadd.ll atomicrmw-fsub.ll

Aug 29, 2024 by Matheus Izvekov on ⎇

users/mizvekov/clang-fix-GH106182

Merge remote-tracking branch 'origin/main' into users/mizvekov/clang-fix-GH106182

Delta		File
+1,306	-563	llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
+1,155	-310	llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+1,028	-41	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+1,033	-0	llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
+1,033	-0	llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
+940	-85	llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
+6,495	-999	1,029 files not shown
+33,447	-11,732	1,035 files

LLVM/project 6200bc5 — llvm/lib/Target/AMDGPU AMDGPUSplitModule.cpp, llvm/test/CodeGen/AArch64 atomicrmw-fsub.ll atomicrmw-fadd.ll

Aug 29, 2024 by Alex Richardson on ⎇

users/arichardson/spr/compiler-rt-simplify-definition-of-uptr

rebase

Created using spr 1.3.6-beta.1

Delta		File
+1,306	-563	llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
+1,155	-310	llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+1,028	-41	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+1,033	-0	llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
+1,033	-0	llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
+940	-85	llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
+6,495	-999	795 files not shown
+27,806	-9,751	801 files

LLVM/project 28147d9 — llvm/lib/Target/AMDGPU AMDGPUSplitModule.cpp, llvm/test/CodeGen/AArch64 atomicrmw-fadd.ll atomicrmw-fsub.ll

Aug 29, 2024 by Alex Richardson on ⎇

users/arichardson/spr/main.compiler-rt-simplify-definition-of-uptr

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+1,306	-563	llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
+1,155	-310	llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+1,028	-41	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+1,033	-0	llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
+1,033	-0	llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
+940	-85	llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
+6,495	-999	795 files not shown
+27,806	-9,751	801 files

LLVM/project c3db84a — llvm/lib/Target/AMDGPU AMDGPUSplitModule.cpp, llvm/test/CodeGen/AArch64 sve-bitcast.ll

Aug 29, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpbetter-cost-estimation-for-masked-gather-or-clustered-loads

Rebase

Created using spr 1.3.5

Delta		File
+3,646	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1-fake16.s
+3,508	-0	llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1-fake16.s
+2,731	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16-fake16.s
+1,306	-563	llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
+249	-807	llvm/test/CodeGen/AArch64/sve-bitcast.ll
+590	-381	llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
+12,030	-1,751	1,425 files not shown
+44,405	-16,813	1,431 files

LLVM/project b8b20b8 — clang/lib/Sema SemaTemplateDeduction.cpp, libcxx/docs/Status Cxx23Issues.csv

Aug 29, 2024 by Alex Richardson on ⎇

users/arichardson/spr/compiler-rt-work-around-incompatible-windows-definitions-of-ssize_t

fix windows build (tested mingw32)

Created using spr 1.3.6-beta.1

Delta		File
+905	-0	llvm/test/CodeGen/X86/fp16-libcalls.ll
+870	-10	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+590	-276	clang/lib/Sema/SemaTemplateDeduction.cpp
+694	-0	llvm/test/Transforms/SimplifyCFG/X86/hoist-loads-stores-with-cf.ll
+349	-0	llvm/test/CodeGen/NVPTX/bf16-instructions.ll
+156	-156	libcxx/docs/Status/Cxx23Issues.csv
+3,564	-442	511 files not shown
+11,243	-4,930	517 files

LLVM/project 5a1795d — llvm/test/CodeGen/AArch64 sve-bitcast.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-fp.ll

Aug 29, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/boltnfci-strip-suffix-in-getltocommonname

rebase

Created using spr 1.3.4

Delta		File
+3,646	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1-fake16.s
+3,508	-0	llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1-fake16.s
+2,731	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16-fake16.s
+249	-807	llvm/test/CodeGen/AArch64/sve-bitcast.ll
+905	-0	llvm/test/CodeGen/X86/fp16-libcalls.ll
+870	-10	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+11,909	-817	1,240 files not shown
+38,879	-14,216	1,246 files

LLVM/project 4cd65d6 — llvm/lib/Target/AMDGPU AMDGPUMachineCFGStructurizer.cpp, llvm/test/CodeGen/AArch64 rem.ll

Aug 28, 2024 by Matheus Izvekov on ⎇

users/mizvekov/clang-fix-GH18291

Merge remote-tracking branch 'origin/main' into users/mizvekov/clang-fix-GH18291

Delta		File
+9,770	-313	llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
+4,427	-0	llvm/test/CodeGen/AArch64/rem.ll
+3,646	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1-fake16.s
+3,508	-0	llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1-fake16.s
+0	-2,837	llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
+2,731	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16-fake16.s
+24,082	-3,150	3,503 files not shown
+146,778	-50,644	3,509 files

LLVM/project e24c249 — llvm/include/llvm/ExecutionEngine/Orc LoadLinkableFile.h LoadRelocatableObject.h, llvm/lib/ExecutionEngine/Orc LoadLinkableFile.cpp LoadRelocatableObject.cpp

Aug 28, 2024 by wanglei on ⎇

users/wangleiat/spr/loongarch-optimize-for-immediate-value-materialization-using-bstrins_d-instruction

rebase

Created using spr 1.3.5-bogner

Delta		File
+121	-0	llvm/lib/ExecutionEngine/Orc/LoadLinkableFile.cpp
+0	-82	llvm/lib/ExecutionEngine/Orc/LoadRelocatableObject.cpp
+55	-24	llvm/lib/ExecutionEngine/Orc/MachO.cpp
+64	-0	llvm/include/llvm/ExecutionEngine/Orc/LoadLinkableFile.h
+6	-38	llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
+0	-37	llvm/include/llvm/ExecutionEngine/Orc/LoadRelocatableObject.h
+246	-181	19 files not shown
+337	-237	25 files

LLVM/project a9fc4d8 — llvm/include/llvm/ExecutionEngine/Orc LoadLinkableFile.h LoadRelocatableObject.h, llvm/lib/ExecutionEngine/Orc LoadLinkableFile.cpp LoadRelocatableObject.cpp

Aug 28, 2024 by wanglei on ⎇

users/wangleiat/spr/main.loongarch-optimize-for-immediate-value-materialization-using-bstrins_d-instruction

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5-bogner

[skip ci]

Delta		File
+121	-0	llvm/lib/ExecutionEngine/Orc/LoadLinkableFile.cpp
+0	-82	llvm/lib/ExecutionEngine/Orc/LoadRelocatableObject.cpp
+55	-24	llvm/lib/ExecutionEngine/Orc/MachO.cpp
+64	-0	llvm/include/llvm/ExecutionEngine/Orc/LoadLinkableFile.h
+6	-38	llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
+0	-37	llvm/include/llvm/ExecutionEngine/Orc/LoadRelocatableObject.h
+246	-181	19 files not shown
+337	-237	25 files

LLVM/project a845c79 — llvm/include/llvm/ExecutionEngine/Orc LoadLinkableFile.h LoadRelocatableObject.h, llvm/lib/ExecutionEngine/Orc LoadLinkableFile.cpp LoadRelocatableObject.cpp

Aug 28, 2024 by wanglei on ⎇

users/wangleiat/spr/loongarch-pre-commit-test-for-immediate-value-materialization-using-bstrins_d

rebase

Created using spr 1.3.5-bogner

Delta		File
+121	-0	llvm/lib/ExecutionEngine/Orc/LoadLinkableFile.cpp
+0	-82	llvm/lib/ExecutionEngine/Orc/LoadRelocatableObject.cpp
+55	-24	llvm/lib/ExecutionEngine/Orc/MachO.cpp
+64	-0	llvm/include/llvm/ExecutionEngine/Orc/LoadLinkableFile.h
+6	-38	llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
+0	-37	llvm/include/llvm/ExecutionEngine/Orc/LoadRelocatableObject.h
+246	-181	19 files not shown
+337	-237	25 files