LLVM / project / 836f08b / [𝘀𝗽𝗿] changes introduced through rebase

LLVM/project 836f08b — . .git-blame-ignore-revs, .github new-prs-labeler.yml CODEOWNERS

Sep 11, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-functions-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+10,766	-12,049	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
+10,766	-12,049	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
+8,109	-7,548	llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+8,109	-7,548	llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+9,474	-2,033	llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+5,958	-4,708	llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
+6,102	-4,432	llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
+9,770	-313	llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
+9,827	-0	llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
+9,694	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
+3,980	-4,433	llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
+3,980	-4,433	llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
+3,890	-3,978	llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
+3,890	-3,978	llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
+6,066	-1,107	llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+3,107	-3,687	llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
+3,106	-3,686	llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
+2,930	-3,165	llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
+2,929	-3,164	llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
+5,845	-0	clang/lib/AST/ByteCode/Compiler.cpp
+5,604	-0	llvm/test/CodeGen/RISCV/rvv/vrgather.ll
+0	-5,598	clang/lib/AST/Interp/Compiler.cpp
+2,593	-2,593	clang/test/OpenMP/task_codegen.cpp
+5,032	-0	llvm/test/CodeGen/X86/avx10_2ni-intrinsics.ll
+0	-4,820	llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
+4,030	-745	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+4,415	-0	llvm/test/CodeGen/AArch64/rem.ll
+0	-4,299	llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
+4,027	-31	llvm/unittests/SandboxIR/SandboxIRTest.cpp
+2,012	-1,642	libc/newhdrgen/yaml/math.yaml
+3,646	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1-fake16.s
+3,597	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop1-fake16.s
+3,508	-0	llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1-fake16.s
+3,300	-0	llvm/test/MC/Disassembler/X86/avx10_2ni-64.txt
+3,300	-0	llvm/test/MC/Disassembler/X86/avx10_2ni-32.txt
+3,299	-0	llvm/test/MC/X86/avx10_2ni-32-intel.s
+3,299	-0	llvm/test/MC/X86/avx10_2ni-64-att.s
+1,852	-1,328	llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+2,219	-897	llvm/test/CodeGen/X86/ucmp.ll
+2,849	-249	llvm/include/llvm/SandboxIR/SandboxIR.h
+3,015	-0	llvm/test/MC/Disassembler/X86/avx10.2-bf16-64.txt
+3,015	-0	llvm/test/MC/Disassembler/X86/avx10.2-bf16-32.txt
+3,014	-0	llvm/test/MC/X86/avx10.2-bf16-64-intel.s
+3,014	-0	llvm/test/MC/X86/avx10.2-bf16-32-att.s
+3,014	-0	llvm/test/MC/X86/avx10.2-bf16-32-intel.s
+3,014	-0	llvm/test/MC/X86/avx10.2-bf16-64-att.s
+935	-2,073	llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
+0	-2,999	clang/lib/AST/Interp/Interp.h
+2,982	-0	clang/lib/AST/ByteCode/Interp.h
+1,483	-1,483	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
+626	-2,277	llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
+2,899	-0	llvm/test/CodeGen/RISCV/rvv/vsaddu.ll
+2,899	-0	llvm/test/CodeGen/RISCV/rvv/vsadd.ll
+0	-2,849	llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
+0	-2,849	llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
+0	-2,837	llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
+2,831	-0	clang/test/CodeGen/X86/avx10_2ni-builtins.c
+2,828	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16-fake16.s
+0	-2,801	llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll
+0	-2,801	llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll
+1,828	-932	llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-agent.ll
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+1,368	-1,368	llvm/test/Transforms/AtomicExpand/AArch64/pcsections.ll
+2,731	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16-fake16.s
+1,852	-862	llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+1,852	-862	llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
+1,396	-1,308	llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-system.ll
+2,702	-0	llvm/test/CodeGen/RISCV/abds-neg.ll
+2,149	-500	llvm/test/CodeGen/AMDGPU/bf16.ll
+0	-2,609	llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
+1,307	-1,296	llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
+2,563	-0	llvm/test/CodeGen/LoongArch/float-imm-vldi.ll
+900	-1,660	llvm/test/Analysis/CostModel/RISCV/cast.ll
+1,276	-1,267	llvm/test/Instrumentation/MemorySanitizer/X86/mmx-intrinsics.ll
+1,489	-889	clang/test/OpenMP/target_teams_codegen.cpp
+2,344	-0	llvm/test/CodeGen/RISCV/abds.ll
+2,332	-0	llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
+1,259	-1,026	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+0	-2,284	llvm/test/CodeGen/RISCV/rv64-legal-i32/condops.ll
+2,138	-126	llvm/lib/SandboxIR/SandboxIR.cpp
+2,229	-0	llvm/test/CodeGen/RISCV/rvv/vsmul.ll
+2,173	-0	llvm/test/CodeGen/RISCV/rvv/vssub.ll
+2,173	-0	llvm/test/CodeGen/RISCV/rvv/vssubu.ll
+0	-2,166	llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
+1,458	-680	llvm/test/CodeGen/X86/scmp.ll
+0	-2,123	llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
+0	-2,123	llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
+0	-2,119	llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll
+2,082	-0	clang/test/CodeGen/X86/avx10_2bf16-builtins.c
+2,075	-0	clang/lib/Headers/avx10_2niintrin.h
+0	-2,075	llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll
+0	-2,075	llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll
+2,020	-0	llvm/test/CodeGen/RISCV/abdu-neg.ll
+0	-1,937	llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
+769	-1,153	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
+769	-1,153	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
+769	-1,153	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
+769	-1,153	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
+769	-1,153	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
+769	-1,153	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
+769	-1,153	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
+769	-1,153	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
+1,917	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_lane.ll
+1,914	-0	llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
+1,684	-224	llvm/test/CodeGen/NVPTX/bf16-instructions.ll
+1,870	-0	llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
+737	-1,105	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
+737	-1,105	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
+737	-1,105	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
+737	-1,105	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
+825	-995	llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
+905	-911	llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_float.ll
+904	-904	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
+904	-904	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
+1,786	-0	clang/lib/AST/ByteCode/InterpBuiltin.cpp
+593	-1,185	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
+593	-1,185	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
+593	-1,185	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
+593	-1,185	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
+593	-1,185	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
+593	-1,185	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
+593	-1,185	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
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+593	-1,185	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
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+593	-1,185	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
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+836	-836	clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
+836	-836	clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
+417	-1,249	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
+417	-1,249	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
+417	-1,249	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
+417	-1,249	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
+417	-1,249	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
+417	-1,249	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
+417	-1,249	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
+417	-1,249	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
+417	-1,249	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
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+824	-824	clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
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+1,054,117	-818,226	13,026 files

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