LLVM/project 7ab2024libcxx/include print, libcxx/test/libcxx/input.output/iostream.format/print.fun vprint_unicode_windows.pass.cpp vprint_unicode_posix.pass.cpp

Cleanups and improvements.
DeltaFile
+106-153libcxx/include/print
+156-0libcxx/test/std/input.output/iostream.format/print.fun/vprint_unicode_buffered.file.pass.cpp
+149-0libcxx/test/std/input.output/iostream.format/print.fun/vprint_nonunicode_buffered.file.pass.cpp
+31-18libcxx/test/libcxx/input.output/iostream.format/print.fun/vprint_unicode_windows.pass.cpp
+10-3libcxx/test/libcxx/input.output/iostream.format/print.fun/vprint_unicode_posix.pass.cpp
+0-4libcxx/test/libcxx/transitive_includes/cxx23.csv
+452-1783 files not shown
+454-1879 files

LLVM/project f13d583llvm/lib/Transforms/Vectorize VPlanUtils.cpp

[VPlan] Pass some functions directly to all_of (NFC).

Remove some unneeded lambdas.
DeltaFile
+2-4llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+2-41 files

LLVM/project 933ecf5mlir/tools/mlir-tblgen RewriterGen.cpp

[mlir] adds `[[maybe_unused]]` to variables that might not be used (#131184)

This should suppress an unused variable warning that was seemingly
pervasive.
DeltaFile
+6-6mlir/tools/mlir-tblgen/RewriterGen.cpp
+6-61 files

LLVM/project a16c225mlir/lib/Conversion/VectorToXeGPU VectorToXeGPU.cpp, mlir/test/Conversion/VectorToXeGPU contract-to-xegpu.mlir

[mlir][xegpu] Convert Vector contraction to XeGPU (#122115)

Adds pattern to lower vector.contract to XeGPU operation.
DeltaFile
+158-0mlir/test/Conversion/VectorToXeGPU/contract-to-xegpu.mlir
+44-1mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
+202-12 files

LLVM/project 6fea340libc/src/stdio/baremetal printf.cpp vprintf.cpp, libc/src/stdio/printf_core float_dec_converter_limited.h

[libc] Fix non-templated uses of `printf_core::Writer` (#131149)

Commit 598e882ee88a1e3 turned `Writer` into a template, and updated most
of the call sites that use it. But not all. The alternative FP printf
system in `float_dec_converter_limited.h` wasn't updated, and neither
was `baremetal/printf.cpp` or `baremetal/vprintf.cpp`.

This patch updates `float_dec_converter_limited.h` in the same way that
the previous commit updated `float_dec_converter.h`: propagate the
templatedness through everything in the header, so that anything using a
`Writer` at all has a `write_mode` template parameter to pass on to it.

`printf.cpp` and `vprintf.cpp` are updated in the same way that the
previous commit updated `printf_core/vfprintf_internal.h`: the
`WriteBuffer` has parameter `WriteMode::FLUSH_TO_STREAM`, and `Writer`
picks it up implicitly from that.
DeltaFile
+25-17libc/src/stdio/printf_core/float_dec_converter_limited.h
+2-1libc/src/stdio/baremetal/printf.cpp
+2-1libc/src/stdio/baremetal/vprintf.cpp
+29-193 files

LLVM/project 02575f8llvm/lib/Transforms/Vectorize VPlanRecipes.cpp VPlan.h

[VPlan] Use VPInstruction for VPScalarPHIRecipe. (NFCI) (#129767)

Now that all phi nodes manage their incoming blocks through the
VPlan-predecessors, there should be no need for having a dedicate
recipe, it should be sufficient to allow PHI opcodes in VPInstruction.

Follow-ups will also migrate VPWidenPHIRecipe and possibly others,
building on top of https://github.com/llvm/llvm-project/pull/129388.

PR: https://github.com/llvm/llvm-project/pull/129767
DeltaFile
+28-25llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+1-42llvm/lib/Transforms/Vectorize/VPlan.h
+12-8llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
+9-4llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
+6-5llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+5-3llvm/lib/Transforms/Vectorize/VPlan.cpp
+61-876 files not shown
+69-9512 files

LLVM/project ba49de6llvm/test/CodeGen/X86 call-graph-section.ll

Reorder IR metadata and rename temporary var names in test.

Created using spr 1.3.6-beta.1
DeltaFile
+18-19llvm/test/CodeGen/X86/call-graph-section.ll
+18-191 files

LLVM/project d842707llvm/test/CodeGen/X86 call-graph-section.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+18-19llvm/test/CodeGen/X86/call-graph-section.ll
+18-191 files

LLVM/project 694cfd0llvm/test/CodeGen/X86 call-graph-section.ll

Reorder IR metadata and rename temporary var names in test.

Created using spr 1.3.6-beta.1
DeltaFile
+18-19llvm/test/CodeGen/X86/call-graph-section.ll
+18-191 files

LLVM/project 6388364llvm/test/CodeGen/X86 call-graph-section.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+18-19llvm/test/CodeGen/X86/call-graph-section.ll
+18-191 files

LLVM/project 678008ellvm/test/CodeGen/X86 call-graph-section.ll

Reorder IR metadata and rename temporary var names in test.

Created using spr 1.3.6-beta.1
DeltaFile
+18-19llvm/test/CodeGen/X86/call-graph-section.ll
+18-191 files

LLVM/project e8e267elibc/utils/gpu/server rpc_server.cpp

[libc] Remove use of C++ STL features from `rpc_server.cpp` (#131169)

Summary:
This is done in preparation for making this header only so we can use it
without an object library. This will be a transient interface that
internal LLVM stuff with use. External people can use it too if they go
through the LLVM libc interface for shared stuff but there's no backward
compatibility guarantees.

Patch just cleans it up prior to the move.
DeltaFile
+111-55libc/utils/gpu/server/rpc_server.cpp
+111-551 files

LLVM/project 3bd71cblibcxx/include __bit_reference, libcxx/include/__algorithm find.h

[libc++] Fix ambiguous call in {ranges, std}::find (#122641)

This PR fixes an ambiguous call encountered when using the `std::ranges::find` or `std::find`
algorithms with `vector<bool>` with small `allocator_traits::size_type`s, an issue reported
in #122528. The ambiguity arises from integral promotions during the internal bitwise
arithmetic of the `find` algorithms when applied to `vector<bool>` with small integral
`size_type`s. This leads to multiple viable candidates for small integral types:
__libcpp_ctz(unsigned), __libcpp_ctz(unsigned long), and __libcpp_ctz(unsigned long long),
none of which represent a single best viable match, resulting in an ambiguous call error.

To resolve this, we propose invoking an internal function __countr_zero as a dispatcher
that directs the call to the appropriate overload of __libcpp_ctz. Necessary amendments
have also been made to __countr_zero.
DeltaFile
+27-11libcxx/include/__bit/countr.h
+37-1libcxx/test/std/algorithms/alg.nonmodifying/alg.find/find.pass.cpp
+36-1libcxx/test/std/algorithms/alg.nonmodifying/alg.find/ranges.find.pass.cpp
+25-5libcxx/include/__bit_reference
+15-13libcxx/test/std/utilities/template.bitset/bitset.members/left_shift_eq.pass.cpp
+5-5libcxx/include/__algorithm/find.h
+145-361 files not shown
+151-397 files

LLVM/project a3f248bclang/lib/Driver/ToolChains/Arch RISCV.cpp

[clang][driver][NFC] Remove else after return
DeltaFile
+10-12clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+10-121 files

LLVM/project e36cc43clang/lib/Driver/ToolChains/Arch RISCV.cpp, clang/test/Driver riscv-features.c

[clang][driver] Use rva22u64_v as the default march for Fuchsia targets
DeltaFile
+12-0clang/test/Driver/riscv-features.c
+4-1clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+16-12 files

LLVM/project e61859fllvm/lib/Target/RISCV RISCVInstrInfoXqci.td RISCVFeatures.td, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

[RISCV] Add Qualcomm uC Xqcili (load large immediates) extension (#130012)

The Xqcili extension includes a two instructions that load large
immediates than is available with the base RISC-V ISA.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0

This patch adds assembler only support.
DeltaFile
+46-0llvm/test/MC/RISCV/xqcili-valid.s
+32-0llvm/test/MC/RISCV/xqcili-invalid.s
+15-0llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+13-0llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+8-0llvm/lib/Target/RISCV/RISCVFeatures.td
+3-3llvm/lib/TargetParser/RISCVISAInfo.cpp
+117-37 files not shown
+132-613 files

LLVM/project c2b66ceflang/lib/Lower/OpenMP Clauses.cpp

[flang][OpenMP] Silence unused-but-set-variable message (NFC) (#130979)

DeltaFile
+1-0flang/lib/Lower/OpenMP/Clauses.cpp
+1-01 files

LLVM/project 4baf1c0libcxx/include __bit_reference, libcxx/include/__algorithm rotate.h

[libc++] Optimize ranges::rotate for vector<bool>::iterator (#121168)

This PR optimizes the performance of `std::ranges::rotate` for
`vector<bool>::iterator`. The optimization yields a performance
improvement of up to 2096x.

Closes #64038.
DeltaFile
+64-0libcxx/test/benchmarks/algorithms/modifying/rotate.bench.cpp
+4-44libcxx/include/__bit_reference
+45-0libcxx/include/__algorithm/rotate.h
+35-0libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/ranges_rotate.pass.cpp
+23-0libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/rotate.pass.cpp
+3-0libcxx/include/__fwd/bit_reference.h
+174-442 files not shown
+176-458 files

LLVM/project 369da84flang/include/flang/Lower BoxAnalyzer.h, flang/include/flang/Semantics tools.h

[flang][cuda] Allow assumed-size declaration for SHARED variable (#130833)

Avoid triggering an assertion for shared variable using the assumed-size
syntax.

```
attributes(global) subroutine sharedstar()
  real, shared :: s(*) ! ok. dynamic shared memory.
end subroutine
```
DeltaFile
+10-0flang/include/flang/Semantics/tools.h
+9-0flang/test/Lower/CUDA/cuda-shared01.cuf
+3-2flang/include/flang/Lower/BoxAnalyzer.h
+22-23 files

LLVM/project e93e0ddclang/lib/Sema SemaDeclCXX.cpp

[NFC] Fix formatting for #80963 (#131100)

This PR fixes formatting issues in `constructor-template.cpp` introduced
in #130866.

Changes:  
- Ran `clang-format` to adhere to LLVM style guidelines.  
- No functional changes.  

CC: @cor3ntin @shafik 
Thanks
DeltaFile
+1-2clang/lib/Sema/SemaDeclCXX.cpp
+1-21 files

LLVM/project 5af5fb0clang/test/C/C2y n3482.c, clang/www c_status.html

[C2y] Claim conformance to WG14 N3482

This paper makes it a constraint violation (instead of UB) to call
va_start from a function with a fixed (non-variadic) parameter list.
This is something Clang has always diagnosed as an error.
DeltaFile
+15-0clang/test/C/C2y/n3482.c
+1-1clang/www/c_status.html
+16-12 files

LLVM/project 071b6c1libcxx/include print, libcxx/include/__ostream print.h

Cleanups and improvements.
DeltaFile
+106-153libcxx/include/print
+156-0libcxx/test/std/input.output/iostream.format/print.fun/vprint_unicode_buffered.file.pass.cpp
+149-0libcxx/test/std/input.output/iostream.format/print.fun/vprint_nonunicode_buffered.file.pass.cpp
+2-2libcxx/include/__ostream/print.h
+0-4libcxx/test/libcxx/transitive_includes/cxx26.csv
+0-4libcxx/test/libcxx/transitive_includes/cxx23.csv
+413-1631 files not shown
+413-1667 files

LLVM/project d8dfdafclang/lib/Frontend CompilerInstance.cpp, llvm/include/llvm/Support AdvisoryLock.h LockFileManager.h

[Support] Introduce new `AdvisoryLock` interface (#130989)

This PR abstracts the `LockFileManager` API into new `AdvisoryLock`
interface. This is so that we can create an alternative implementation
for Clang implicitly-built modules that is optimized for single-process
environment.
DeltaFile
+58-0llvm/include/llvm/Support/AdvisoryLock.h
+11-25llvm/include/llvm/Support/LockFileManager.h
+7-7llvm/lib/Support/LockFileManager.cpp
+5-5llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
+5-5clang/lib/Frontend/CompilerInstance.cpp
+86-425 files

LLVM/project bd0d28aclang/include/clang/CIR/Dialect/IR CIRTypes.td, clang/lib/CIR/CodeGen CIRGenBuilder.h

[CIR] Upstream basic support for ArrayType (#130502)

This change adds the basic support for ArrayType

Issue #130197
DeltaFile
+51-0clang/test/CIR/IR/array.cir
+27-0clang/test/CIR/Lowering/array.cpp
+26-0clang/test/CIR/CodeGen/array.cpp
+21-2clang/include/clang/CIR/Dialect/IR/CIRTypes.td
+16-0clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+10-0clang/lib/CIR/CodeGen/CIRGenBuilder.h
+151-24 files not shown
+170-210 files

LLVM/project 7847eb0llvm/include/llvm/CodeGen MachineFunction.h, llvm/lib/IR Verifier.cpp

Remove unnecessary asserts. Remove autos for better readability.

Created using spr 1.3.6-beta.1
DeltaFile
+6-9llvm/include/llvm/CodeGen/MachineFunction.h
+4-3llvm/lib/IR/Verifier.cpp
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-1llvm/lib/Target/ARM/ARMISelLowering.cpp
+1-1llvm/lib/Target/Mips/MipsISelLowering.cpp
+13-155 files

LLVM/project 8440139llvm/include/llvm/CodeGen MachineFunction.h, llvm/lib/IR Verifier.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+6-9llvm/include/llvm/CodeGen/MachineFunction.h
+4-3llvm/lib/IR/Verifier.cpp
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-1llvm/lib/Target/ARM/ARMISelLowering.cpp
+1-1llvm/lib/Target/Mips/MipsISelLowering.cpp
+13-155 files

LLVM/project 673481ellvm/include/llvm/CodeGen MachineFunction.h, llvm/lib/IR Verifier.cpp

Remove unnecessary asserts. Remove autos for better readability.

Created using spr 1.3.6-beta.1
DeltaFile
+6-9llvm/include/llvm/CodeGen/MachineFunction.h
+4-3llvm/lib/IR/Verifier.cpp
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-1llvm/lib/Target/ARM/ARMISelLowering.cpp
+1-1llvm/lib/Target/Mips/MipsISelLowering.cpp
+13-155 files

LLVM/project eb582bdllvm/include/llvm/CodeGen MachineFunction.h, llvm/lib/IR Verifier.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+6-9llvm/include/llvm/CodeGen/MachineFunction.h
+4-3llvm/lib/IR/Verifier.cpp
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-1llvm/lib/Target/ARM/ARMISelLowering.cpp
+1-1llvm/lib/Target/Mips/MipsISelLowering.cpp
+13-155 files

LLVM/project 835c2e2llvm/include/llvm/CodeGen MachineFunction.h, llvm/lib/IR Verifier.cpp

Remove unnecessary asserts. Remove autos for better readability.

Created using spr 1.3.6-beta.1
DeltaFile
+6-9llvm/include/llvm/CodeGen/MachineFunction.h
+4-3llvm/lib/IR/Verifier.cpp
+1-1llvm/lib/Target/ARM/ARMISelLowering.cpp
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-1llvm/lib/Target/Mips/MipsISelLowering.cpp
+13-155 files

LLVM/project 607b992llvm/include/llvm/CodeGen MachineFunction.h, llvm/lib/IR Verifier.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+6-9llvm/include/llvm/CodeGen/MachineFunction.h
+4-3llvm/lib/IR/Verifier.cpp
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-1llvm/lib/Target/ARM/ARMISelLowering.cpp
+1-1llvm/lib/Target/Mips/MipsISelLowering.cpp
+13-155 files