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rebase

Created using spr 1.3.4

run 'git merge main'

[RISCV] Consolidate some DecoderNamespaces for standard extensions. (#128954)

First thing to know is that the subtarget feature checks used to block
accessing a decoder table are only a performance optimization and not
required for functionality. The tables have their own predicate checks.
I've removed them from all the standard extension tables.

-RV32 Zacas decoder namespace has been renamed to RV32GPRPair, I think
Zilsd(rv32 load/store pair) can go in here too.
-The RV32 Zdinx table has been renamed to also use RV32GPRPair.
-The Zfinx table has been renamed to remove superflous "RV" prefix.
-Zcmp and Zcmt tables have been combined into a ZcOverlap table. I think
 Zclsd(rv32 compressed load/store pair) can go in here too.
-All the extra standard extension tables are checked after the main
 standard extension table. This makes the common case of the main table
 matching occur earlier.
-Zicfiss is the exception to this as it needs to be checked before
 the main table since it overrides some encodings from Zcmop. This
can't be handled by a predicate based priority as Zicfiss only overrides
 a subset of Zcmop encodings.

fix order

Created using spr 1.3.4

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Rebase, add option

Created using spr 1.3.5

[RISCV] Add Xqccmp 0.1 Assembly Support (#128731)

Xqccmp is a new spec by Qualcomm that makes a vendor-specific effort to
solve the push/pop + frame pointers issue. Broadly, it takes the Zcmp
instructions and reverse the order they push/pop registers in, which
ends up matching the frame pointer convention.

This extension adds a new instruction not present in Zcmp,
`qc.cm.pushfp`, which will set `fp` to the incoming `sp` value after it
has pushed the registers.

This change duplicates the Zcmp implementation, with minor changes to
mnemonics (for the `qc.` prefix), predicates, and the addition of
`qc.cm.pushfp`. There is also new logic to prevent combining Xqccmp and
Zcmp. Xqccmp is kept separate to Xqci for decoding/encoding etc, as the
specs are separate today.

Specification:
https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0

Merge branch 'main' into users/mtrofin/02-25-_ctxprof_don_t_inline_weak_symbols_after_instrumentation

Fix formatting

Created using spr 1.3.5

[RISCV][MC] Add assembler support for XRivosVisni (#128773)

This implements assembler support for the XRivosVisni custom/vendor
extension from Rivos Inc. which is defined in:
https://github.com/rivosinc/rivos-custom-extensions (See
src/xrivosvisni.adoc)

Codegen support will follow in separate changes.

[RISCV] Merge some of the Sifive decoder tables. (#128794)

This makes a single table for vector and another table for system. I
left sf.cease out of system because its not in custom encoding space.
The other system instructions are in the custom part of OPC_SYSTEM.

rebase

Created using spr 1.3.4

rebase

Created using spr 1.3.4

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

[RISCV][NFC] Merge Xqci Decoder Tables (#128140)

RISC-V has multiple decoder tables because there is no guarantee that
non-standard extensions do not overlap with each other.

Qualcomm's Xqci family of extensions are intended to be implemented
together, and therefore we want a single decode table for this group of
extensions. This should be more efficient overall, and allows us to use
tablegen's existing mechanism that finds overlapping encodings within
the group.

To implement this, the key addition is `TRY_TO_DECODE_FEATURE_ANY`,
which will use the provided decoder table if any of the features from
the FeatureBitset (first argument) are enabled, rather than if all are
enabled.

[RISCV] Correctly Decode Unsigned Immediates with Ranges (#128584)

We currently have two operands upstream that are an unsigned immediate
with a range constraint - `uimm8ge32` (for `cm.jalt`) and `uimm5gt3`
(for `qc.shladd`).

Both of these were using `decodeUImmOperand<N>` for decoding. For `Zcmt`
this worked, because the generated decoder automatically checked for
`cm.jt` first because the 8 undefined bits in `cm.jalt` are `000?????`
in `cm.jt` (this is to do with the range lower-bound being a
power-of-two). For Zcmt, this patch is NFC.

We have less luck with `Xqciac` - `qc.shladd` is being decoded where the
`uimm5` field is 3 or lower. This patch fixes this by introducing a
`decodeUImmOperandGE<Width, LowerBound>` helper, which will corretly
return `MCDisassembler::Fail` when the immediate is below the lower
bound.

I have added a test to show the encoding where `uimm5` is equal to 3 is
no longer disassembled as `qc.shladd`.

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

comments

Created using spr 1.3.5-bogner

Merge branch 'main' into users/junlarsen/codegen_replace_pointertype_getunqual_type_with_opaque_pointer_version_nfc_

rebase

Created using spr 1.3.4

rebase

Created using spr 1.3.4

[RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706)

This extension adds eight 48 bit large arithmetic instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

Rebase

Created using spr 1.3.5

rebase

Created using spr 1.3.4

refactor

Created using spr 1.3.4

[RISCV] Assembler support for XRivosVizip (#127694)

This implements assembler support for the XRivosVizip custom/vendor
extension from Rivos Inc. which is defined in:
https://github.com/rivosinc/rivos-custom-extensions (See
src/xrivosvizip.adoc)

Codegen support will follow in a separate change.

[RISCV] Simplify the debug messages in the disassembler. (#128102)

Move the printing of "table" to the macro instantiation.

Don't use string concatenation in the macro. Print DESC as it own
string. This allows the "Trying " and " table:" to only appear in the
binary once instead of being part of every string.

Remove "custom opcode" from the messages, I don't think it provides much
value after mentioning the vendor.

I'm hoping to replace the macros with a table of features, decoder table
pointer, and string that we can iterate over.

Address @DavidSpickett's comment

Created using spr 1.3.5-bogner

Merge branch 'main' into users/chapuni/yaml/newgen

Conflicts:
        llvm/test/tools/llvm-cov/Inputs/branch-logical-mixed.cpp
        llvm/test/tools/llvm-cov/Inputs/branch-macros.cpp

Merge branch 'main' into users/ylzsx/r-call36