[RISCV] Add nf argument to VReg class instead overriding with a let. NFC (#131235) This treats nf consistently with LMul.
| Delta | File | |
|---|---|---|
| +11 | -12 | llvm/lib/Target/RISCV/RISCVRegisterInfo.td |
| +11 | -12 | 1 files |
[RISCV] Move Size and CopyCost overrides for vector register to the VReg class. NFC (#131222) Instead using the IsVRegClass to calculate in the base class, just override directly. This will scale better if we need to do different types of overrides for other register types in the future.
| Delta | File | |
|---|---|---|
| +3 | -3 | llvm/lib/Target/RISCV/RISCVRegisterInfo.td |
| +3 | -3 | 1 files |
[RISCV] Reorder include of RISCVInstrInfoZi* before C and Zc*. NFC (#131274) Zclsd needs to reference Zilsd in CompressPats so put Zi before Zc. The one issue I encountered is that RISCVInstrFormatsC.td needs to be included before RISCVInstrInfoZicfiss. To fix this I moved the include of RISCVInstrFormatsC.td from RISCVInstrInfoC.td to RISCVInstrInfo.td where we include RISCVInstrFormats.td. I moved RISCVInstrFormatsV.td for consistency.
| Delta | File | |
|---|---|---|
| +7 | -5 | llvm/lib/Target/RISCV/RISCVInstrInfo.td |
| +0 | -2 | llvm/lib/Target/RISCV/RISCVInstrInfoC.td |
| +0 | -2 | llvm/lib/Target/RISCV/RISCVInstrInfoV.td |
| +7 | -9 | 3 files |
[MachineCombiner][Targets] Use Register in TII genAlternativeCodeSequence interface. NFC (#131272)
[ARM] Pass ArrayRef by value instead of const reference. NFC
| Delta | File | |
|---|---|---|
| +1 | -1 | llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp |
| +1 | -1 | 1 files |
[RISCV] Shrink the size of the VLMul field in RegisterClass target flags. Use uint8_t for TSFlags. NFC (#131227) There are only 4 possible LMULs corresponding to log2 of 1, 2, 4, and 8. Those fit in 2 bits. Use uint8_t for the flag bits to match the size in TargetRegisterClass.
| Delta | File | |
|---|---|---|
| +6 | -6 | llvm/lib/Target/RISCV/RISCVRegisterInfo.h |
| +2 | -2 | llvm/lib/Target/RISCV/RISCVRegisterInfo.td |
| +8 | -8 | 2 files |
[RISCV] Remove some unnecessary hasSideEffects = 0 and sink some to their base class. NFC (#131044) Some of these were already present in their base class and therefore redundant. Others were missing from their base classes. Maybe leftover from when VXRM was modeled with side effects?
| Delta | File | |
|---|---|---|
| +11 | -23 | llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td |
| +11 | -23 | 1 files |
[RISCV][Disassembler] Use a table to store all the decoder tables and their associated features. NFC (#130883) Replace the macros with a table that we can iterate over. Use a different table for each possible instruction bitwidth.
| Delta | File | |
|---|---|---|
| +97 | -67 | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp |
| +97 | -67 | 1 files |
[RISCV] Add an error that Xqccmp, Xqciac, and Xqcicm are not compatible with C+D or Zcd. (#130816) I was reviewing encodings to put the disassembling of vendor instructions after after standard instructions and found that these overlap with c.fldsp and c.fsdsp.
| Delta | File | |
|---|---|---|
| +11 | -8 | llvm/lib/TargetParser/RISCVISAInfo.cpp |
| +8 | -0 | llvm/unittests/TargetParser/RISCVISAInfoTest.cpp |
| +19 | -8 | 2 files |
[X86][GISel] Use Register and MCRegister. NFC (#130907)
| Delta | File | |
|---|---|---|
| +12 | -12 | llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp |
| +4 | -4 | llvm/lib/Target/X86/GISel/X86CallLowering.cpp |
| +16 | -16 | 2 files |
[X86] Use Register in X86SpeculativeLoadHardening.cpp. NFC (#130905)
| Delta | File | |
|---|---|---|
| +35 | -35 | llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp |
| +35 | -35 | 1 files |
[RISCV] FeatureVendorXwchc should imply FeatureStdExtZca. (#130817) If we don't do this the binary emission won't set the compressed flag in the ELF header and won't emit alignment NOPs for R_RISCV_ALIGN correctly to support the existence of 2 byte instructions in the stream.
| Delta | File | |
|---|---|---|
| +2 | -1 | llvm/lib/Target/RISCV/RISCVFeatures.td |
| +1 | -1 | llvm/test/CodeGen/RISCV/attributes.ll |
| +3 | -2 | 2 files |
[RISCV] Move DecoderNamespace in RISCVInstrInfoXCV.td to the Instruction defs. NFC (#130800) This puts them in the same place as the Predicates. I'd like to have a single DecoderNamespace scope for all the instruction defs, but we need to reorder the classes and InstAliases away from the defs to do that.
| Delta | File | |
|---|---|---|
| +14 | -29 | llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td |
| +14 | -29 | 1 files |
[RISCV] Move let statement for hasSideEffects, mayLoad, mayStore into BranchCC_rri. NFC (#130721) This is consistent with the isBranch and isTerminator flags already in the class. Addresses feedback given on #130714 where I copied the inconsistent split into RISCVInstrInfoXCV.td.
| Delta | File | |
|---|---|---|
| +3 | -1 | llvm/lib/Target/RISCV/RISCVInstrInfo.td |
| +3 | -1 | 1 files |
[RISCV] Sink hasSideEffects, mayLoad, mayStore from defs to classes in RISCVInstrInfoXCV.td. NFC (#130714) This is consistent with how RISCVInstrInfo.td is generally structured.
| Delta | File | |
|---|---|---|
| +38 | -30 | llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td |
| +38 | -30 | 1 files |
[TableGen] Remove unnecessary const_cast and use range-based for loops. NFC (#130717) In order to use a range-based loop, I reduced a needed const_cast to only the one line that needed it.
| Delta | File | |
|---|---|---|
| +3 | -7 | llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp |
| +3 | -7 | 1 files |
[RISCV] Use inheritance to reduce duplicated code in RISCVInstrInfoXCV.td. NFC (#130703) CVSIMDRU and CVSIMDRI were the same except for immediate type. Make it a default argument of CVSIMDRI so that CVSIMDRU can inherit from it and override the argument. Similar for CVSIMDRUWb.
| Delta | File | |
|---|---|---|
| +11 | -17 | llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td |
| +11 | -17 | 1 files |
[TableGen] Reduce the number of vectors passed to getIslands. NFC (#130402) Combine the StartBits, EndBits, and FieldVals vectors into a single vector of a struct that contains all 3 pieces of information. Instead of storing EndBits, we store NumBits since that's what the users want. I've removed the BitNo variable as it was easy to construct calculate from StartBit. I've also removed Num in favor of Islands.size().
| Delta | File | |
|---|---|---|
| +26 | -42 | llvm/utils/TableGen/DecoderEmitter.cpp |
| +26 | -42 | 1 files |
[X86] Use Register in X86InstrBuilder.h. NFC (#130514) I had to give the X86AddressMode Base union a name and a constructor so it would default to Register. This means the Base.Reg = 0 in the X86AddressMode constructor is no longer needed.
| Delta | File | |
|---|---|---|
| +17 | -24 | llvm/lib/Target/X86/X86InstrBuilder.h |
| +17 | -24 | 1 files |
[RISCV] Move let Constraints closer to where outs/ins are declared in RISCVInstrInfoXCV.td. NFC The Constraint refers to the ins/outs register names so should be as close as they can be.
| Delta | File | |
|---|---|---|
| +9 | -6 | llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td |
| +9 | -6 | 1 files |
[RISCV] Reduce arguments for CVStore_rr_inc and CVStore_rr clases in RISCVInstrInfoXCV.td. NFC The ins, outs, and argstr for all instantiations of the classes are the same so just make them part of the class.
| Delta | File | |
|---|---|---|
| +19 | -37 | llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td |
| +19 | -37 | 1 files |
[RISCV] Merge DecoderNamespace for CORE-V extensions. NFC Similar to Qualcomm, Sifive, T-Head, and Rivos extensions.
| Delta | File | |
|---|---|---|
| +16 | -16 | llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td |
| +8 | -14 | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp |
| +24 | -30 | 2 files |
[RISCV] Move CV_INSERTR into the XCVbitmanip DecoderNamespace instead of the default. This uses RVInstR, while other XCVbitmanip instructions use classes that set the DecoderNamespace.
| Delta | File | |
|---|---|---|
| +1 | -0 | llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td |
| +1 | -0 | 1 files |
[RISCV] Merge DecoderNamespace for T-Head extensions. NFC (#130555) Consistent with what has been done for Rivos, SiFive, and Qualcomm extensions.
| Delta | File | |
|---|---|---|
| +17 | -24 | llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td |
| +10 | -22 | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp |
| +27 | -46 | 2 files |
[RISCV] Remove Predicates from classes in RISCVInstrInfoXTHead.td. NFC All of instantiations of these classes also specify Predicates making the base class redundant or unnecessary. The Predicates on the instantiations aren't always the same as the base class so those are needed. Also move the DecoderNamespace to the instantiations for consistency with the Predicates.
| Delta | File | |
|---|---|---|
| +19 | -19 | llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td |
| +19 | -19 | 1 files |
[X86] Use Register in FastISel. NFC Replace 'Reg == 0' with '!Reg'
| Delta | File | |
|---|---|---|
| +92 | -87 | llvm/lib/Target/X86/X86FastISel.cpp |
| +92 | -87 | 1 files |
Recommit "[ARM] Change FastISel Address from a struct to a class. NFC" With clang-format this time. Original message: This allows us to use Register in the interface, but store an unsigned internally in a union.
| Delta | File | |
|---|---|---|
| +92 | -56 | llvm/lib/Target/ARM/ARMFastISel.cpp |
| +92 | -56 | 1 files |
Revert "[ARM] Change FastISel Address from a struct to a class. NFC" This reverts commit d47bc6fd93f9f439a54fd7cf55cdcb2e2ca0cfcb. I forgot to commit clang-format cleanup before I pushed this.
| Delta | File | |
|---|---|---|
| +41 | -73 | llvm/lib/Target/ARM/ARMFastISel.cpp |
| +41 | -73 | 1 files |
[ARM] Change FastISel Address from a struct to a class. NFC This allows us to use Register in the interface, but store an unsigned internally in a union.
| Delta | File | |
|---|---|---|
| +73 | -41 | llvm/lib/Target/ARM/ARMFastISel.cpp |
| +73 | -41 | 1 files |
[AArch64] Remove unused DenseMap variable. NFC
| Delta | File | |
|---|---|---|
| +0 | -1 | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |
| +0 | -1 | 1 files |