LLVM / project - FreshBSD

LLVM/project 552f6c9 — llvm/test/CodeGen/X86 vector-interleaved-store-i8-stride-7.ll vector-interleaved-store-i16-stride-6.ll, llvm/test/Instrumentation/MemorySanitizer/AArch64 arm64-ld1.ll

users/fmayer/spr/mte-generalize-overalignment-size-of-mte-globals

rebase

Created using spr 1.3.4

Delta		File
+3,128	-3,170	llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,487	-2,510	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+2,099	-2,096	llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053	-2,052	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+3,860	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,716	-1,780	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
+15,343	-11,608	4,566 files not shown
+159,258	-104,313	4,572 files

LLVM/project e61859f — llvm/lib/Target/RISCV RISCVInstrInfoXqci.td RISCVFeatures.td, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

a day ago by u4f3 via GitHub on ⎇

users/ilovepi/driver-cleanup

[RISCV] Add Qualcomm uC Xqcili (load large immediates) extension (#130012)

The Xqcili extension includes a two instructions that load large
immediates than is available with the base RISC-V ISA.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0

This patch adds assembler only support.

Delta		File
+46	-0	llvm/test/MC/RISCV/xqcili-valid.s
+32	-0	llvm/test/MC/RISCV/xqcili-invalid.s
+15	-0	llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+13	-0	llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+8	-0	llvm/lib/Target/RISCV/RISCVFeatures.td
+3	-3	llvm/lib/TargetParser/RISCVISAInfo.cpp
+117	-3	7 files not shown
+132	-6	13 files

LLVM/project 85e290b — llvm/test/CodeGen/AMDGPU bf16.ll, llvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm60.ll

a day ago by Michael Kruse on ⎇

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'main' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,350	-4,196	llvm/test/CodeGen/AMDGPU/bf16.ll
+6,173	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0	-6,173	llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+90,478	-10,369	6,999 files not shown
+425,286	-177,378	7,005 files

LLVM/project 62e37a8 — llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

2 days ago by Craig Topper via GitHub on ⎇

main

[RISCV][Disassembler] Use a table to store all the decoder tables and their associated features. NFC (#130883)

Replace the macros with a table that we can iterate over. Use a
different table for each possible instruction bitwidth.

Delta		File
+97	-67	llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+97	-67	1 files

LLVM/project 2ece26f — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

2 days ago by prabhukr on ⎇

users/Prabhuk/sprclangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets-1

Update OB name from `type` to `callee_type`.

Created using spr 1.3.6-beta.1

Delta		File
+30,641	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+164,956	-0	24,133 files not shown
+2,356,601	-721,363	24,139 files

LLVM/project 9c94049 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

2 days ago by prabhukr on ⎇

users/Prabhuk/sprmain.clangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets-1

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+30,641	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+164,956	-0	24,129 files not shown
+2,356,435	-721,198	24,135 files

LLVM/project 05307cf — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

2 days ago by prabhukr on ⎇

users/Prabhuk/sprclangcallgraphsection-add-call-graph-section-option-and-docs

Update LTO compilation CodeGen flag for call-graph-section.

Created using spr 1.3.6-beta.1

Delta		File
+30,641	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956	-0	24,129 files not shown
+2,356,435	-721,198	24,135 files

LLVM/project de23806 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

2 days ago by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.clangcallgraphsection-add-call-graph-section-option-and-docs

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+30,641	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956	-0	24,128 files not shown
+2,356,423	-721,193	24,134 files

LLVM/project 2c57c89 — llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll

2 days ago by Helena Kotas on ⎇

users/hekota/pr-130338-remove-old-res-middle

Merge branch 'main' of https://github.com/llvm/llvm-project into remove-old-res-middle

Delta		File
+2,099	-2,096	llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053	-2,052	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434	-1,828	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+2,915	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+1,434	-1,418	llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940	-1,896	llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+10,875	-9,290	2,274 files not shown
+97,298	-62,357	2,280 files

LLVM/project ed3f871 — llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-cttz-vp.ll

3 days ago by Vitaly Buka via GitHub on ⎇

users/vitalybuka/spr/ir-optimize-cfi-in-writecombinedglobalvaluesummary

Merge branch 'main' into users/vitalybuka/spr/ir-optimize-cfi-in-writecombinedglobalvaluesummary

Delta		File
+2,099	-2,096	llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053	-2,052	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434	-1,828	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+1,434	-1,418	llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940	-1,896	llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+1,240	-1,230	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
+9,200	-10,520	1,240 files not shown
+47,494	-33,145	1,246 files

LLVM/project 397c487 — llvm/test/CodeGen/AMDGPU global_atomics_scan_fsub.ll global_atomics_scan_fadd.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-cttz-vp.ll

4 days ago by Congcong Cai on ⎇

users/ccc03-08-_astmatcher_templateargumentcountis_support_functiondecl_

Merge remote-tracking branch 'origin/main' into users/ccc03-08-_astmatcher_templateargumentcountis_support_functiondecl_

Delta		File
+1,434	-1,828	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+1,246	-1,246	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+1,246	-1,246	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+1,214	-1,214	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+1,214	-1,214	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+726	-1,509	llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
+7,080	-8,257	1,023 files not shown
+37,140	-28,442	1,029 files

LLVM/project 9b066f0 — llvm/lib/Target/RISCV RISCVInstrInfoXCV.td, llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

4 days ago by Craig Topper on ⎇

main

[RISCV] Merge DecoderNamespace for CORE-V extensions. NFC

Similar to Qualcomm, Sifive, T-Head, and Rivos extensions.

Delta		File
+16	-16	llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+8	-14	llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+24	-30	2 files

LLVM/project d72f620 — llvm/lib/Target/RISCV RISCVInstrInfoXTHead.td, llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

4 days ago by Craig Topper via GitHub on ⎇

main

[RISCV] Merge DecoderNamespace for T-Head extensions. NFC (#130555)

Consistent with what has been done for Rivos, SiFive, and Qualcomm
extensions.

Delta		File
+17	-24	llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+10	-22	llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+27	-46	2 files

LLVM/project dc66ca4 — llvm/test/CodeGen/AMDGPU llvm.amdgcn.smfmac.gfx950.ll, llvm/test/CodeGen/RISCV xqccmp-push-pop-popret.ll

4 days ago by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvfiximprove-max-safe-distance-analysis

Rebase, address comments

Created using spr 1.3.5

Delta		File
+6,173	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0	-6,173	llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+3,951	-0	llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+3,860	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,746	-1,734	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,348	-1,952	llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+17,078	-9,859	2,714 files not shown
+131,118	-67,392	2,720 files

LLVM/project 7dc7264 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

6 days ago by yangzhaoxin on ⎇

users/ylzsx/r-tls-noie

Merge branch 'main' into users/ylzsx/r-tls-noie

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+29,745	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+203,722	-0	16,100 files not shown
+2,040,184	-604,855	16,106 files

LLVM/project 2ff290b — llvm/test/CodeGen/RISCV xqccmp-push-pop-popret.ll qci-interrupt-attr.ll, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-7.ll vector-interleaved-store-i8-stride-7.ll

7 days ago by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpreduce-number-of-alternate-instruction-where-possible-1

Rebase

Created using spr 1.3.5

Delta		File
+3,951	-0	llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+3,860	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,746	-1,734	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,532	-1,534	llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,927	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+16,837	-3,268	1,830 files not shown
+73,594	-27,591	1,836 files

LLVM/project 6e7e46c — llvm/lib/Target/RISCV RISCVInstrInfoXqci.td, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

9 days ago by quic_hchandel via GitHub on ⎇

main

[RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (#129504)

This extension adds thirty eight  bit manipulation instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.6

This patch adds assembler only support.

Co-authored-by: Sudharsan Veeravalli <quic_svs at quicinc.com>

Delta		File
+539	-0	llvm/test/MC/RISCV/xqcibm-invalid.s
+123	-0	llvm/test/MC/RISCV/xqcibm-valid.s
+117	-0	llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+37	-0	llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+27	-5	llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+19	-0	llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+862	-5	9 files not shown
+891	-9	15 files

LLVM/project 8cb72bd — llvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm70.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

9 days ago by Florian Mayer on ⎇

users/fmayer/spr/mte-generalize-overalignment-size-of-mte-globals

reb

Created using spr 1.3.4

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+0	-6,173	llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+6,173	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+88,808	-6,173	3,815 files not shown
+253,453	-75,507	3,821 files

LLVM/project 8c41ae6 — lldb/tools/lldb-dap lldb-dap.cpp, llvm/test/CodeGen/AMDGPU bf16.ll

9 days ago by Michael Kruse on ⎇

users/meinersbur/flang_runtime_premerge

Merge branch 'main' into users/meinersbur/flang_runtime_premerge

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,194	-3,880	llvm/test/CodeGen/AMDGPU/bf16.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+309	-5,049	lldb/tools/lldb-dap/lldb-dap.cpp
+90,138	-8,929	5,013 files not shown
+307,445	-100,302	5,019 files

LLVM/project 5ea9c7e — clang/lib/Headers avx10_2convertintrin.h, llvm/test/Instrumentation/MemorySanitizer/AArch64 neon_vmul.ll arm64-vmul.ll

10 days ago by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpfiximprove-getspillcost-analysis

Reabse, address comments

Created using spr 1.3.5

Delta		File
+0	-6,173	llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+6,173	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+2,854	-51	clang/lib/Headers/avx10_2convertintrin.h
+0	-1,933	llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll
+1,933	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-st1.ll
+0	-1,917	llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_lane.ll
+10,960	-10,074	1,598 files not shown
+58,088	-25,827	1,604 files

LLVM/project d7bc6d6 — clang/lib/Headers avx10_2convertintrin.h, llvm/test/CodeGen/NVPTX cmpxchg-sm60.ll cmpxchg-sm70.ll

11 days ago by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvfiximprove-max-safe-distance-analysis

Rebase, address comments

Created using spr 1.3.5

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+4,730	-0	llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s
+2,854	-51	clang/lib/Headers/avx10_2convertintrin.h
+90,219	-51	2,963 files not shown
+198,153	-49,563	2,969 files

LLVM/project a97bbe6 — lldb/tools/lldb-dap lldb-dap.cpp, llvm/test/CodeGen/AMDGPU bf16.ll

13 days ago by Fangrui Song on ⎇

users/MaskRay/spr/mips-allow-expressions-in-some-immediate-operands

rebase

Created using spr 1.3.5-bogner

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,194	-3,880	llvm/test/CodeGen/AMDGPU/bf16.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+309	-5,049	lldb/tools/lldb-dap/lldb-dap.cpp
+90,138	-8,929	4,327 files not shown
+283,321	-85,441	4,333 files

LLVM/project 519ae24 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

14 days ago by NAKAMURA Takumi on ⎇

users/chapuni/mcdc/nest/trunk

Merge branch 'users/chapuni/mcdc/nest/nest-base' into users/chapuni/mcdc/nest/trunk

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782	-7,782	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,255	-7,255	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+102,453	-36,858	10,567 files not shown
+953,290	-609,134	10,573 files

LLVM/project 03c851a — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

14 days ago by NAKAMURA Takumi on ⎇

users/chapuni/mcdc/nest/nest-base

Merge branch 'users/chapuni/mcdc/nest/bitmapaddr' into users/chapuni/mcdc/nest/nest-base

Conflicts:
        clang/test/CoverageMapping/mcdc-single-cond.cpp

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782	-7,782	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255	-7,255	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+102,453	-36,858	10,567 files not shown
+953,290	-609,134	10,573 files

LLVM/project d6cb61a — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

14 days ago by NAKAMURA Takumi on ⎇

users/chapuni/mcdc/nest/bitmapaddr

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/bitmapaddr

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782	-7,782	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255	-7,255	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+102,453	-36,858	10,567 files not shown
+953,323	-609,042	10,573 files

LLVM/project 457cf4b — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

14 days ago by NAKAMURA Takumi on ⎇

users/chapuni/mcdc/nest/mcdcstate

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/mcdcstate

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782	-7,782	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255	-7,255	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+102,453	-36,858	10,567 files not shown
+953,323	-609,042	10,573 files

LLVM/project aac9c6d — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

14 days ago by NAKAMURA Takumi on ⎇

users/chapuni/mcdc/nest/lnot

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/lnot

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782	-7,782	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255	-7,255	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+102,453	-36,858	10,566 files not shown
+953,289	-609,129	10,572 files

LLVM/project e57bdcc — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

14 days ago by NAKAMURA Takumi on ⎇

users/chapuni/mcdc/nest/expect

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/expect

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782	-7,782	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,255	-7,255	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+102,453	-36,858	10,566 files not shown
+953,289	-609,129	10,572 files

LLVM/project 9a175d0 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

14 days ago by NAKAMURA Takumi on ⎇

users/chapuni/mcdc/nest/expect

Merge branch 'main' into users/chapuni/mcdc/nest/tests

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782	-7,782	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255	-7,255	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+102,453	-36,858	10,565 files not shown
+953,289	-609,032	10,571 files

LLVM/project 45f17fa — clang/lib/Headers avx10_2convertintrin.h, llvm/test/CodeGen/AMDGPU lower-buffer-fat-pointers-mem-transfer.ll buffer-fat-pointers-memcpy.ll

14 days ago by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpreduce-number-of-alternate-instruction-where-possible-1

Reabse, address comments

Created using spr 1.3.5

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+2,854	-51	clang/lib/Headers/avx10_2convertintrin.h
+1,730	-0	llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll
+779	-762	llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
+1,345	-0	llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
+421	-466	llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
+72,724	-1,279	902 files not shown
+94,704	-8,096	908 files