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author (46)
Matt Arsenault (47)
NAKAMURA Takumi (30)
Amir Ayupov (25)
Michael Kruse (22)
Necip Fazil Yildiran (18)
Alexey Bataev (14)
prabhukr (11)
Vitaly Buka (10)
Alex Richardson (9)
Paul Kirth (6)
Fangrui Song (5)
Wang Pengcheng (5)
wlei (5)
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mingmingl (4)
wanglei (4)
Florian Mayer (3)
Justin Bogner (3)
Krzysztof Parzyszek (3)
Matheus Izvekov (3)
ZhaoQi (3)
Helena Kotas (2)
Sander de Smalen (2)
Simon Pilgrim (2)
joaosaffran (2)
yangzhaoxin (2)
Aiden Grossman (1)
Alexander Richardson (1)
Andrzej Warzyński (1)
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Nikita Popov (1)
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shawbyoung (1)
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revert-107307-revert-106793-revert-106792-revert-103371-users/arsenm/atomic-expand-visit-new-blocks (2)
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users/alexey-bataev/spr/lvinitial-support-for-safe-distance-in-predicated-datawithevl-vectorization-mode (2)
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users/alexey-bataev/spr/lvenable-max-safe-distance-in-predicated-datawithevl-vectorization-mode (1)
users/alexey-bataev/spr/riscvcguse-processshufflemasks-for-per-register-shuffles-1 (1)
users/alexey-bataev/spr/riscvcodegenttiuse-processshufflemasks-for-cost-estimationsactual-per-register-shuffles (1)
users/alexey-bataev/spr/slpbetter-cost-estimation-for-masked-gather-or-clustered-loads (1)
users/alexey-bataev/spr/slpinitial-non-power-of-2-but-still-whole-register-for-remaining-nodes (1)
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users/arichardson/spr/datalayout-refactor-storage-of-non-integral-address-spaces (1)
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LLVM/project 58a8800 — llvm/test/CodeGen/AMDGPU peephole-opt-fold-reg-sequence-subreg.mir, llvm/test/CodeGen/RISCV/rvv fixed-vectors-interleaved-access.ll

by Matt Arsenault via GitHub on ⎇
PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)

This fixes the handling of subregister extract copies. This
will allow AMDGPU to remove its implementation of
shouldRewriteCopySrc, which exists as a 10 year old workaround
to this bug. peephole-opt-fold-reg-sequence-subreg.mir will
show the expected improvement once the custom implementation
is removed.

The copy coalescing processing here is overly abstracted
from what's actually happening. Previously when visiting
coalescable copy-like instructions, we would parse the
sources one at a time and then pass the def of the root
instruction into findNextSource. This means that the
first thing the new ValueTracker constructed would do
is getVRegDef to find the instruction we are currently
processing. This adds an unnecessary step, placing
a useless entry in the RewriteMap, and required skipping
the no-op case where getNewSource would return the original

    [25 lines not shown]
DeltaFile
+391-342llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
+214-338llvm/test/CodeGen/Thumb2/mve-vld3.ll
+265-280llvm/test/CodeGen/Thumb2/mve-vst3.ll
+195-197llvm/test/CodeGen/X86/avx512-ext.ll
+144-144llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
+189-0llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
+1,398-1,30198 files not shown
+2,834-2,830104 files

LLVM/project 5133ec1 — llvm/test/CodeGen/AMDGPU peephole-opt-fold-reg-sequence-subreg.mir, llvm/test/CodeGen/RISCV/rvv fixed-vectors-interleaved-access.ll

by Matt Arsenault on ⎇
PeepholeOpt: Fix looking for def of current copy to coalesce

This fixes the handling of subregister extract copies. This
will allow AMDGPU to remove its implementation of
shouldRewriteCopySrc, which exists as a 10 year old workaround
to this bug. peephole-opt-fold-reg-sequence-subreg.mir will
show the expected improvement once the custom implementation
is removed.

The copy coalescing processing here is overly abstracted
from what's actually happening. Previously when visiting
coalescable copy-like instructions, we would parse the
sources one at a time and then pass the def of the root
instruction into findNextSource. This means that the
first thing the new ValueTracker constructed would do
is getVRegDef to find the instruction we are currently
processing. This adds an unnecessary step, placing
a useless entry in the RewriteMap, and required skipping
the no-op case where getNewSource would return the original

    [26 lines not shown]
DeltaFile
+391-342llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
+214-338llvm/test/CodeGen/Thumb2/mve-vld3.ll
+265-280llvm/test/CodeGen/Thumb2/mve-vst3.ll
+195-197llvm/test/CodeGen/X86/avx512-ext.ll
+144-144llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
+189-0llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
+1,398-1,30198 files not shown
+2,830-2,828104 files

LLVM/project d975b54 — llvm/test/CodeGen/AMDGPU peephole-opt-fold-reg-sequence-subreg.mir, llvm/test/CodeGen/RISCV/rvv fixed-vectors-interleaved-access.ll

by Matt Arsenault on ⎇
PeepholeOpt: Fix looking for def of current copy to coalesce

This fixes the handling of subregister extract copies. This
will allow AMDGPU to remove its implementation of
shouldRewriteCopySrc, which exists as a 10 year old workaround
to this bug. peephole-opt-fold-reg-sequence-subreg.mir will
show the expected improvement once the custom implementation
is removed.

The copy coalescing processing here is overly abstracted
from what's actually happening. Previously when visiting
coalescable copy-like instructions, we would parse the
sources one at a time and then pass the def of the root
instruction into findNextSource. This means that the
first thing the new ValueTracker constructed would do
is getVRegDef to find the instruction we are currently
processing. This adds an unnecessary step, placing
a useless entry in the RewriteMap, and required skipping
the no-op case where getNewSource would return the original

    [26 lines not shown]
DeltaFile
+391-342llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
+214-338llvm/test/CodeGen/Thumb2/mve-vld3.ll
+265-280llvm/test/CodeGen/Thumb2/mve-vst3.ll
+204-206llvm/test/CodeGen/X86/avx512-ext.ll
+144-144llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
+189-0llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
+1,407-1,31099 files not shown
+2,841-2,839105 files

LLVM/project a897dcf — llvm/test/CodeGen/AMDGPU peephole-opt-fold-reg-sequence-subreg.mir, llvm/test/CodeGen/RISCV/rvv fixed-vectors-interleaved-access.ll

by Matt Arsenault on ⎇
PeepholeOpt: Fix looking for def of current copy to coalesce

This fixes the handling of subregister extract copies. This
will allow AMDGPU to remove its implementation of
shouldRewriteCopySrc, which exists as a 10 year old workaround
to this bug. peephole-opt-fold-reg-sequence-subreg.mir will
show the expected improvement once the custom implementation
is removed.

The copy coalescing processing here is overly abstracted
from what's actually happening. Previously when visiting
coalescable copy-like instructions, we would parse the
sources one at a time and then pass the def of the root
instruction into findNextSource. This means that the
first thing the new ValueTracker constructed would do
is getVRegDef to find the instruction we are currently
processing. This adds an unnecessary step, placing
a useless entry in the RewriteMap, and required skipping
the no-op case where getNewSource would return the original

    [26 lines not shown]
DeltaFile
+391-342llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
+214-338llvm/test/CodeGen/Thumb2/mve-vld3.ll
+265-280llvm/test/CodeGen/Thumb2/mve-vst3.ll
+204-206llvm/test/CodeGen/X86/avx512-ext.ll
+144-144llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
+189-0llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
+1,407-1,31099 files not shown
+2,841-2,839105 files

LLVM/project 3fad066 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

by Necip Fazil Yildiran via prabhukr on ⎇
Rebase on top of main.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+164,956-021,151 files not shown
+2,151,133-609,87521,157 files

LLVM/project 2d88d20 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

by Necip Fazil Yildiran via prabhukr on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-021,151 files not shown
+2,151,133-609,87521,157 files

LLVM/project f38ce99 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

by Necip Fazil Yildiran via prabhukr on ⎇
Rebase on top of main.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-021,151 files not shown
+2,151,133-609,87521,157 files

LLVM/project 67662e4 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

by Necip Fazil Yildiran via prabhukr on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+164,956-021,150 files not shown
+2,151,135-609,88221,156 files

LLVM/project 1cf40e1 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

by Necip Fazil Yildiran via prabhukr on ⎇
Rebase on top of main.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-021,149 files not shown
+2,151,129-609,86721,155 files

LLVM/project d235c0f — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

by prabhukr on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+164,956-021,149 files not shown
+2,151,129-609,86721,155 files

LLVM/project 787045d — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

by prabhukr on ⎇
Rebase on top of main.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+164,956-021,149 files not shown
+2,151,129-609,86721,155 files

LLVM/project 52efb9a — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

by prabhukr on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
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LLVM/project 1942c70 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

by prabhukr on ⎇
Rebase on top of main.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
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LLVM/project bd7bc84 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

by Roland McGrath via prabhukr on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
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LLVM/project ea2d838 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

by mingmingl on ⎇
merge with main branch
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
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+164,956-07,311 files not shown
+1,335,790-223,1007,317 files

LLVM/project 6a3c6bb — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

by Alexey Bataev on ⎇
Rebase, rework

Created using spr 1.3.5
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
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+165,052-06,598 files not shown
+1,277,792-184,4106,604 files

LLVM/project bba7783 — clang/include/clang/Basic BuiltinsX86.td, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll

by Alexey Bataev on ⎇
Rebase

Created using spr 1.3.5
DeltaFile
+4,839-5,345llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056-4,201llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
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+22,820-18,7155,948 files not shown
+312,261-154,8845,954 files

LLVM/project f4fb73a — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

by Michael Kruse on ⎇
Merge branch 'users/meinersbur/flang_runtime' into users/meinersbur/flang_runtime_shared
DeltaFile
+4,839-5,345llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056-4,201llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
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+19,871-21,1214,698 files not shown
+229,000-108,8514,704 files

LLVM/project bed5b1f — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

by Michael Kruse on ⎇
Merge branch 'users/meinersbur/flang_runtime_move-files' into users/meinersbur/flang_runtime
DeltaFile
+4,839-5,345llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056-4,201llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
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+19,871-21,1214,698 files not shown
+229,000-108,8514,704 files

LLVM/project a8c87d7 — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

by Michael Kruse on ⎇
Merge branch 'users/meinersbur/flang_runtime_flang_rt' into users/meinersbur/flang_runtime_move-files
DeltaFile
+4,839-5,345llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
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+19,871-21,1214,698 files not shown
+229,000-108,8514,704 files

LLVM/project 1f3d71e — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

by Michael Kruse on ⎇
Merge branch 'users/meinersbur/flang_runtime_FLANG_INCLUDE_RUNTIME' into users/meinersbur/flang_runtime_flang_rt
DeltaFile
+4,839-5,345llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
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+19,871-21,1214,698 files not shown
+229,000-108,8514,704 files

LLVM/project b68700b — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

by Michael Kruse on ⎇
Merge branch 'users/meinersbur/flang_runtime_Testing' into users/meinersbur/flang_runtime_FLANG_INCLUDE_RUNTIME
DeltaFile
+4,839-5,345llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056-4,201llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
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+6,647-0llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
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+19,871-21,1214,698 files not shown
+229,000-108,8514,704 files

LLVM/project f007594 — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

by Michael Kruse on ⎇
Merge branch 'users/meinersbur/flang_runtime_FortranSupport' into users/meinersbur/flang_runtime_Testing
DeltaFile
+4,839-5,345llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
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+19,871-21,1214,698 files not shown
+229,000-108,8514,704 files

LLVM/project a519f98 — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

by U-BERGUFFLEN\meinersbur on ⎇
Merge branch 'users/meinersbur/flang_runtime_FortranDecimal' into users/meinersbur/flang_runtime_FortranSupport
DeltaFile
+4,839-5,345llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
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+19,871-21,1214,698 files not shown
+229,000-108,8504,704 files

LLVM/project f2abcde — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

by Michael Kruse on ⎇
Merge branch 'main' into users/meinersbur/flang_runtime_FortranDecimal
DeltaFile
+4,839-5,345llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056-4,201llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
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+19,871-21,1214,699 files not shown
+229,007-108,8504,705 files

LLVM/project df1b617 — clang/include/clang/Basic BuiltinsX86.td, llvm/test/CodeGen/AMDGPU dagcombine-fmul-sel.ll

by ZhaoQi via GitHub on ⎇
Merge branch 'main' into users/zhaoqi5/pre-commit-tlsle-mergebaseoffset-tests
DeltaFile
+4,839-5,345llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056-4,201llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+6,647-0llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+5,378-4clang/include/clang/Basic/BuiltinsX86.td
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+3,130-1,856llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+25,717-13,9925,312 files not shown
+294,216-135,0845,318 files

LLVM/project f1a1be0 — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

by Alexey Bataev on ⎇
Rebase

Created using spr 1.3.5
DeltaFile
+4,839-5,345llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056-4,201llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+6,647-0llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
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+21,901-16,7504,167 files not shown
+210,098-98,5164,173 files

LLVM/project 31f9136 — clang/include/clang/Basic BuiltinsX86.td, llvm/test/CodeGen/AMDGPU dagcombine-fmul-sel.ll

by ZhaoQi via GitHub on ⎇
Merge branch 'main' into users/zhaoqi5/avoid-scheduling-and-attach-relax
DeltaFile
+4,839-5,345llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056-4,201llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+6,647-0llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+5,378-4clang/include/clang/Basic/BuiltinsX86.td
+2,667-2,586llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+3,130-1,856llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+25,717-13,9924,774 files not shown
+272,955-129,7234,780 files

LLVM/project 142a3ff — llvm/test/CodeGen/AArch64 bf16-v8-instructions.ll bf16-instructions.ll, llvm/test/Transforms/InstSimplify const-fold-nvvm-f2i-d2i.ll const-fold-nvvm-f2ll-d2ll.ll

by Alex Richardson on ⎇
fix bug in parsing and extend tests -- will update LangRef shortly

Created using spr 1.3.6-beta.1
DeltaFile
+697-1,151llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
+1,129-0llvm/test/Transforms/InstSimplify/const-fold-nvvm-f2i-d2i.ll
+1,129-0llvm/test/Transforms/InstSimplify/const-fold-nvvm-f2ll-d2ll.ll
+413-689llvm/test/CodeGen/AArch64/bf16-instructions.ll
+1,009-0llvm/test/tools/llvm-mca/RISCV/SiFiveP400/div.s
+539-0llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination.ll
+4,916-1,840522 files not shown
+17,058-6,744528 files

LLVM/project 1e07d91 — llvm/test/CodeGen/AArch64 bf16-v8-instructions.ll bf16-instructions.ll, llvm/test/Transforms/InstSimplify const-fold-nvvm-f2ll-d2ll.ll const-fold-nvvm-f2i-d2i.ll

by Alexander Richardson via Alex Richardson on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+697-1,151llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
+1,129-0llvm/test/Transforms/InstSimplify/const-fold-nvvm-f2ll-d2ll.ll
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+4,916-1,840520 files not shown
+17,024-6,737526 files