LLVM / project / a5a6bb3 / [𝘀𝗽𝗿] changes introduced through rebase

LLVM/project a5a6bb3 — .ci generate-buildkite-pipeline-scheduled generate-buildkite-pipeline-premerge, .github new-prs-labeler.yml CODEOWNERS

Mar 21, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/main.bolt-emit-intra-function-control-flow-in-yamlbat

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,204	-17,874	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+19,816	-19,812	llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+22,733	-6,530	llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
+21,621	-6,188	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
+21,152	-6,073	llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
+14,429	-12,423	llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
+14,732	-9,307	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+14,488	-9,192	llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+17,390	-6,049	llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
+14,349	-8,974	llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
+17,546	-5,259	llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
+12,734	-8,820	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+14,841	-6,599	llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
+15,642	-4,968	llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
+15,690	-4,843	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
+10,697	-9,165	llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
+14,974	-4,698	llvm/test/CodeGen/AMDGPU/bf16.ll
+10,032	-9,543	clang/include/clang/Sema/Sema.h
+10,574	-8,028	llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
+11,405	-7,124	llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
+10,463	-7,975	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
+8,203	-8,836	llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
+12,281	-4,041	llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
+8,793	-7,517	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
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+11,150	-4,157	llvm/test/CodeGen/RISCV/atomic-rmw.ll
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+8,773	-5,829	llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+7,998	-5,559	llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
+7,770	-5,340	llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
+7,660	-4,906	llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
+6,422	-4,492	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
+7,756	-2,894	llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
+8,044	-2,287	llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll
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+7,268	-2,452	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
+4,813	-4,813	llvm/test/CodeGen/X86/mul-i1024.ll
+6,247	-1,957	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
+3,084	-4,804	llvm/test/CodeGen/AArch64/vecreduce-add.ll
+5,745	-2,111	llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
+4,702	-3,117	llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
+5,351	-1,528	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
+4,521	-1,868	llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
+4,751	-1,501	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
+4,631	-1,357	llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
+3,441	-2,484	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
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+2,610	-2,610	llvm/test/Analysis/CostModel/X86/icmp.ll
+3,196	-1,982	llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
+3,007	-1,823	llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
+2,549	-2,270	clang/test/SemaCXX/type-traits.cpp
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+2,992	-1,691	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
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+2,586	-808	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll
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+1,284	-2,064	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
+3,235	-0	llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/neon-instructions.s
+1,240	-1,984	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
+1,144	-1,976	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
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+1,144	-1,976	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
+1,144	-1,976	clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
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