LLVM / project / 7eadc19 / [RISCV] Add a generic OOO CPU (#120712)

LLVM/project 7eadc19 — clang/docs ReleaseNotes.rst, clang/test/Misc/target-invalid-cpu-note riscv.c

Feb 14 by Pengcheng Wang via GitHub on ⎇

main

[RISCV] Add a generic OOO CPU (#120712)

We add a generic out-of-order CPU model here just like what GCC
has done.
    
People may use this model to evaluate some optimizations, and more
importantly, people can use this model as a template to customize
their own CPU models.
    
The design (units, cycles, ...) of this model is random so don't
take it seriously.

Delta		File
+562	-0	llvm/test/tools/llvm-mca/RISCV/GenericOOO/atomic.s
+499	-0	llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
+465	-0	llvm/test/tools/llvm-mca/RISCV/GenericOOO/integer.s
+438	-0	llvm/test/tools/llvm-mca/RISCV/GenericOOO/floating-point.s
+2	-0	llvm/lib/Target/RISCV/RISCVProcessors.td
+1	-1	llvm/lib/Target/RISCV/RISCV.td
+2	-0	clang/test/Misc/target-invalid-cpu-note/riscv.c
+2	-0	clang/docs/ReleaseNotes.rst
+1,971	-1	8 files

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