LLVM / project - FreshBSD

LLVM/project 552f6c9 — llvm/test/CodeGen/X86 vector-interleaved-store-i8-stride-7.ll vector-interleaved-store-i16-stride-6.ll, llvm/test/Instrumentation/MemorySanitizer/AArch64 arm64-ld1.ll

users/fmayer/spr/mte-generalize-overalignment-size-of-mte-globals

rebase

Created using spr 1.3.4

Delta		File
+3,128	-3,170	llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,487	-2,510	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+2,099	-2,096	llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053	-2,052	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+3,860	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,716	-1,780	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
+15,343	-11,608	4,566 files not shown
+159,258	-104,313	4,572 files

LLVM/project 85e290b — llvm/test/CodeGen/AMDGPU bf16.ll, llvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm70.ll

2 days ago by Michael Kruse on ⎇

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'main' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,350	-4,196	llvm/test/CodeGen/AMDGPU/bf16.ll
+6,173	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0	-6,173	llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+90,478	-10,369	6,999 files not shown
+425,286	-177,378	7,005 files

LLVM/project 2c57c89 — llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll

3 days ago by Helena Kotas on ⎇

users/hekota/pr-130338-remove-old-res-middle

Merge branch 'main' of https://github.com/llvm/llvm-project into remove-old-res-middle

Delta		File
+2,099	-2,096	llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053	-2,052	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434	-1,828	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+2,915	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+1,434	-1,418	llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940	-1,896	llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+10,875	-9,290	2,274 files not shown
+97,298	-62,357	2,280 files

LLVM/project ed3f871 — llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-cttz-vp.ll

3 days ago by Vitaly Buka via GitHub on ⎇

users/vitalybuka/spr/ir-optimize-cfi-in-writecombinedglobalvaluesummary

Merge branch 'main' into users/vitalybuka/spr/ir-optimize-cfi-in-writecombinedglobalvaluesummary

Delta		File
+2,099	-2,096	llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053	-2,052	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434	-1,828	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+1,434	-1,418	llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940	-1,896	llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+1,240	-1,230	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
+9,200	-10,520	1,240 files not shown
+47,494	-33,145	1,246 files

LLVM/project 397c487 — llvm/test/CodeGen/AMDGPU global_atomics_scan_fadd.ll global_atomics_scan_fsub.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-cttz-vp.ll

4 days ago by Congcong Cai on ⎇

users/ccc03-08-_astmatcher_templateargumentcountis_support_functiondecl_

Merge remote-tracking branch 'origin/main' into users/ccc03-08-_astmatcher_templateargumentcountis_support_functiondecl_

Delta		File
+1,434	-1,828	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+1,246	-1,246	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+1,246	-1,246	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+1,214	-1,214	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+1,214	-1,214	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+726	-1,509	llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
+7,080	-8,257	1,023 files not shown
+37,140	-28,442	1,029 files

LLVM/project 2bada41 — llvm/test/CodeGen/AMDGPU itofp.i128.ll branch-folding-implicit-def-subreg.ll

5 days ago by Matt Arsenault via GitHub on ⎇

main

StructurizeCFG: Use poison instead of undef (#130459)

There are a surprising number of codegen changes from this.

Delta		File
+132	-132	llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+99	-114	llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
+101	-99	llvm/test/CodeGen/AMDGPU/loop_break.ll
+59	-61	llvm/test/CodeGen/AMDGPU/multilevel-break.ll
+44	-34	llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
+23	-23	llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
+458	-463	20 files not shown
+591	-622	26 files

LLVM/project c2f7c83 — llvm/test/CodeGen/AMDGPU itofp.i128.ll branch-folding-implicit-def-subreg.ll

6 days ago by Matt Arsenault on ⎇

users/arsenm/structurizecfg-use-poison-instead-of-undef

StructurizeCFG: Use poison instead of undef

There are a surprising number of codegen changes from this.

Delta		File
+132	-132	llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+99	-114	llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
+101	-99	llvm/test/CodeGen/AMDGPU/loop_break.ll
+59	-61	llvm/test/CodeGen/AMDGPU/multilevel-break.ll
+44	-34	llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
+23	-23	llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
+458	-463	20 files not shown
+591	-622	26 files

LLVM/project 16e61cf — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Jan 7 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-add-riscv_atomich-and-zawrs-builtins

Rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	45,766 files not shown
+4,106,333	-2,097,168	45,772 files

LLVM/project d7d008b — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Dec 11, 2024 by Vitaly Buka via GitHub on ⎇

users/vitalybuka/spr/libclocale-update-grouping-tests

Merge branch 'main' into users/vitalybuka/spr/libclocale-update-grouping-tests

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	43,237 files not shown
+4,159,794	-2,020,023	43,243 files

LLVM/project e51ce07 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprasmprintercallgraphsection-emit-call-graph-section-4

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project 17ee91d — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.asmprintercallgraphsection-emit-call-graph-section-4

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project 4f31680 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallsiteinfocallgraphsection-extract-and-propagate-indirect-call-type-ids

Rebase on top of upstream main. Remove opt has_value, value use.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project a993e6d — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.callsiteinfocallgraphsection-extract-and-propagate-indirect-call-type-ids

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 26a149b — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallsiteinfocallgraphsection-extend-callsiteinfo-with-typeid

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 2cb9de4 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.callsiteinfocallgraphsection-extend-callsiteinfo-with-typeid

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project a3ca3e2 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprclangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 08dc8a4 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.clangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project 23ac5ef — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallgraphsection-add-call-graph-section-options-and-documentation

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project c0b6218 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by LLVM GN Syncbot via prabhukr on ⎇

users/Prabhuk/sprmain.callgraphsection-add-call-graph-section-options-and-documentation

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project 6675226 — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/test/CodeGen/AMDGPU flat_atomics_i64_system_noprivate.ll flat_atomics_i64_noprivate.ll

Nov 20, 2024 by NAKAMURA Takumi on ⎇

users/chapuni/cov/single/merge

Merge branch 'users/chapuni/cov/single/test' into users/chapuni/cov/single/merge

Delta		File
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+9,196	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
+3,630	-3,624	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,804	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+40,524	-10,845	8,255 files not shown
+418,694	-225,256	8,261 files

LLVM/project 50f8bd9 — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/include/llvm/SandboxIR SandboxIR.h

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime

Merge branch 'users/meinersbur/flang_runtime_move-files' into users/meinersbur/flang_runtime

Delta		File
+10,807	-1,742	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+6,938	-29	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+2,525	-2,525	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+0	-4,772	llvm/include/llvm/SandboxIR/SandboxIR.h
+1,064	-3,557	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+24,624	-15,915	5,001 files not shown
+234,963	-128,663	5,007 files

LLVM/project dec720f — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/include/llvm/SandboxIR SandboxIR.h

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_move-files

Merge branch 'users/meinersbur/flang_runtime_split-headers' into users/meinersbur/flang_runtime_move-files

Delta		File
+10,807	-1,742	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+6,938	-29	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+2,525	-2,525	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+0	-4,772	llvm/include/llvm/SandboxIR/SandboxIR.h
+1,064	-3,557	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+24,624	-15,915	5,000 files not shown
+234,951	-128,652	5,006 files

LLVM/project 08db098 — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/include/llvm/SandboxIR SandboxIR.h

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_split-headers2

Merge branch 'users/meinersbur/flang_runtime_split-headers' into users/meinersbur/flang_runtime_split-headers2

Delta		File
+10,807	-1,742	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+6,938	-29	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+2,525	-2,525	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+0	-4,772	llvm/include/llvm/SandboxIR/SandboxIR.h
+1,064	-3,557	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+24,624	-15,915	5,000 files not shown
+234,945	-128,653	5,006 files

LLVM/project 49b22d8 — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/include/llvm/SandboxIR SandboxIR.h

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_split-headers

Merge commit '06eb10dadfaeaadc5d0d95d38bea4bfb5253e077^' into users/meinersbur/flang_runtime_split-headers

Delta		File
+10,807	-1,742	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+6,938	-29	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+2,525	-2,525	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+0	-4,772	llvm/include/llvm/SandboxIR/SandboxIR.h
+1,064	-3,557	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+24,624	-15,915	5,000 files not shown
+234,945	-128,653	5,006 files

LLVM/project 76aaed5 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 9, 2024 by Caroline Tice on ⎇

users/cmtice/DIL-collaboration-work

Merge remote-tracking branch 'origin/main' into DIL-work-new

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	36,026 files not shown
+3,104,398	-1,498,303	36,032 files

LLVM/project 3bd1ec2 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by shawbyoung via Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-functions-with-pseudo-probes

Pseudo probe function matchign

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	20,516 files not shown
+1,508,774	-528,137	20,522 files

LLVM/project 7be0b9e — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-functions-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	20,516 files not shown
+1,508,726	-528,067	20,522 files

LLVM/project e7bce6d — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-blocks-with-pseudo-probes

address comments

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	18,744 files not shown
+1,374,895	-489,660	18,750 files

LLVM/project c84de42 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-blocks-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	18,743 files not shown
+1,374,820	-489,573	18,749 files

LLVM/project 94991b2 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Nov 7, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/bolttest-add-callcont-fallthrutest

Drop call check

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,948	-0	llvm/test/MC/AMDGPU/gfx11_asm_vopc-fake16.s
+10,486	-0	llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc-fake16.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+77,630	-4,605	13,289 files not shown
+985,511	-356,667	13,295 files