LLVM/project 7dc7264 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll
Merge branch 'main' into users/ylzsx/r-tls-noie
Merge branch 'main' into users/ylzsx/r-tls-noie
Merge branch 'users/chapuni/mcdc/nest/nest-base' into users/chapuni/mcdc/nest/trunk
Delta | File | |
---|---|---|
+65,595 | -0 | llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll |
+7,782 | -7,782 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll |
+102,453 | -36,858 | 10,567 files not shown |
+953,290 | -609,134 | 10,573 files |
Merge branch 'users/chapuni/mcdc/nest/bitmapaddr' into users/chapuni/mcdc/nest/nest-base Conflicts: clang/test/CoverageMapping/mcdc-single-cond.cpp
Delta | File | |
---|---|---|
+65,595 | -0 | llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll |
+7,782 | -7,782 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll |
+102,453 | -36,858 | 10,567 files not shown |
+953,290 | -609,134 | 10,573 files |
Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/bitmapaddr
Delta | File | |
---|---|---|
+65,595 | -0 | llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll |
+7,782 | -7,782 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll |
+102,453 | -36,858 | 10,567 files not shown |
+953,323 | -609,042 | 10,573 files |
Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/mcdcstate
Delta | File | |
---|---|---|
+65,595 | -0 | llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll |
+7,782 | -7,782 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll |
+102,453 | -36,858 | 10,567 files not shown |
+953,323 | -609,042 | 10,573 files |
Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/lnot
Delta | File | |
---|---|---|
+65,595 | -0 | llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll |
+7,782 | -7,782 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll |
+102,453 | -36,858 | 10,566 files not shown |
+953,289 | -609,129 | 10,572 files |
Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/expect
Delta | File | |
---|---|---|
+65,595 | -0 | llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll |
+7,782 | -7,782 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll |
+102,453 | -36,858 | 10,566 files not shown |
+953,289 | -609,129 | 10,572 files |
Merge branch 'main' into users/chapuni/mcdc/nest/tests
Delta | File | |
---|---|---|
+65,595 | -0 | llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll |
+7,782 | -7,782 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll |
+102,453 | -36,858 | 10,565 files not shown |
+953,289 | -609,032 | 10,571 files |
run 'git merge main'
Delta | File | |
---|---|---|
+65,595 | -0 | llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll |
+7,782 | -7,782 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll |
+102,453 | -36,858 | 8,560 files not shown |
+809,659 | -558,257 | 8,566 files |
fix order Created using spr 1.3.4
Delta | File | |
---|---|---|
+7,782 | -7,782 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll |
+43,825 | -43,825 | 7,407 files not shown |
+681,199 | -531,648 | 7,413 files |
[𝘀𝗽𝗿] changes introduced through rebase Created using spr 1.3.4 [skip ci]
Delta | File | |
---|---|---|
+7,782 | -7,782 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll |
+43,825 | -43,825 | 7,401 files not shown |
+681,165 | -531,621 | 7,407 files |
Rebase Created using spr 1.3.5
Delta | File | |
---|---|---|
+7,782 | -7,782 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll |
+43,825 | -43,825 | 4,283 files not shown |
+513,606 | -420,700 | 4,289 files |
rebase Created using spr 1.3.4
Delta | File | |
---|---|---|
+7,782 | -7,782 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll |
+43,825 | -43,825 | 4,198 files not shown |
+510,585 | -434,236 | 4,204 files |
refactor Created using spr 1.3.4
Delta | File | |
---|---|---|
+30,641 | -0 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+27,655 | -0 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+27,655 | -0 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+27,139 | -0 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+25,933 | -0 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll |
+25,933 | -0 | llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll |
+164,956 | -0 | 15,561 files not shown |
+1,914,489 | -576,768 | 15,567 files |
Address @DavidSpickett's comment Created using spr 1.3.5-bogner
Delta | File | |
---|---|---|
+7,513 | -7,513 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll |
+43,556 | -43,556 | 6,429 files not shown |
+608,030 | -497,429 | 6,435 files |
Rebase, address comments, remove some extra graph-related code Created using spr 1.3.5
Delta | File | |
---|---|---|
+2,440 | -2,400 | llvm/test/CodeGen/RISCV/atomic-rmw.ll |
+2,056 | -2,666 | llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll |
+1,891 | -2,097 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll |
+1,632 | -1,586 | llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll |
+2,330 | -0 | libc/test/src/time/strftime_test.cpp |
+861 | -804 | llvm/test/CodeGen/RISCV/rvv/expandload.ll |
+11,210 | -9,553 | 2,508 files not shown |
+128,915 | -94,898 | 2,514 files |
rebase Created using spr 1.3.4
Delta | File | |
---|---|---|
+2,440 | -2,400 | llvm/test/CodeGen/RISCV/atomic-rmw.ll |
+1,990 | -2,598 | llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll |
+1,891 | -2,097 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll |
+1,632 | -1,586 | llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll |
+2,330 | -0 | libc/test/src/time/strftime_test.cpp |
+861 | -804 | llvm/test/CodeGen/RISCV/rvv/expandload.ll |
+11,144 | -9,485 | 2,423 files not shown |
+127,695 | -92,793 | 2,429 files |
Merge branch 'users/meinersbur/flang_runtime' into users/meinersbur/flang_runtime_shared
Delta | File | |
---|---|---|
+2,440 | -2,400 | llvm/test/CodeGen/RISCV/atomic-rmw.ll |
+1,891 | -2,097 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll |
+1,632 | -1,586 | llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll |
+2,330 | -0 | libc/test/src/time/strftime_test.cpp |
+861 | -804 | llvm/test/CodeGen/RISCV/rvv/expandload.ll |
+648 | -642 | llvm/test/CodeGen/RISCV/atomic-signext.ll |
+9,802 | -7,529 | 1,075 files not shown |
+53,268 | -34,260 | 1,081 files |
Merge branch 'users/meinersbur/flang_runtime_move-files' into users/meinersbur/flang_runtime
Delta | File | |
---|---|---|
+2,440 | -2,400 | llvm/test/CodeGen/RISCV/atomic-rmw.ll |
+1,891 | -2,097 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll |
+1,632 | -1,586 | llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll |
+2,330 | -0 | libc/test/src/time/strftime_test.cpp |
+861 | -804 | llvm/test/CodeGen/RISCV/rvv/expandload.ll |
+648 | -642 | llvm/test/CodeGen/RISCV/atomic-signext.ll |
+9,802 | -7,529 | 1,064 files not shown |
+52,899 | -34,233 | 1,070 files |
Merge branch 'main' into users/meinersbur/flang_runtime_move-files
Delta | File | |
---|---|---|
+2,440 | -2,400 | llvm/test/CodeGen/RISCV/atomic-rmw.ll |
+1,891 | -2,097 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll |
+1,632 | -1,586 | llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll |
+2,330 | -0 | libc/test/src/time/strftime_test.cpp |
+861 | -804 | llvm/test/CodeGen/RISCV/rvv/expandload.ll |
+648 | -642 | llvm/test/CodeGen/RISCV/atomic-signext.ll |
+9,802 | -7,529 | 1,064 files not shown |
+52,899 | -34,233 | 1,070 files |
Merge branch 'main' into users/ylzsx/r-call36
Delta | File | |
---|---|---|
+30,641 | -0 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+27,655 | -0 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+27,655 | -0 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+27,139 | -0 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+25,933 | -0 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll |
+25,933 | -0 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll |
+164,956 | -0 | 10,990 files not shown |
+1,581,431 | -416,524 | 10,996 files |
Merge branch 'main' of https://github.com/llvm/llvm-project into cbuffer-codegen5
Delta | File | |
---|---|---|
+20,021 | -0 | llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll |
+7,513 | -7,513 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll |
+56,610 | -36,589 | 8,229 files not shown |
+698,110 | -527,440 | 8,235 files |
Merge branch 'test/adding-missing-test' into obj2yaml/root-constants
Delta | File | |
---|---|---|
+7,513 | -7,513 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll |
+7,427 | -7,427 | llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll |
+7,255 | -7,255 | llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll |
+6,967 | -6,967 | llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll |
+43,556 | -43,556 | 3,452 files not shown |
+431,676 | -408,043 | 3,458 files |
[SLP]Improved reduction cost/codegen SLP vectorizer is able to combine several reductions from the list of (potentially) reduced values with the different opcodes/values kind. Currently, these reductions are handled independently of each other. But instead the compiler can combine them into wide vector operations and then perform only single reduction. E.g, if the SLP vectorizer emits currently something like: ``` %r1 = reduce.add(<4 x i32> %v1) %r2 = reduce.add(<4 x i32> %v2) %r = add i32 %r1, %r2 ``` it can be emitted as: ``` %v = add <4 x i32> %v1, %v2 %r = reduce.add(<4 x i32> %v) ``` [80 lines not shown]
Revert "[SLP]Improved reduction cost/codegen" This reverts commit 7ec60bf0166519317b5ae2505dd6ed4660e3ea39 to fix a bug reported in https://github.com/llvm/llvm-project/issues/127220.
[SLP]Improved reduction cost/codegen SLP vectorizer is able to combine several reductions from the list of (potentially) reduced values with the different opcodes/values kind. Currently, these reductions are handled independently of each other. But instead the compiler can combine them into wide vector operations and then perform only single reduction. E.g, if the SLP vectorizer emits currently something like: ``` %r1 = reduce.add(<4 x i32> %v1) %r2 = reduce.add(<4 x i32> %v2) %r = add i32 %r1, %r2 ``` it can be emitted as: ``` %v = add <4 x i32> %v1, %v2 %r = reduce.add(<4 x i32> %v) ``` [80 lines not shown]
[SLP]Add a test with non-power-of-2 reduction for ctpop, NFC From #127177
Delta | File | |
---|---|---|
+38 | -0 | llvm/test/Transforms/SLPVectorizer/X86/ctpop-non-power-of-2-reduction.ll |
+38 | -0 | 1 files |
[SLP]Improved reduction cost/codegen SLP vectorizer is able to combine several reductions from the list of (potentially) reduced values with the different opcodes/values kind. Currently, these reductions are handled independently of each other. But instead the compiler can combine them into wide vector operations and then perform only single reduction. E.g, if the SLP vectorizer emits currently something like: ``` %r1 = reduce.add(<4 x i32> %v1) %r2 = reduce.add(<4 x i32> %v2) %r = add i32 %r1, %r2 ``` it can be emitted as: ``` %v = add <4 x i32> %v1, %v2 %r = reduce.add(<4 x i32> %v) ``` [80 lines not shown]
Revert "[SLP]Improved reduction cost/codegen" This reverts commit 7ec60bf0166519317b5ae2505dd6ed4660e3ea39 to fix a bug reported in https://github.com/llvm/llvm-project/issues/127220.
[SLP]Improved reduction cost/codegen SLP vectorizer is able to combine several reductions from the list of (potentially) reduced values with the different opcodes/values kind. Currently, these reductions are handled independently of each other. But instead the compiler can combine them into wide vector operations and then perform only single reduction. E.g, if the SLP vectorizer emits currently something like: ``` %r1 = reduce.add(<4 x i32> %v1) %r2 = reduce.add(<4 x i32> %v2) %r = add i32 %r1, %r2 ``` it can be emitted as: ``` %v = add <4 x i32> %v1, %v2 %r = reduce.add(<4 x i32> %v) ``` [80 lines not shown]