LLVM / project - FreshBSD

LLVM/project 552f6c9 — llvm/test/CodeGen/X86 vector-interleaved-store-i8-stride-7.ll vector-interleaved-store-i16-stride-6.ll, llvm/test/Instrumentation/MemorySanitizer/AArch64 arm64-ld1.ll

users/fmayer/spr/mte-generalize-overalignment-size-of-mte-globals

rebase

Created using spr 1.3.4

Delta		File
+3,128	-3,170	llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,487	-2,510	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+2,099	-2,096	llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053	-2,052	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+3,860	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,716	-1,780	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
+15,343	-11,608	4,566 files not shown
+159,258	-104,313	4,572 files

LLVM/project 85e290b — llvm/test/CodeGen/AMDGPU bf16.ll, llvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm70.ll

2 days ago by Michael Kruse on ⎇

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'main' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,350	-4,196	llvm/test/CodeGen/AMDGPU/bf16.ll
+6,173	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0	-6,173	llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+90,478	-10,369	6,999 files not shown
+425,286	-177,378	7,005 files

LLVM/project 2c57c89 — llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll

3 days ago by Helena Kotas on ⎇

users/hekota/pr-130338-remove-old-res-middle

Merge branch 'main' of https://github.com/llvm/llvm-project into remove-old-res-middle

Delta		File
+2,099	-2,096	llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053	-2,052	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434	-1,828	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+2,915	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+1,434	-1,418	llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940	-1,896	llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+10,875	-9,290	2,274 files not shown
+97,298	-62,357	2,280 files

LLVM/project ed3f871 — llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-cttz-vp.ll

3 days ago by Vitaly Buka via GitHub on ⎇

users/vitalybuka/spr/ir-optimize-cfi-in-writecombinedglobalvaluesummary

Merge branch 'main' into users/vitalybuka/spr/ir-optimize-cfi-in-writecombinedglobalvaluesummary

Delta		File
+2,099	-2,096	llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053	-2,052	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434	-1,828	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+1,434	-1,418	llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940	-1,896	llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+1,240	-1,230	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
+9,200	-10,520	1,240 files not shown
+47,494	-33,145	1,246 files

LLVM/project 397c487 — llvm/test/CodeGen/AMDGPU global_atomics_scan_fadd.ll global_atomics_scan_fsub.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-cttz-vp.ll

4 days ago by Congcong Cai on ⎇

users/ccc03-08-_astmatcher_templateargumentcountis_support_functiondecl_

Merge remote-tracking branch 'origin/main' into users/ccc03-08-_astmatcher_templateargumentcountis_support_functiondecl_

Delta		File
+1,434	-1,828	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+1,246	-1,246	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+1,246	-1,246	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+1,214	-1,214	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+1,214	-1,214	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+726	-1,509	llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
+7,080	-8,257	1,023 files not shown
+37,140	-28,442	1,029 files

LLVM/project fa315ec — llvm/test/CodeGen/RISCV/rvv fixed-vectors-cttz-vp.ll cttz-vp.ll

4 days ago by Philip Reames via GitHub on ⎇

main

[RISCV] Convert vsub.vx to vadd.vi if possible (#130669)

We'd already had this transform for the intrinsics, but hadn't added it
for either fixed length or scalable vectors coming from normal IR.

For the record, the fact we have three different sets of patterns here
really is quite ugly.

Delta		File
+1,098	-1,174	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+568	-640	llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
+264	-316	llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
+24	-44	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
+12	-18	llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
+8	-12	llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
+1,974	-2,204	8 files not shown
+2,022	-2,237	14 files

LLVM/project af42b11 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

19 days ago by Vitaly Buka on ⎇

users/vitalybuka/spr/ubsan-remove-fsanitizervptr-from-fsanitizerundefined

rebase

Created using spr 1.3.4

Delta		File
+7,782	-7,782	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255	-7,255	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+43,825	-43,825	4,198 files not shown
+510,585	-434,236	4,204 files

LLVM/project e157634 — libc/test/src/time strftime_test.cpp, llvm/test/CodeGen/RISCV atomic-rmw.ll

24 days ago by Alexey Bataev on ⎇

users/alexey-bataev/spr/slprepresent-slp-graph-as-a-tree

Rebase, address comments, remove some extra graph-related code

Created using spr 1.3.5

Delta		File
+2,440	-2,400	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+2,056	-2,666	llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
+1,891	-2,097	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,632	-1,586	llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+2,330	-0	libc/test/src/time/strftime_test.cpp
+861	-804	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+11,210	-9,553	2,508 files not shown
+128,915	-94,898	2,514 files

LLVM/project ffab4ee — libc/test/src/time strftime_test.cpp, llvm/test/CodeGen/RISCV atomic-rmw.ll

24 days ago by Vitaly Buka on ⎇

revert-127076-revert-125020-users/vitalybuka/spr/libclang-always-dup-in-createref

rebase

Created using spr 1.3.4

Delta		File
+2,440	-2,400	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+1,990	-2,598	llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
+1,891	-2,097	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,632	-1,586	llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+2,330	-0	libc/test/src/time/strftime_test.cpp
+861	-804	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+11,144	-9,485	2,423 files not shown
+127,695	-92,793	2,429 files

LLVM/project d9751a3 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

25 days ago by NAKAMURA Takumi on ⎇

users/chapuni/yaml/newgen

Merge branch 'main' into users/chapuni/yaml/newgen

Conflicts:
        llvm/test/tools/llvm-cov/Inputs/branch-logical-mixed.cpp
        llvm/test/tools/llvm-cov/Inputs/branch-macros.cpp

Delta		File
+30,641	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+164,956	-0	30,003 files not shown
+3,294,806	-1,187,822	30,009 files

LLVM/project 02ecc27 — libc/test/src/time strftime_test.cpp, llvm/test/CodeGen/RISCV atomic-rmw.ll atomic-signext.ll

26 days ago by Michael Kruse on ⎇

users/meinersbur/flang_runtime_shared

Merge branch 'users/meinersbur/flang_runtime' into users/meinersbur/flang_runtime_shared

Delta		File
+2,440	-2,400	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+1,891	-2,097	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,632	-1,586	llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+2,330	-0	libc/test/src/time/strftime_test.cpp
+861	-804	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+648	-642	llvm/test/CodeGen/RISCV/atomic-signext.ll
+9,802	-7,529	1,075 files not shown
+53,268	-34,260	1,081 files

LLVM/project 6fa8982 — libc/test/src/time strftime_test.cpp, llvm/test/CodeGen/RISCV atomic-rmw.ll atomic-signext.ll

27 days ago by Michael Kruse on ⎇

users/meinersbur/flang_runtime

Merge branch 'users/meinersbur/flang_runtime_move-files' into users/meinersbur/flang_runtime

Delta		File
+2,440	-2,400	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+1,891	-2,097	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,632	-1,586	llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+2,330	-0	libc/test/src/time/strftime_test.cpp
+861	-804	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+648	-642	llvm/test/CodeGen/RISCV/atomic-signext.ll
+9,802	-7,529	1,064 files not shown
+52,899	-34,233	1,070 files

LLVM/project c2c7bb2 — libc/test/src/time strftime_test.cpp, llvm/test/CodeGen/RISCV atomic-rmw.ll atomic-signext.ll

27 days ago by Michael Kruse on ⎇

users/meinersbur/flang_runtime

Merge branch 'main' into users/meinersbur/flang_runtime_move-files

Delta		File
+2,440	-2,400	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+1,891	-2,097	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,632	-1,586	llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+2,330	-0	libc/test/src/time/strftime_test.cpp
+861	-804	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+648	-642	llvm/test/CodeGen/RISCV/atomic-signext.ll
+9,802	-7,529	1,064 files not shown
+52,899	-34,233	1,070 files

LLVM/project c1cc655 — llvm/test/CodeGen/RISCV atomic-rmw.ll atomic-signext.ll, llvm/test/CodeGen/RISCV/GlobalISel wide-scalar-shift-by-byte-multiple-legalization.ll

29 days ago by Philip Reames via joaosaffran on ⎇

users/joaosaffran/123147

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

This reverts commit 9cc8442a2b438962883bbbfd8ff62ad4b1a2b95d.
This reverts commit 859c871184bdfdebb47b5c7ec5e59348e0534e0b.

A performance regression was reported on the original review.  There appears
to have been an unexpected interaction here.  Reverting during investigation.

Delta		File
+2,440	-2,400	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+1,891	-2,097	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,632	-1,586	llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+861	-804	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+648	-642	llvm/test/CodeGen/RISCV/atomic-signext.ll
+639	-582	llvm/test/CodeGen/RISCV/pr69586.ll
+8,111	-8,111	399 files not shown
+29,828	-28,652	405 files

LLVM/project 8191357 — llvm/test/CodeGen/RISCV atomic-rmw.ll atomic-signext.ll, llvm/test/CodeGen/RISCV/GlobalISel wide-scalar-shift-by-byte-multiple-legalization.ll

29 days ago by Philip Reames via joaosaffran on ⎇

users/joaosaffran/123147

[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)

This change introduces a default schedule model for the RISCV target
which leaves everything unchanged except the MicroOpBufferSize. The
default value of this flag in NoSched is 0. Both configurations
represent in order cores (i.e. no reorder window), the difference
between them comes down to whether heuristics other than latency are
allowed to apply. (Implementation details below)

I left the processor models which explicitly set MicroOpBufferSize=0
unchanged in this patch, but strongly suspect we should change those
too. Honestly, I think the LLVM wide default for this flag should be
changed, but don't have the energy to manage the updates for all
targets.

Implementation wise, the effect of this change is that schedule units
which are ready to run *except that* one of their predecessors may not
have completed yet are added to the Available list, not the Pending one.
The result of this is that it becomes possible to chose to schedule a

    [18 lines not shown]

Delta		File
+2,400	-2,440	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+2,237	-2,031	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,572	-1,618	llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+794	-851	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+642	-648	llvm/test/CodeGen/RISCV/atomic-signext.ll
+586	-643	llvm/test/CodeGen/RISCV/pr69586.ll
+8,231	-8,231	397 files not shown
+28,727	-29,913	403 files

LLVM/project 113d413 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

Feb 13 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'users/meinersbur/flang_runtime_shared' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Delta		File
+7,513	-7,513	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,255	-7,255	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+43,556	-43,556	1,183 files not shown
+355,173	-350,599	1,189 files

LLVM/project 0f208a4 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

Feb 13 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_shared

Merge branch 'users/meinersbur/flang_runtime' into users/meinersbur/flang_runtime_shared

Delta		File
+7,513	-7,513	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,255	-7,255	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+43,556	-43,556	1,183 files not shown
+355,173	-350,599	1,189 files

LLVM/project ff761f6 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

Feb 13 by Michael Kruse on ⎇

users/meinersbur/flang_runtime

Merge branch 'users/meinersbur/flang_runtime_move-files' into users/meinersbur/flang_runtime

Delta		File
+7,513	-7,513	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255	-7,255	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+43,556	-43,556	1,183 files not shown
+355,173	-350,599	1,189 files

LLVM/project b12d925 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

Feb 13 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_move-files

Merge commit '660cdace559a8dbe44ebf2222b854bf3f39a5f62' into users/meinersbur/flang_runtime_move-files

Delta		File
+7,513	-7,513	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255	-7,255	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+43,556	-43,556	1,183 files not shown
+355,173	-350,599	1,189 files

LLVM/project 059722d — llvm/test/CodeGen/RISCV atomic-rmw.ll atomic-signext.ll, llvm/test/CodeGen/RISCV/GlobalISel wide-scalar-shift-by-byte-multiple-legalization.ll

Feb 13 by Philip Reames on ⎇

main

Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

This reverts commit 9cc8442a2b438962883bbbfd8ff62ad4b1a2b95d.
This reverts commit 859c871184bdfdebb47b5c7ec5e59348e0534e0b.

A performance regression was reported on the original review.  There appears
to have been an unexpected interaction here.  Reverting during investigation.

Delta		File
+2,440	-2,400	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+1,891	-2,097	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,632	-1,586	llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+861	-804	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+648	-642	llvm/test/CodeGen/RISCV/atomic-signext.ll
+639	-582	llvm/test/CodeGen/RISCV/pr69586.ll
+8,111	-8,111	399 files not shown
+29,828	-28,652	405 files

LLVM/project f0b3fbd — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

Feb 13 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slprepresent-slp-graph-as-a-tree

Rebase

Created using spr 1.3.5

Delta		File
+7,513	-7,513	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,427	-7,427	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,255	-7,255	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+6,967	-6,967	llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+43,556	-43,556	1,547 files not shown
+371,601	-354,865	1,553 files

LLVM/project a63f09e — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

Feb 13 by Vitaly Buka on ⎇

users/vitalybuka/spr/ubsan-remove-fsanitizervptr-from-fsanitizerundefined

rebase

Created using spr 1.3.4

Delta		File
+30,641	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+164,956	-0	14,444 files not shown
+1,781,638	-474,012	14,450 files

LLVM/project f4d53b4 — clang/lib/CodeGen CGObjCMac.cpp, llvm/test/CodeGen/AArch64/Atomics aarch64_be-atomicrmw-lsfe.ll

Feb 13 by Vitaly Buka on ⎇

users/vitalybuka/spr/libclang-replace-createref-with-createdup

relnote

Created using spr 1.3.4

Delta		File
+2,400	-2,440	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+2,237	-2,031	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,572	-1,618	llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+2,764	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions/cl_khr_extended_bit_ops.ll
+1,049	-1,175	clang/lib/CodeGen/CGObjCMac.cpp
+1,984	-0	llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lsfe.ll
+12,006	-7,264	1,200 files not shown
+59,235	-40,600	1,206 files

LLVM/project c5e9141 — clang/lib/CodeGen CGObjCMac.cpp, llvm/test/CodeGen/AArch64/Atomics aarch64_be-atomicrmw-v8a_fp.ll

Feb 13 by Vitaly Buka on ⎇

users/vitalybuka/spr/main.libclang-replace-createref-with-createdup

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+2,400	-2,440	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+2,237	-2,031	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,572	-1,618	llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+2,764	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions/cl_khr_extended_bit_ops.ll
+1,049	-1,175	clang/lib/CodeGen/CGObjCMac.cpp
+1,984	-0	llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a_fp.ll
+12,006	-7,264	1,200 files not shown
+59,235	-40,600	1,206 files

LLVM/project 859c871 — llvm/test/CodeGen/RISCV atomic-rmw.ll atomic-signext.ll, llvm/test/CodeGen/RISCV/GlobalISel wide-scalar-shift-by-byte-multiple-legalization.ll

Feb 12 by Philip Reames via GitHub on ⎇

main

[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)

This change introduces a default schedule model for the RISCV target
which leaves everything unchanged except the MicroOpBufferSize. The
default value of this flag in NoSched is 0. Both configurations
represent in order cores (i.e. no reorder window), the difference
between them comes down to whether heuristics other than latency are
allowed to apply. (Implementation details below)

I left the processor models which explicitly set MicroOpBufferSize=0
unchanged in this patch, but strongly suspect we should change those
too. Honestly, I think the LLVM wide default for this flag should be
changed, but don't have the energy to manage the updates for all
targets.

Implementation wise, the effect of this change is that schedule units
which are ready to run *except that* one of their predecessors may not
have completed yet are added to the Available list, not the Pending one.
The result of this is that it becomes possible to chose to schedule a

    [18 lines not shown]

Delta		File
+2,400	-2,440	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+2,237	-2,031	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,572	-1,618	llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+794	-851	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+642	-648	llvm/test/CodeGen/RISCV/atomic-signext.ll
+586	-643	llvm/test/CodeGen/RISCV/pr69586.ll
+8,231	-8,231	397 files not shown
+28,727	-29,913	403 files

LLVM/project 16e61cf — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Jan 7 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-add-riscv_atomich-and-zawrs-builtins

Rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	45,766 files not shown
+4,106,333	-2,097,168	45,772 files

LLVM/project df9bdfe — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Jan 3 by Alex Richardson on ⎇

users/arichardson/spr/datalayoutlangref-split-non-integral-and-unstable-pointer-properties

split out the external state property based on discourse discussion

Created using spr 1.3.6-beta.1

Delta		File
+16,880	-2,842	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+19,618	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+12,081	-2,343	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+13,103	-0	clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
+79,100	-22,603	22,891 files not shown
+1,488,029	-919,945	22,897 files

LLVM/project 9c2aecb — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Jan 3 by Min-Yih Hsu via Alex Richardson on ⎇

users/arichardson/spr/main.datalayoutlangref-split-non-integral-and-unstable-pointer-properties

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+16,880	-2,842	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+19,618	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+12,081	-2,343	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+0	-13,103	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+65,997	-35,706	22,890 files not shown
+1,487,884	-919,891	22,896 files

LLVM/project d1e961e — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Dec 21, 2024 by NAKAMURA Takumi on ⎇

users/chapuni/cov/single/trunk

Merge branch 'users/chapuni/cov/single/binop' into users/chapuni/cov/single/trunk

Delta		File
+16,880	-2,842	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+19,618	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,081	-2,343	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,046	-22,603	23,484 files not shown
+1,825,881	-939,357	23,490 files

LLVM/project cb3ff1f — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Dec 21, 2024 by NAKAMURA Takumi on ⎇

users/chapuni/cov/single/switch

Merge branch 'users/chapuni/cov/single/base' into users/chapuni/cov/single/switch

Delta		File
+16,880	-2,842	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+19,618	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,081	-2,343	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,046	-22,603	23,484 files not shown
+1,825,881	-939,357	23,490 files