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[AMDGPU][True16][CodeGen] enable true16 for more codegen test patch 2 (#131210)

This is a NFC patch.

Enable true16 mode for more CodeGen tests

rebase

Created using spr 1.3.4

[AMDGPU][RegBankCombiner] Add cast_of_cast and constant_fold_cast combines

We can add a bunch of exts/truncs during RBSelect, we should be able to fold
them away afterwards.

[AMDGPU][RegBankCombiner] Add cast_of_cast and constant_fold_cast combines

We can add a bunch of exts/truncs during RBSelect, we should be able to fold
them away afterwards.

Merge branch 'main' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Update OB name from `type` to `callee_type`.

Created using spr 1.3.6-beta.1

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Update LTO compilation CodeGen flag for call-graph-section.

Created using spr 1.3.6-beta.1

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Merge branch 'main' of https://github.com/llvm/llvm-project into remove-old-res-middle

AMDGPU: Replace insertelement poison with insertelement undef (#130896)

This is the bulk update with perl, with cases which require additional
update left for later.

AMDGPU: Replace insertelement poison with insertelement undef

This is the bulk update with perl, with cases which require additional
update left for later.

AMDGPU: Replace insertelement poison with insertelement undef

This is the bulk update with perl, with cases which require additional
update left for later.

AMDGPU: Replace insertelement poison with insertelement undef

This is the bulk update with perl, with cases which require additional
update left for later.

AMDGPU: Replace insertelement poison with insertelement undef

This is the bulk update with perl, with cases which require additional
update left for later.

Rebase, address comments

Created using spr 1.3.5

reb

Created using spr 1.3.4

Rebase, address comments

Created using spr 1.3.5

Reabse, address comments

Created using spr 1.3.5

[AMDGPU] Account for existing SDWA selections  (#123221)

The si-peephole-sdwa pass adjusts the selections on sdwa instructions to
the selections on their operands during its conversions. For instance,
if an instruction selects `BYTE_0` and its operand selects `WORD_1`, the
combined selection should be `BYTE_2`, i.e. "`BYTE_0` of `WORD_1`". The
existing implementation does not always handle this correctly in some
complex situations with instructions across different basic blocks as
demonstrated by the test cases included in this PR.

This PR adds an additional selection combination step to the conversion
to fix this issue. It reverts the changes made by PR #123942 which had
disabled the conversion of preexisting SDWA instructions completely as a
quick fix.

---------

Co-authored-by: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>

refactor

Created using spr 1.3.4

Merge branch 'main' into users/chapuni/yaml/newgen

Conflicts:
        llvm/test/tools/llvm-cov/Inputs/branch-logical-mixed.cpp
        llvm/test/tools/llvm-cov/Inputs/branch-macros.cpp

Merge branch 'main' into users/ylzsx/r-call36

rebase

Created using spr 1.3.4

Merge branch 'main' into users/zhaoqi5/opt-tlsle-mergebaseoffset

Merge branch 'main' into users/joaosaffran/123147

rebase and add test

Created using spr 1.3.5-bogner

Merge branch 'main' into users/kparzysz/spr/m06-dirspec-args

Merge branch 'main' into users/kparzysz/spr/m05-spec-todo

Merge branch 'main' into mlir-call-attrs-llvm