LLVM / project - FreshBSD

LLVM/project 552f6c9 — llvm/test/CodeGen/X86 vector-interleaved-store-i8-stride-7.ll vector-interleaved-store-i16-stride-6.ll, llvm/test/Instrumentation/MemorySanitizer/AArch64 arm64-ld1.ll

users/fmayer/spr/mte-generalize-overalignment-size-of-mte-globals

rebase

Created using spr 1.3.4

Delta		File
+3,128	-3,170	llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,487	-2,510	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+2,099	-2,096	llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053	-2,052	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+3,860	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,716	-1,780	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
+15,343	-11,608	4,566 files not shown
+159,258	-104,313	4,572 files

LLVM/project ac94ccd — llvm/test/CodeGen/AMDGPU merge-flat-load-store.mir merge-flat-with-global-load-store.mir

16 hours ago by Matt Arsenault via GitHub on ⎇

main

AMDGPU: Replace undef references with poison in some MIR tests (#131254)

Delta		File
+105	-105	llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
+31	-31	llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
+20	-20	llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
+20	-20	llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
+11	-11	llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
+9	-9	llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
+196	-196	5 files not shown
+211	-211	11 files

LLVM/project 2e03138 — llvm/test/CodeGen/AMDGPU merge-flat-load-store.mir merge-flat-with-global-load-store.mir

19 hours ago by Matt Arsenault on ⎇

users/arsenm/amdgpu/replace-undef-uses-with-poison-mir

AMDGPU: Replace undef references with poison in some MIR tests

Delta		File
+105	-105	llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
+31	-31	llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
+20	-20	llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
+20	-20	llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
+11	-11	llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
+9	-9	llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
+196	-196	5 files not shown
+211	-211	11 files

LLVM/project a9ed4e3 — llvm/test/CodeGen/AMDGPU merge-flat-load-store.mir merge-flat-with-global-load-store.mir

21 hours ago by Matt Arsenault on ⎇

users/arsenm/amdgpu/replace-undef-uses-with-poison-mir

AMDGPU: Replace undef references with poison in some MIR tests

Delta		File
+105	-105	llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
+31	-31	llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
+20	-20	llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
+20	-20	llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
+11	-11	llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
+9	-9	llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
+196	-196	5 files not shown
+211	-211	11 files

LLVM/project 06c379a — llvm/test/CodeGen/AMDGPU merge-global-load-store.mir fold-imm-f16-f32.mir

21 hours ago by Matt Arsenault via GitHub on ⎇

main

AMDGPU: Replace more undef test pointer uses with poison (#131102)

Delta		File
+179	-179	llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
+85	-85	llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
+32	-32	llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
+29	-29	llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
+417	-417	12 files not shown
+480	-480	18 files

LLVM/project 87664c3 — llvm/test/CodeGen/AMDGPU merge-global-load-store.mir fold-imm-f16-f32.mir

21 hours ago by Matt Arsenault on ⎇

users/arsenm/amdgpu/tests-replace-more-undef-ptr-with-poison

AMDGPU: Replace more undef test pointer uses with poison

Delta		File
+179	-179	llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
+85	-85	llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
+32	-32	llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
+29	-29	llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
+417	-417	12 files not shown
+480	-480	18 files

LLVM/project 7251260 — llvm/test/CodeGen/AMDGPU merge-global-load-store.mir fold-imm-f16-f32.mir

23 hours ago by Matt Arsenault on ⎇

users/arsenm/amdgpu/tests-replace-more-undef-ptr-with-poison

AMDGPU: Replace more undef test pointer uses with poison

Delta		File
+179	-179	llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
+85	-85	llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
+32	-32	llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
+29	-29	llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
+417	-417	12 files not shown
+480	-480	18 files

LLVM/project 1e888ed — llvm/test/CodeGen/AMDGPU merge-global-load-store.mir fold-imm-f16-f32.mir

a day ago by Matt Arsenault on ⎇

users/arsenm/amdgpu/tests-replace-more-undef-ptr-with-poison

AMDGPU: Replace more undef test pointer uses with poison

Delta		File
+179	-179	llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
+85	-85	llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
+32	-32	llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
+29	-29	llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
+417	-417	12 files not shown
+480	-480	18 files

LLVM/project 2e4885a — llvm/test/CodeGen/AMDGPU merge-global-load-store.mir fold-imm-f16-f32.mir

2 days ago by Matt Arsenault on ⎇

users/arsenm/amdgpu/tests-replace-more-undef-ptr-with-poison

AMDGPU: Replace more undef test pointer uses with poison

Delta		File
+179	-179	llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
+85	-85	llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
+32	-32	llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
+29	-29	llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
+417	-417	12 files not shown
+480	-480	18 files

LLVM/project dac4c0e — llvm/test/CodeGen/AMDGPU merge-global-load-store.mir fold-imm-f16-f32.mir

2 days ago by Matt Arsenault on ⎇

users/arsenm/amdgpu/tests-replace-more-undef-ptr-with-poison

AMDGPU: Replace more undef test pointer uses with poison

Delta		File
+179	-179	llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
+85	-85	llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
+32	-32	llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
+29	-29	llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
+417	-417	12 files not shown
+480	-480	18 files

LLVM/project a0de19d — llvm/test/CodeGen/AMDGPU merge-global-load-store.mir fold-imm-f16-f32.mir

2 days ago by Matt Arsenault on ⎇

users/arsenm/amdgpu/tests-replace-more-undef-ptr-with-poison

AMDGPU: Replace more undef test pointer uses with poison

Delta		File
+179	-179	llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
+85	-85	llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
+32	-32	llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
+29	-29	llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
+417	-417	12 files not shown
+480	-480	18 files

LLVM/project a20e042 — llvm/test/CodeGen/AMDGPU merge-global-load-store.mir fold-imm-f16-f32.mir

2 days ago by Matt Arsenault on ⎇

users/arsenm/amdgpu/tests-replace-more-undef-ptr-with-poison

AMDGPU: Replace more undef test pointer uses with poison

Delta		File
+179	-179	llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
+85	-85	llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
+46	-46	llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
+32	-32	llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
+29	-29	llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
+417	-417	13 files not shown
+481	-481	19 files

LLVM/project 16e61cf — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Jan 7 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-add-riscv_atomich-and-zawrs-builtins

Rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	45,766 files not shown
+4,106,333	-2,097,168	45,772 files

LLVM/project d7d008b — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Dec 11, 2024 by Vitaly Buka via GitHub on ⎇

users/vitalybuka/spr/libclocale-update-grouping-tests

Merge branch 'main' into users/vitalybuka/spr/libclocale-update-grouping-tests

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	43,237 files not shown
+4,159,794	-2,020,023	43,243 files

LLVM/project e51ce07 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprasmprintercallgraphsection-emit-call-graph-section-4

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project 17ee91d — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.asmprintercallgraphsection-emit-call-graph-section-4

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project 4f31680 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallsiteinfocallgraphsection-extract-and-propagate-indirect-call-type-ids

Rebase on top of upstream main. Remove opt has_value, value use.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project a993e6d — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.callsiteinfocallgraphsection-extract-and-propagate-indirect-call-type-ids

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 26a149b — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallsiteinfocallgraphsection-extend-callsiteinfo-with-typeid

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 2cb9de4 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.callsiteinfocallgraphsection-extend-callsiteinfo-with-typeid

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project a3ca3e2 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprclangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 08dc8a4 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.clangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project 23ac5ef — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallgraphsection-add-call-graph-section-options-and-documentation

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project c0b6218 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by LLVM GN Syncbot via prabhukr on ⎇

users/Prabhuk/sprmain.callgraphsection-add-call-graph-section-options-and-documentation

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project 0a0c824 — llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll

Nov 15, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/flang_runtime

Merge branch 'users/meinersbur/flang_runtime_move-files' into users/meinersbur/flang_runtime

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+58,428	-8,569	4,153 files not shown
+268,225	-99,256	4,159 files

LLVM/project 02812d5 — llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_move-files

Merge branch 'users/meinersbur/flang_runtime_split-headers2' into users/meinersbur/flang_runtime_move-files

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+58,428	-8,569	4,135 files not shown
+268,162	-99,193	4,141 files

LLVM/project 9118d19 — llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_split-headers2

Merge branch 'users/meinersbur/flang_runtime_split-headers' into users/meinersbur/flang_runtime_split-headers2

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+58,428	-8,569	4,127 files not shown
+268,062	-99,143	4,133 files

LLVM/project 7a08438 — llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_split-headers

Merge commit 'fa627d98e87504b6f6d621a7dab5d140340ed760^' into users/meinersbur/flang_runtime_split-headers

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+58,428	-8,569	4,127 files not shown
+268,062	-99,143	4,133 files

LLVM/project 76aaed5 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 9, 2024 by Caroline Tice on ⎇

users/cmtice/DIL-collaboration-work

Merge remote-tracking branch 'origin/main' into DIL-work-new

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	36,026 files not shown
+3,104,398	-1,498,303	36,032 files

LLVM/project 3bd1ec2 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by shawbyoung via Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-functions-with-pseudo-probes

Pseudo probe function matchign

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	20,516 files not shown
+1,508,774	-528,137	20,522 files