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rebase

Created using spr 1.3.4

Merge branch 'main' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'main' of https://github.com/llvm/llvm-project into remove-old-res-middle

AMDGPU: Replace undef with poison in tests using insertvalue (#130895)

perl -p -i -e 's/insertvalue (.*) undef/insertvalue \1 poison/g'

AMDGPU: Replace undef with poison in tests using insertvalue

perl -p -i -e 's/insertvalue (.*) undef/insertvalue \1 poison/g'

AMDGPU: Replace undef with poison in tests using insertvalue

perl -p -i -e 's/insertvalue (.*) undef/insertvalue \1 poison/g'

Merge commit 'dd699c1333daeaea1c50c1506a66e9c7372afbb5' into users/meinersbur/irbuilder-extract

Merge commit 'e2d1e2183a9615c669392eefcfe632cc0b59a649' into users/meinersbur/irbuilder-extract

Merge commit '6942c64e8128e4ccd891b813d0240f574f80f59e^' into users/meinersbur/irbuilder-extract-refactor

[AMDGPU] Do not wait for vscnt on function entry and return

SIInsertWaitcnts inserts waitcnt instructions to resolve data
dependencies. The GFX10+ vscnt (VMEM store count) counter is never used
in this way. It is only used to resolve memory dependencies, and that is
handled by SIMemoryLegalizer. Hence there is no need to conservatively
wait for vscnt to be 0 on function entry and before returns.

Differential Revision: https://reviews.llvm.org/D153537

[AMDGPU] Add GFX11 test coverage

Add GFX11 test coverage to a bunch of tests where it was easy to do so,
mostly because the checks are autogenerated and/or GFX11 can share the
same checks as GFX10.

Differential Revision: https://reviews.llvm.org/D129295

[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
the compilation time and there is no case for which we see any improvement in
performance. This patch removes this pass and its associated test cases from
the tree.

Differential Revision: https://reviews.llvm.org/D101313

Change-Id: I0599169a7609c19a887f8d847a71e664030cc141

[AMDGPU] Extend gfx10 test coverage. NFC.

Differential Revision: https://reviews.llvm.org/D99267

[DPWBS-1200] Merge community 'master' into HighTec 'htc/master'

Due to interface changes there were a few necessary changes to TriCore
specific files. The following table lists the changed files and the
corresponding community master commits:

TriCoreInstrInfo.h/.cpp:        e6c9a9af398baf40537d45498e0aaf417c1306dc
TriCoreInstPrinter.h/.cpp:      aa708763d30384c0da0b0779be96ba45f65773df
TriCoreRegisterBankInfo.h/.cpp: 21309eafdebaa0041a83a026ae011e305b2f52a0
TriCoreMCInstLower.cpp:         a transitive include of TargetMachine.h
                                was removed somewhere and had to be
                                included here
TriCoreDisassembler.cpp:        6fdd6a7b3f696972edc244488f59532d05136a27
TriCoreTargetMachine.cpp:       05da2fe52162c80dfa18aedf70cf73cb11201811
TriCore/*/CMakeLists.txt:       ab411801b82783eb7f652701ccfce81b16cf1811
legalize-phi.mir:               6da7dbb806dce9fbc05416482a5b895efdea96b0

DAG: Stop trying to fold FP -(x-y) -> y-x in getNode with nsz

This was increasing the number of instructions when fsub was legalized
on AMDGPU with no signed zeros enabled. This fold should be guarded by
hasOneUse, and I don't think getNode should be doing that. The same
fold is already done as a regular combine through isNegatibleForFree.

This does require duplicating, even though isNegatibleForFree does
this combine already (and properly checks hasOneUse) to avoid one PPC
regression. In the regression, the outer fneg has nsz but the fsub
operand does not. isNegatibleForFree only sees the operand, and
doesn't see it's used from a nsz context. A nsz parameter needs to be
added and threaded through isNegatibleForFree to avoid this.

AMDGPU: Precommit test showing extra instructions are introduced