LLVM/project 85e290bllvm/test/CodeGen/AMDGPU bf16.ll, llvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm70.ll

Merge branch 'main' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,350-4,196llvm/test/CodeGen/AMDGPU/bf16.ll
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+90,478-10,3696,999 files not shown
+425,286-177,3787,005 files

LLVM/project 7dc7264llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'main' into users/ylzsx/r-tls-noie
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+29,745-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+203,722-016,100 files not shown
+2,040,184-604,85516,106 files

LLVM/project 8cb72bdllvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm60.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

reb

Created using spr 1.3.4
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+88,808-6,1733,815 files not shown
+253,453-75,5073,821 files

LLVM/project 8c41ae6lldb/tools/lldb-dap lldb-dap.cpp, llvm/test/CodeGen/AMDGPU bf16.ll

Merge branch 'main' into users/meinersbur/flang_runtime_premerge
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,194-3,880llvm/test/CodeGen/AMDGPU/bf16.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+309-5,049lldb/tools/lldb-dap/lldb-dap.cpp
+90,138-8,9295,013 files not shown
+307,445-100,3025,019 files

LLVM/project d7bc6d6clang/lib/Headers avx10_2convertintrin.h, llvm/test/CodeGen/NVPTX cmpxchg-sm70.ll cmpxchg-sm60.ll

Rebase, address comments

Created using spr 1.3.5
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+4,730-0llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s
+2,854-51clang/lib/Headers/avx10_2convertintrin.h
+90,219-512,963 files not shown
+198,153-49,5632,969 files

LLVM/project a97bbe6lldb/tools/lldb-dap lldb-dap.cpp, llvm/test/CodeGen/AMDGPU bf16.ll

rebase

Created using spr 1.3.5-bogner
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,194-3,880llvm/test/CodeGen/AMDGPU/bf16.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+309-5,049lldb/tools/lldb-dap/lldb-dap.cpp
+90,138-8,9294,327 files not shown
+283,321-85,4414,333 files

LLVM/project 519ae24llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/nest-base' into users/chapuni/mcdc/nest/trunk
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782-7,782llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255-7,255llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967-6,967llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+102,453-36,85810,567 files not shown
+953,290-609,13410,573 files

LLVM/project 03c851allvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/bitmapaddr' into users/chapuni/mcdc/nest/nest-base

Conflicts:
        clang/test/CoverageMapping/mcdc-single-cond.cpp
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782-7,782llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255-7,255llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967-6,967llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+102,453-36,85810,567 files not shown
+953,290-609,13410,573 files

LLVM/project d6cb61allvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/bitmapaddr
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782-7,782llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,255-7,255llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967-6,967llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+102,453-36,85810,567 files not shown
+953,323-609,04210,573 files

LLVM/project 457cf4bllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/mcdcstate
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782-7,782llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255-7,255llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967-6,967llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+102,453-36,85810,567 files not shown
+953,323-609,04210,573 files

LLVM/project aac9c6dllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/lnot
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782-7,782llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255-7,255llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967-6,967llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+102,453-36,85810,566 files not shown
+953,289-609,12910,572 files

LLVM/project e57bdccllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/expect
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782-7,782llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,255-7,255llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967-6,967llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+102,453-36,85810,566 files not shown
+953,289-609,12910,572 files

LLVM/project 9a175d0llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'main' into users/chapuni/mcdc/nest/tests
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782-7,782llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,255-7,255llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967-6,967llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+102,453-36,85810,565 files not shown
+953,289-609,03210,571 files

LLVM/project 942fda2clang/lib/Headers avx10_2convertintrin.h, llvm/test/Analysis/CostModel/AArch64 arith-widening.ll

rebase

Created using spr 1.3.4
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+4,730-0llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s
+2,854-51clang/lib/Headers/avx10_2convertintrin.h
+1,896-940llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+1,730-0llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll
+779-762llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
+77,584-1,7531,903 files not shown
+138,958-30,9491,909 files

LLVM/project 967dc03llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

run 'git merge main'
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782-7,782llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255-7,255llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967-6,967llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+102,453-36,8588,560 files not shown
+809,659-558,2578,566 files

LLVM/project c0cb6c1lldb/source/Plugins/UnwindAssembly/InstEmulation UnwindAssemblyInstEmulation.cpp, llvm/test/CodeGen/AArch64 sve-lrint.ll sve-llrint.ll

Merge branch 'main' into users/mtrofin/02-25-_ctxprof_don_t_inline_weak_symbols_after_instrumentation
DeltaFile
+659-652llvm/test/CodeGen/AArch64/sve-lrint.ll
+659-652llvm/test/CodeGen/AArch64/sve-llrint.ll
+392-392llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
+214-231lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+415-0mlir/test/Dialect/Vector/vector-rewrite-subbyte-ext-and-trunci.mlir
+0-411llvm/test/Transforms/InstCombine/AArch64/sve-inst-combine-cmpne.ll
+2,339-2,338723 files not shown
+18,238-14,765729 files

LLVM/project 3bb5867lldb/tools/lldb-dap lldb-dap.cpp, llvm/test/CodeGen/AMDGPU llvm.log10.ll llvm.log.ll

Fix formatting

Created using spr 1.3.5
DeltaFile
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+26-2,694lldb/tools/lldb-dap/lldb-dap.cpp
+764-833llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+764-833llvm/test/CodeGen/AMDGPU/llvm.log.ll
+18,594-4,3601,391 files not shown
+65,876-28,1571,397 files

LLVM/project 6f2345allvm/test/CodeGen/AArch64 sve-streaming-mode-fixed-length-int-immediates.ll sve-fixed-length-int-immediates.ll

[LLVM][AArch64] Change SVE CodeGen tests to use splat().

The affected tests were using the longwinded syntax for constant
splats. By using the splat() syntax the tests get simplified whilst
also removing the need for "undef".
DeltaFile
+56-168llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
+56-168llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll
+40-80llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
+48-58llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
+32-64llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
+31-41llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
+263-5797 files not shown
+318-70213 files

LLVM/project ad220d9clang/test/OpenMP target_teams_distribute_parallel_for_simd_schedule_codegen.cpp teams_distribute_parallel_for_simd_schedule_codegen.cpp, llvm/test/CodeGen/X86 large-gep-chain.ll

Merge commit 'e2d1e2183a9615c669392eefcfe632cc0b59a649' into users/meinersbur/irbuilder-extract
DeltaFile
+0-116,484llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
+0-115,677llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
+0-98,954llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
+25,277-25,277llvm/test/CodeGen/X86/large-gep-chain.ll
+9,540-24,668clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
+9,364-24,292clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
+44,181-405,35242,672 files not shown
+3,761,432-2,721,70342,678 files

LLVM/project 95e0882llvm/lib/Target/AArch64 AArch64ISelLowering.cpp SVEInstrFormats.td, llvm/test/CodeGen/AArch64 sve-int-pred-reduce.ll sve-int-log.ll

[AArch64] Add support for various operations on nxv1i1 types.

The supported operations are:
* Logical operations (and, or, xor, bic)
* Logical reductions (and, or, xor, [us]min, [us]max)
* Conversions to/from svbool_t
* Predicate count (CNTP)

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D128835
DeltaFile
+88-0llvm/test/CodeGen/AArch64/sve-int-pred-reduce.ll
+39-0llvm/test/CodeGen/AArch64/sve-int-log.ll
+21-0llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
+10-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+6-0llvm/lib/Target/AArch64/SVEInstrFormats.td
+5-0llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+169-26 files

LLVM/project 80a0c15clang/test/CodeGen/RISCV/rvv-intrinsics vluxseg.c vloxseg.c, clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded vloxseg.c vluxseg.c

Merge branch 'main' into irbuilder-extract-refactor
DeltaFile
+12,242-14,649llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+11,615-13,961llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+2-24,936clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
+2-24,936clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
+2-21,307clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
+2-21,307clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
+23,865-121,09630,598 files not shown
+2,090,526-1,305,42030,604 files

LLVM/project bcda4c4llvm/lib/Target/AArch64 AArch64SVEInstrInfo.td SVEInstrFormats.td, llvm/test/CodeGen/AArch64 sve-umulo-sdnode.ll sve-smulo-sdnode.ll

[SVE] By using SEL when orring predicates we forgo the need for a PTRUE.

Differential Revision: https://reviews.llvm.org/D118463
DeltaFile
+12-12llvm/test/CodeGen/AArch64/sve-umulo-sdnode.ll
+12-12llvm/test/CodeGen/AArch64/sve-smulo-sdnode.ll
+4-8llvm/test/CodeGen/AArch64/sve-int-log.ll
+3-6llvm/test/CodeGen/AArch64/sve-split-int-pred-reduce.ll
+4-4llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+4-2llvm/lib/Target/AArch64/SVEInstrFormats.td
+39-446 files

LLVM/project 49178a2llvm/lib/Target/AArch64 AArch64SVEInstrInfo.td SVEInstrFormats.td, llvm/test/CodeGen/AArch64 sve-int-log.ll llvm-ir-to-intrinsic.ll

[SVE] Extend isel pattern coverage for BIC.

Adds patterns of the form "(and a, (not b)) -> bic".

NOTE: With this support I'm inclined to remove AArch64ISD::BIC,
but will leave that investigation for another time.

Differential Revision: https://reviews.llvm.org/D118365
DeltaFile
+88-0llvm/test/CodeGen/AArch64/sve-int-log.ll
+13-17llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
+9-3llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+6-5llvm/lib/Target/AArch64/SVEInstrFormats.td
+116-254 files

LLVM/project dafd1f2llvm/lib/Target/AArch64 SVEInstrFormats.td AArch64SVEInstrInfo.td, llvm/test/CodeGen/AArch64 sve-int-log.ll sve-split-int-pred-reduce.ll

[AArch64][SVE] Avoid using ptrue for unpredicated predicate AND.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D118146
DeltaFile
+4-8llvm/test/CodeGen/AArch64/sve-int-log.ll
+12-0llvm/lib/Target/AArch64/SVEInstrFormats.td
+6-6llvm/test/CodeGen/AArch64/sve-split-int-pred-reduce.ll
+3-6llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
+1-1llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+26-215 files

LLVM/project 1ef5699llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 sve-int-arith.ll sve-int-log.ll

[DAGCombiner] Support fold zero scalar vector.

This patch changes ISD::isBuildVectorAllZeros to
ISD::isConstantSplatVectorAllZeros which handles zero sclar vector.

TestPlan: check-llvm

Differential Revision: https://reviews.llvm.org/D100813
DeltaFile
+32-0llvm/test/CodeGen/AArch64/sve-int-arith.ll
+16-16llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+25-0llvm/test/CodeGen/AArch64/sve-int-log.ll
+0-10llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
+0-10llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
+0-10llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
+73-461 files not shown
+73-567 files

LLVM/project 672f673llvm/test/Analysis/LoopAccessAnalysis runtime-pointer-checking-insert-typesize.ll, llvm/test/CodeGen/AArch64 dag-combine-insert-subvector.ll named-vector-shuffle-reverse-neon.ll

[SVE] Remove checks for warnings in scalable-vector tests.

After D98856 these tests will by default break (fatal_error) if any of
the wrong interfaces are used, so there's no longer a need to have a
RUN line that checks for a warning message emitted by the compiler.
DeltaFile
+6-9llvm/test/Analysis/LoopAccessAnalysis/runtime-pointer-checking-insert-typesize.ll
+5-8llvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll
+1-9llvm/test/Transforms/InstCombine/debuginfo-scalable-typesize.ll
+2-8llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll
+3-6llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
+2-7llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
+19-47437 files not shown
+457-2,258443 files

LLVM/project 02650acllvm/test/CodeGen/AArch64 README sve-gather-scatter-dag-combine.ll

[SVE][CodeGen] Add README for SVE-related warnings in tests

I have added a new file:

  llvm/test/CodeGen/AArch64/README

that describes what to do in the event one of the SVE codegen tests
fails the warnings check. In addition, I've added comments to all
the relevant SVE tests pointing users at the README file.

Differential Revision: https://reviews.llvm.org/D83467
DeltaFile
+11-0llvm/test/CodeGen/AArch64/README
+1-0llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
+1-0llvm/test/CodeGen/AArch64/sve-gep.ll
+1-0llvm/test/CodeGen/AArch64/sve-insert-element.ll
+1-0llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
+1-0llvm/test/CodeGen/AArch64/sve-int-arith-pred.ll
+16-0114 files not shown
+130-0120 files

LLVM/project 7edc7f6llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp DAGCombiner.cpp, llvm/test/CodeGen/AArch64 sve-int-log-imm.ll sve-int-log.ll

[CodeGen] Fix SimplifyDemandedBits for scalable vectors

For now I have changed SimplifyDemandedBits and it's various callers
to assume we know nothing for scalable vectors and to ignore the
demanded bits completely. I have also done something similar for
SimplifyDemandedVectorElts. These changes fix up lots of warnings
due to calls to EVT::getVectorNumElements() for types with scalable
vectors. These functions are all used for optimisations, rather than
functional requirements. In future we can revisit this code if
there is a need to improve code quality for SVE.

Differential Revision: https://reviews.llvm.org/D80537
DeltaFile
+55-0llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp
+26-5llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+14-4llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+4-1llvm/test/CodeGen/AArch64/sve-int-log-imm.ll
+4-1llvm/test/CodeGen/AArch64/sve-int-log.ll
+4-1llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
+107-123 files not shown
+119-159 files

LLVM/project 24ac256llvm/test/CodeGen/AMDGPU/GlobalISel udiv.i64.ll urem.i64.ll, llvm/test/CodeGen/Thumb2 mve-satmul-loops.ll

Merge community 'master' into 'htc/master'

The following TriCore specific files needed to be touched due to
upstream changes:

TriCore.cpp:                    <unknown>
TriCoreCallLowering.cpp:        01ba2ad9ef085f184f3b01cefed4ce59e170054a
TriCoreFrameLowering.h/.cpp:    2481f26ac3f228cc085d4d68ee72dadc07afa48f
TriCoreInstrInfo.cpp:           01ba2ad9ef085f184f3b01cefed4ce59e170054a
TriCoreLegalizerInfo.cpp:       01ba2ad9ef085f184f3b01cefed4ce59e170054a
TriCoreRegisterInfo.cpp:        2481f26ac3f228cc085d4d68ee72dadc07afa48f

The following TriCore specific tests needed to be touched due to
upstream changes:

call-translator.ll:                  b8fc192d42af56b17b7d940e6c226f4969e0d851
legalize-insert.mir:                 c8393240abc10218b03f2cafe9a83b1fb29b4e3d
legalize-unmerge-values-invalid.mir: c8393240abc10218b03f2cafe9a83b1fb29b4e3d
                                     432720f1c4c6b47edfb475f8616e471d14c26974

    [10 lines not shown]
DeltaFile
+4,328-2,388llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
+3,787-0llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
+2,138-1,394llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
+3,465-0llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
+3,436-0llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
+0-3,036mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp
+17,154-6,8186,132 files not shown
+249,691-116,5866,138 files

LLVM/project dacf8d3llvm/lib/Target/AArch64 SVEInstrFormats.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sve-fcmp.ll sve-int-log.ll

[AArch64][SVE] Add support for fcmp.

This also requires support for boolean "not", so I added boolean logic
while I was there.

Differential Revision: https://reviews.llvm.org/D76901
DeltaFile
+231-0llvm/test/CodeGen/AArch64/sve-fcmp.ll
+172-38llvm/test/CodeGen/AArch64/sve-int-log.ll
+31-1llvm/lib/Target/AArch64/SVEInstrFormats.td
+21-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+8-8llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+463-485 files