LLVM/project 26324bcllvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize/RISCV vplan-vp-intrinsics-fixed-order-recurrence.ll

[VPlan] Move FOR splice cost into VPInstruction::FirstOrderRecurrenceSplice (#129645)

After #124093 we now support fixed-order recurrences with EVL tail
folding by replacing VPInstruction::FirstOrderRecurrenceSplice with a VP
splice intrinsic.

However the costing for the splice is currently done in
VPFirstOrderRecurrencePHIRecipe, so when we add the VP splice intrinsic
we end up costing it twice.

This fixes it by splitting out the cost for the splice into
FirstOrderRecurrenceSplice so that it's not duplicated when we replace
it.

We still have to keep the VF=1 checks in VPFirstOrderRecurrencePHIRecipe
since the splice might end up dead and discarded, e.g. in the test
@pr97452_scalable_vf1_for.
DeltaFile
+11-8llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+2-1llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
+13-92 files

LLVM/project 02575f8llvm/lib/Transforms/Vectorize VPlanRecipes.cpp VPlan.h

[VPlan] Use VPInstruction for VPScalarPHIRecipe. (NFCI) (#129767)

Now that all phi nodes manage their incoming blocks through the
VPlan-predecessors, there should be no need for having a dedicate
recipe, it should be sufficient to allow PHI opcodes in VPInstruction.

Follow-ups will also migrate VPWidenPHIRecipe and possibly others,
building on top of https://github.com/llvm/llvm-project/pull/129388.

PR: https://github.com/llvm/llvm-project/pull/129767
DeltaFile
+28-25llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+1-42llvm/lib/Transforms/Vectorize/VPlan.h
+12-8llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
+9-4llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
+6-5llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+5-3llvm/lib/Transforms/Vectorize/VPlan.cpp
+61-876 files not shown
+69-9512 files

LLVM/project 85e290bllvm/test/CodeGen/AMDGPU bf16.ll, llvm/test/CodeGen/NVPTX cmpxchg-sm70.ll cmpxchg-sm90.ll

Merge branch 'main' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,350-4,196llvm/test/CodeGen/AMDGPU/bf16.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+90,478-10,3696,999 files not shown
+425,286-177,3787,005 files

LLVM/project 2ece26fllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

Update OB name from `type` to `callee_type`.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-024,133 files not shown
+2,356,601-721,36324,139 files

LLVM/project 9c94049llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
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+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-024,129 files not shown
+2,356,435-721,19824,135 files

LLVM/project 05307cfllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

Update LTO compilation CodeGen flag for call-graph-section.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-024,129 files not shown
+2,356,435-721,19824,135 files

LLVM/project de23806llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-024,128 files not shown
+2,356,423-721,19324,134 files

LLVM/project 2c57c89llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll

Merge branch 'main' of https://github.com/llvm/llvm-project into remove-old-res-middle
DeltaFile
+2,099-2,096llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053-2,052llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434-1,828llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+2,915-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+1,434-1,418llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940-1,896llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+10,875-9,2902,274 files not shown
+97,298-62,3572,280 files

LLVM/project 79c32c1llvm/test/MC/AMDGPU gfx12_asm_sop2.s gfx12_asm_sop1.s, llvm/test/MC/Disassembler/AMDGPU gfx12_dasm_sop2.txt gfx12_dasm_sop1.txt

.

Created using spr 1.3.5-bogner
DeltaFile
+2,099-2,096llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053-2,052llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
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+1,234-1,233llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
+721-720llvm/test/MC/AMDGPU/gfx12_asm_sopc.s
+721-720llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt
+8,252-8,244263 files not shown
+14,950-10,040269 files

LLVM/project ed3f871llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-cttz-vp.ll

Merge branch 'main' into users/vitalybuka/spr/ir-optimize-cfi-in-writecombinedglobalvaluesummary
DeltaFile
+2,099-2,096llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053-2,052llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434-1,828llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+1,434-1,418llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940-1,896llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+1,240-1,230llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
+9,200-10,5201,240 files not shown
+47,494-33,1451,246 files

LLVM/project dc23234llvm/lib/Transforms/Vectorize VPlanRecipes.cpp

[VPlan] Remove dead code in VPWidenPHIRecipe::print (NFC).

All incoming models for VPWidenPHIRecipe are modled in VPlan, remove
code trying to print the orignial phi.
DeltaFile
+0-10llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+0-101 files

LLVM/project 9274743llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Analysis/CostModel/AArch64 arith-widening.ll sve-intrinsics.ll

release note

Created using spr 1.3.5-bogner
DeltaFile
+940-1,896llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+741-741llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
+660-658llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+545-533llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
+464-470llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
+74-698llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+3,424-4,996379 files not shown
+13,173-12,743385 files

LLVM/project 26ecf97llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize/AArch64 early_exit_costs.ll simple_early_exit.ll

[LoopVectorize] Further improve cost model for early exit loops (#126235)

Following on from #125058, this patch takes into account the
work done in the vector early exit block when assessing the
profitability of vectorising the loop. I have renamed
areRuntimeChecksProfitable to isOutsideLoopWorkProfitable and
we now pass in the early exit costs. As part of this, I have
added the ExtractFirstActive opcode to VPInstruction::computeCost.

It's worth pointing out that when we assess profitability of the
loop we calculate a minimum trip count and compare that against
the *maximum* trip count. However, since the loop has an early
exit the runtime trip count can still end up being less than the
minimum. Alternatively, we may never take the early exit at all
at runtime and so we have the opposite problem of over-estimating
the cost of the loop. The loop vectoriser cannot simultaneously
take two contradictory positions and so I feel the only sensible
thing to do is be conservative and assume the loop will be more
expensive than loops without early exits.

    [4 lines not shown]
DeltaFile
+86-0llvm/test/Transforms/LoopVectorize/AArch64/early_exit_costs.ll
+56-14llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+12-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+1-0llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
+155-144 files

LLVM/project 397c487llvm/test/CodeGen/AMDGPU global_atomics_scan_fsub.ll global_atomics_scan_fadd.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-cttz-vp.ll

Merge remote-tracking branch 'origin/main' into users/ccc03-08-_astmatcher_templateargumentcountis_support_functiondecl_
DeltaFile
+1,434-1,828llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+1,246-1,246llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+1,246-1,246llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+1,214-1,214llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+1,214-1,214llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+726-1,509llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
+7,080-8,2571,023 files not shown
+37,140-28,4421,029 files

LLVM/project 809a33dllvm/lib/Transforms/Vectorize VPlanRecipes.cpp

[VPlan] Clean up unused header (NFC) (#130599)

We use VPlanPatternMatch, and not PatternMatch: clean up the
PatternMatch include to avoid confusion.
DeltaFile
+0-1llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+0-11 files

LLVM/project dc66ca4llvm/test/CodeGen/AMDGPU llvm.amdgcn.smfmac.gfx950.ll, llvm/test/CodeGen/RISCV xqccmp-push-pop-popret.ll

Rebase, address comments

Created using spr 1.3.5
DeltaFile
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+3,951-0llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
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+1,746-1,734llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,348-1,952llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+17,078-9,8592,714 files not shown
+131,118-67,3922,720 files

LLVM/project d4e79afllvm/test/CodeGen/AMDGPU global_atomics_scan_fadd.ll global_atomics_scan_fsub.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll qci-interrupt-attr-fpr.ll

Merge branch 'main' into users/kparzysz/spr/o03-cancel-directive-name
DeltaFile
+2,927-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821-0llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+1,246-1,246llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+1,246-1,246llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+1,214-1,214llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+1,214-1,214llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+10,668-4,9201,301 files not shown
+51,893-31,2131,307 files

LLVM/project 7dc7264llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'main' into users/ylzsx/r-tls-noie
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+29,745-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+203,722-016,100 files not shown
+2,040,184-604,85516,106 files

LLVM/project 33f623dllvm/test/CodeGen/AMDGPU vni8-across-blocks.ll shufflevector-physreg-copy.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll qci-interrupt-attr-fpr.ll

Merge branch 'main' into users/kparzysz/spr/o02-metadirective-flush
DeltaFile
+2,927-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821-0llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+603-1,206llvm/test/CodeGen/X86/matrix-multiply.ll
+706-540llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
+812-407llvm/test/CodeGen/Thumb2/mve-vld3.ll
+795-0llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
+8,664-2,153747 files not shown
+23,408-10,802753 files

LLVM/project 2ff290bllvm/test/CodeGen/RISCV xqccmp-push-pop-popret.ll qci-interrupt-attr.ll, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-7.ll vector-interleaved-store-i8-stride-7.ll

Rebase

Created using spr 1.3.5
DeltaFile
+3,951-0llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+3,860-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,746-1,734llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,532-1,534llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,927-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821-0llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+16,837-3,2681,830 files not shown
+73,594-27,5911,836 files

LLVM/project 6d89c04llvm/lib/Transforms/Vectorize VPlanRecipes.cpp

[VPlan] Remove dead AnyOf reduction case in VPReductionRecipe. NFCI (#130048)

From what I understand, we only create VPReductionRecipes for in-loop
reductions, and we don't currently support in-loop AnyOf reductions.

We only create VPReductionRecipes in the !PhiR->isInLoop() section of
adjustRecipesForReductions, and this comment from the initial patch
seems to confirm this
https://reviews.llvm.org/D108136#anchor-inline-1038338, so I think we
can remove this check in the condition logic.

I checked compiling SPEC 2017 with -prefer-inloop-predicates and the
added assertion doesn't trigger.
DeltaFile
+4-6llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+4-61 files

LLVM/project 8cb72bdllvm/test/CodeGen/NVPTX cmpxchg-sm60.ll cmpxchg-sm90.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

reb

Created using spr 1.3.4
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+88,808-6,1733,815 files not shown
+253,453-75,5073,821 files

LLVM/project 8c41ae6lldb/tools/lldb-dap lldb-dap.cpp, llvm/test/CodeGen/AMDGPU bf16.ll

Merge branch 'main' into users/meinersbur/flang_runtime_premerge
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,194-3,880llvm/test/CodeGen/AMDGPU/bf16.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+309-5,049lldb/tools/lldb-dap/lldb-dap.cpp
+90,138-8,9295,013 files not shown
+307,445-100,3025,019 files

LLVM/project fd374e5llvm/test/CodeGen/AArch64 sve-partial-reduce-dot-product.ll, llvm/test/CodeGen/AMDGPU llvm.amdgcn.smfmac.gfx950.ll llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll

Rebase, address comments

Created using spr 1.3.5
DeltaFile
+1,348-1,952llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+760-23mlir/test/Dialect/Tosa/level_check.mlir
+172-258llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
+285-102mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
+192-194llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
+342-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-umaxv.ll
+3,099-2,529382 files not shown
+9,637-5,261388 files

LLVM/project b2e1758llvm/test/CodeGen/AMDGPU llvm.amdgcn.smfmac.gfx950.ll, llvm/test/Instrumentation/MemorySanitizer/AArch64 arm64-vmul.ll neon_vmul.ll

Rebase, address comments

Created using spr 1.3.5
DeltaFile
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
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+0-1,933llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll
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+0-1,917llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_lane.ll
+9,454-11,9751,125 files not shown
+41,367-24,0581,131 files

LLVM/project 5ea9c7eclang/lib/Headers avx10_2convertintrin.h, llvm/test/Instrumentation/MemorySanitizer/AArch64 neon_vmul.ll arm64-vmul.ll

Reabse, address comments

Created using spr 1.3.5
DeltaFile
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+2,854-51clang/lib/Headers/avx10_2convertintrin.h
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+0-1,933llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll
+1,917-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-st1_lane.ll
+12,877-8,1571,598 files not shown
+58,088-25,8271,604 files

LLVM/project 47fb9c4llvm/lib/Transforms/Vectorize VPlan.h VPlanRecipes.cpp

[VPlan] Add Name argument to VPWidenPHIRecipe. NFC (#129527)

This allows a different IR name for the generated phi to be used. This
is split off from #118638 and helps remove some of the diffs in it.
DeltaFile
+7-2llvm/lib/Transforms/Vectorize/VPlan.h
+1-1llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+1-1llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp
+9-43 files

LLVM/project d7bc6d6clang/lib/Headers avx10_2convertintrin.h, llvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm70.ll

Rebase, address comments

Created using spr 1.3.5
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
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LLVM/project a97bbe6lldb/tools/lldb-dap lldb-dap.cpp, llvm/test/CodeGen/AMDGPU bf16.ll

rebase

Created using spr 1.3.5-bogner
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,194-3,880llvm/test/CodeGen/AMDGPU/bf16.ll
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+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+309-5,049lldb/tools/lldb-dap/lldb-dap.cpp
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LLVM/project 519ae24llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/nest-base' into users/chapuni/mcdc/nest/trunk
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782-7,782llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,255-7,255llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967-6,967llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
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+953,290-609,13410,573 files