LLVM / project - FreshBSD

LLVM/project 552f6c9 — llvm/test/CodeGen/X86 vector-interleaved-store-i8-stride-7.ll vector-interleaved-store-i16-stride-6.ll, llvm/test/Instrumentation/MemorySanitizer/AArch64 arm64-ld1.ll

users/fmayer/spr/mte-generalize-overalignment-size-of-mte-globals

rebase

Created using spr 1.3.4

Delta		File
+3,128	-3,170	llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,487	-2,510	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+2,099	-2,096	llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053	-2,052	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+3,860	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,716	-1,780	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
+15,343	-11,608	4,566 files not shown
+159,258	-104,313	4,572 files

LLVM/project 85e290b — llvm/test/CodeGen/AMDGPU bf16.ll, llvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm70.ll

2 days ago by Michael Kruse on ⎇

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'main' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,350	-4,196	llvm/test/CodeGen/AMDGPU/bf16.ll
+6,173	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0	-6,173	llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+90,478	-10,369	6,999 files not shown
+425,286	-177,378	7,005 files

LLVM/project 2c57c89 — llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll

3 days ago by Helena Kotas on ⎇

users/hekota/pr-130338-remove-old-res-middle

Merge branch 'main' of https://github.com/llvm/llvm-project into remove-old-res-middle

Delta		File
+2,099	-2,096	llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053	-2,052	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434	-1,828	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+2,915	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+1,434	-1,418	llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940	-1,896	llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+10,875	-9,290	2,274 files not shown
+97,298	-62,357	2,280 files

LLVM/project dc66ca4 — llvm/test/CodeGen/AMDGPU llvm.amdgcn.smfmac.gfx950.ll, llvm/test/CodeGen/RISCV xqccmp-push-pop-popret.ll

5 days ago by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvfiximprove-max-safe-distance-analysis

Rebase, address comments

Created using spr 1.3.5

Delta		File
+0	-6,173	llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+6,173	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+3,951	-0	llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+3,860	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,746	-1,734	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,348	-1,952	llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+17,078	-9,859	2,714 files not shown
+131,118	-67,392	2,720 files

LLVM/project d4e79af — llvm/test/CodeGen/AMDGPU global_atomics_scan_fsub.ll global_atomics_scan_fadd.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll qci-interrupt-attr-fpr.ll

5 days ago by Krzysztof Parzyszek via GitHub on ⎇

users/kparzysz/spr/o03-cancel-directive-name

Merge branch 'main' into users/kparzysz/spr/o03-cancel-directive-name

Delta		File
+2,927	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+1,246	-1,246	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+1,246	-1,246	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+1,214	-1,214	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+1,214	-1,214	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+10,668	-4,920	1,301 files not shown
+51,893	-31,213	1,307 files

LLVM/project 7dc7264 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

6 days ago by yangzhaoxin on ⎇

users/ylzsx/r-tls-noie

Merge branch 'main' into users/ylzsx/r-tls-noie

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+29,745	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+203,722	-0	16,100 files not shown
+2,040,184	-604,855	16,106 files

LLVM/project ad73b90 — llvm/docs LangRef.rst, llvm/test/Transforms/LoopVectorize select-cmp.ll single_early_exit_live_outs.ll

8 days ago by Vitaly Buka on ⎇

users/vitalybuka/spr/nfcir-wrap-stdset-into-cfifunctionindex

format

Created using spr 1.3.4

Delta		File
+120	-60	llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
+85	-0	offload/test/offloading/fortran/usm_map_close.f90
+62	-15	llvm/docs/LangRef.rst
+44	-22	llvm/test/Transforms/LoopVectorize/select-cmp.ll
+36	-18	llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
+27	-24	llvm/test/Transforms/LoopVectorize/select-reduction-start-value-may-be-undef-or-poison.ll
+374	-139	52 files not shown
+851	-377	58 files

LLVM/project f117881 — flang/test/Integration/OpenMP map-types-and-sizes.f90, flang/test/Lower/OpenMP map-modifiers.f90

8 days ago by agozillon via GitHub on ⎇

main

[Flang][OpenMP][MLIR] Implement close, present and ompx_hold modifiers for Flang maps (#129586)

This PR adds an initial implementation for the map modifiers close,
present and ompx_hold, primarily just required adding the appropriate
map type flags to the map type bits. In the case of ompx_hold it
required adding the map type to the OpenMP dialect. Close has a bit of a
problem when utilised with the ALWAYS map type on descriptors, so it is
likely we'll have to make sure close and always are not applied to the
descriptor simultaneously in the future when we apply always to the
descriptors to facilitate movement of descriptor information to device
for consistency, however, we may find an alternative to this with
further investigation. For the moment, it is a TODO/Note to keep track
of it.

Delta		File
+85	-0	offload/test/offloading/fortran/usm_map_close.f90
+41	-0	offload/test/offloading/fortran/target_map_present_success.f90
+36	-0	offload/test/offloading/fortran/target_map_present_fail.f90
+32	-1	flang/test/Integration/OpenMP/map-types-and-sizes.f90
+32	-0	flang/test/Lower/OpenMP/map-modifiers.f90
+29	-0	offload/test/offloading/fortran/target_map_ompx_hold.f90
+255	-1	11 files not shown
+293	-75	17 files

LLVM/project 16e61cf — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Jan 7 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-add-riscv_atomich-and-zawrs-builtins

Rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	45,766 files not shown
+4,106,333	-2,097,168	45,772 files

LLVM/project 631bc35 — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Dec 21, 2024 by NAKAMURA Takumi on ⎇

users/chapuni/cov/single/replace

Merge branch 'main' into users/chapuni/cov/single/replace

Delta		File
+16,880	-2,842	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+19,618	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,081	-2,450	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,046	-22,710	26,925 files not shown
+2,067,496	-1,063,533	26,931 files

LLVM/project ce7c17d — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Dec 21, 2024 by NAKAMURA Takumi on ⎇

users/chapuni/cov/single/pair

Merge branch 'main' into users/chapuni/cov/single/pair

Delta		File
+16,880	-2,842	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+19,618	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,081	-2,450	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,046	-22,710	26,925 files not shown
+2,067,496	-1,063,533	26,931 files

LLVM/project d7d008b — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Dec 11, 2024 by Vitaly Buka via GitHub on ⎇

users/vitalybuka/spr/libclocale-update-grouping-tests

Merge branch 'main' into users/vitalybuka/spr/libclocale-update-grouping-tests

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	43,237 files not shown
+4,159,794	-2,020,023	43,243 files

LLVM/project e51ce07 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprasmprintercallgraphsection-emit-call-graph-section-4

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project 17ee91d — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.asmprintercallgraphsection-emit-call-graph-section-4

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project 4f31680 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallsiteinfocallgraphsection-extract-and-propagate-indirect-call-type-ids

Rebase on top of upstream main. Remove opt has_value, value use.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project a993e6d — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.callsiteinfocallgraphsection-extract-and-propagate-indirect-call-type-ids

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 26a149b — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallsiteinfocallgraphsection-extend-callsiteinfo-with-typeid

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 2cb9de4 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.callsiteinfocallgraphsection-extend-callsiteinfo-with-typeid

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project a3ca3e2 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprclangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 08dc8a4 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.clangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project 23ac5ef — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallgraphsection-add-call-graph-section-options-and-documentation

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project c0b6218 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by LLVM GN Syncbot via prabhukr on ⎇

users/Prabhuk/sprmain.callgraphsection-add-call-graph-section-options-and-documentation

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
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+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project 6675226 — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/test/CodeGen/AMDGPU flat_atomics_i64_system_noprivate.ll flat_atomics_i64_noprivate.ll

Nov 20, 2024 by NAKAMURA Takumi on ⎇

users/chapuni/cov/single/merge

Merge branch 'users/chapuni/cov/single/test' into users/chapuni/cov/single/merge

Delta		File
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+9,196	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
+3,630	-3,624	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,804	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+40,524	-10,845	8,255 files not shown
+418,694	-225,256	8,261 files

LLVM/project cfc6dbe — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime

Merge branch 'users/meinersbur/flang_runtime_move-files' into users/meinersbur/flang_runtime

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,877	-2,839	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,078	-2,340	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,608	-22,597	16,041 files not shown
+1,309,194	-678,314	16,047 files

LLVM/project 7caea4d — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_move-files

Merge branch 'users/meinersbur/flang_runtime_split-headers2' into users/meinersbur/flang_runtime_move-files

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,877	-2,839	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,078	-2,340	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,608	-22,597	16,042 files not shown
+1,309,200	-678,317	16,048 files

LLVM/project bf24912 — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_split-headers2

Merge branch 'users/meinersbur/flang_runtime_split-headers' into users/meinersbur/flang_runtime_split-headers2

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,877	-2,839	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,078	-2,340	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,608	-22,597	16,042 files not shown
+1,309,196	-678,318	16,048 files

LLVM/project 2a97e4a — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_split-headers

Merge branch 'main' into users/meinersbur/flang_runtime_split-headers

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,877	-2,839	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,078	-2,340	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,608	-22,597	16,042 files not shown
+1,309,196	-678,318	16,048 files

LLVM/project 76aaed5 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 9, 2024 by Caroline Tice on ⎇

users/cmtice/DIL-collaboration-work

Merge remote-tracking branch 'origin/main' into DIL-work-new

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	36,026 files not shown
+3,104,398	-1,498,303	36,032 files

LLVM/project 3bd1ec2 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by shawbyoung via Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-functions-with-pseudo-probes

Pseudo probe function matchign

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	20,516 files not shown
+1,508,774	-528,137	20,522 files

LLVM/project 7be0b9e — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-functions-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
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+89,937	-5,837	20,516 files not shown
+1,508,726	-528,067	20,522 files