LLVM / project - FreshBSD

LLVM/project 17ee91d — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.asmprintercallgraphsection-emit-call-graph-section-4

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project 4f31680 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallsiteinfocallgraphsection-extract-and-propagate-indirect-call-type-ids

Rebase on top of upstream main. Remove opt has_value, value use.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project a993e6d — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.callsiteinfocallgraphsection-extract-and-propagate-indirect-call-type-ids

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 26a149b — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallsiteinfocallgraphsection-extend-callsiteinfo-with-typeid

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 2cb9de4 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.callsiteinfocallgraphsection-extend-callsiteinfo-with-typeid

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project a3ca3e2 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprclangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 08dc8a4 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.clangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project 23ac5ef — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallgraphsection-add-call-graph-section-options-and-documentation

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project c0b6218 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by LLVM GN Syncbot via prabhukr on ⎇

users/Prabhuk/sprmain.callgraphsection-add-call-graph-section-options-and-documentation

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project 3198bfa — llvm/test/CodeGen/AMDGPU llvm.minimum.f64.ll llvm.maximum.f64.ll, llvm/test/CodeGen/NVPTX f16x2-instructions.ll fma-relu-instruction-flag.ll

Nov 20, 2024 by Krzysztof Parzyszek on ⎇

users/kparzysz/spr/m03-semantic-checks

Merge branch 'main' into users/kparzysz/spr/m03-semantic-checks

Delta		File
+1,395	-2,208	llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
+1,869	-987	llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+873	-1,408	llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
+1,912	-0	llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
+741	-800	llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
+741	-800	llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
+7,531	-6,203	1,248 files not shown
+38,686	-22,745	1,254 files

LLVM/project 6613174 — llvm/test/CodeGen/AMDGPU llvm.maximum.f64.ll llvm.minimum.f64.ll, llvm/test/CodeGen/NVPTX f16x2-instructions.ll fma-relu-instruction-flag.ll

Nov 20, 2024 by Krzysztof Parzyszek on ⎇

users/kparzysz/spr/m02-openmp-descriptors

Merge branch 'main' into users/kparzysz/spr/m02-openmp-descriptors

Delta		File
+1,395	-2,208	llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
+1,869	-987	llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+873	-1,408	llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
+1,912	-0	llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
+741	-800	llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
+741	-800	llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
+7,531	-6,203	1,195 files not shown
+37,224	-21,802	1,201 files

LLVM/project aec7da5 — llvm/test/CodeGen/AMDGPU llvm.maximum.f64.ll llvm.minimum.f64.ll, llvm/test/CodeGen/NVPTX f16x2-instructions.ll fma-relu-instruction-flag.ll

Nov 20, 2024 by Krzysztof Parzyszek on ⎇

users/kparzysz/spr/m01-normalize-existing

Merge branch 'main' into users/kparzysz/spr/m01-normalize-existing

Delta		File
+1,395	-2,208	llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
+1,869	-987	llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+873	-1,408	llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
+1,912	-0	llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
+741	-800	llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
+741	-800	llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
+7,531	-6,203	1,178 files not shown
+36,494	-21,606	1,184 files

LLVM/project b32a441 — llvm/test/CodeGen/AMDGPU llvm.maximum.f64.ll llvm.minimum.f64.ll, llvm/test/CodeGen/NVPTX f16x2-instructions.ll i16x2-instructions.ll

Nov 20, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpadd-cost-estimation-for-gather-node-reshuffling

Address comments

Created using spr 1.3.5

Delta		File
+1,869	-987	llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+741	-800	llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
+741	-800	llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
+572	-624	llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
+572	-623	llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
+701	-409	llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
+5,196	-4,243	929 files not shown
+27,692	-15,563	935 files

LLVM/project 9bccf61 — llvm/include/llvm/Analysis TargetTransformInfo.h, llvm/lib/Transforms/Vectorize LoopVectorize.cpp

Nov 20, 2024 by Sjoerd Meijer via GitHub on ⎇

main

[AArch64][LV] Set MaxInterleaving to 4 for Neoverse V2 and V3 (#100385)

Set the maximum interleaving factor to 4, aligning with the number of available
SIMD pipelines. This increases the number of vector instructions in the vectorised
loop body, enhancing performance during its execution. However, for very low
iteration counts, the vectorised body might not execute at all, leaving only the
epilogue loop to run. This issue affects e.g. cam4_r from SPEC FP, which
experienced a performance regression. To address this, the patch reduces the
minimum epilogue vectorisation factor from 16 to 8, enabling the epilogue to be
vectorised and largely mitigating the regression.

Delta		File
+118	-0	llvm/test/Transforms/LoopVectorize/AArch64/neoverse-epilogue-vect.ll
+5	-3	llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+8	-0	llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll
+8	-0	llvm/include/llvm/Analysis/TargetTransformInfo.h
+8	-0	llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll
+6	-1	llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-vscale-tune.ll
+153	-4	7 files not shown
+176	-6	13 files

LLVM/project 0a0c824 — llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll

Nov 15, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/flang_runtime

Merge branch 'users/meinersbur/flang_runtime_move-files' into users/meinersbur/flang_runtime

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+58,428	-8,569	4,153 files not shown
+268,225	-99,256	4,159 files

LLVM/project 02812d5 — llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_move-files

Merge branch 'users/meinersbur/flang_runtime_split-headers2' into users/meinersbur/flang_runtime_move-files

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+58,428	-8,569	4,135 files not shown
+268,162	-99,193	4,141 files

LLVM/project 9118d19 — llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_split-headers2

Merge branch 'users/meinersbur/flang_runtime_split-headers' into users/meinersbur/flang_runtime_split-headers2

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+58,428	-8,569	4,127 files not shown
+268,062	-99,143	4,133 files

LLVM/project 7a08438 — llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_split-headers

Merge commit 'fa627d98e87504b6f6d621a7dab5d140340ed760^' into users/meinersbur/flang_runtime_split-headers

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+58,428	-8,569	4,127 files not shown
+268,062	-99,143	4,133 files

LLVM/project 76aaed5 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 9, 2024 by Caroline Tice on ⎇

users/cmtice/DIL-collaboration-work

Merge remote-tracking branch 'origin/main' into DIL-work-new

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	36,026 files not shown
+3,104,398	-1,498,303	36,032 files

LLVM/project 3bd1ec2 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by shawbyoung via Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-functions-with-pseudo-probes

Pseudo probe function matchign

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	20,516 files not shown
+1,508,774	-528,137	20,522 files

LLVM/project 7be0b9e — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-functions-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	20,516 files not shown
+1,508,726	-528,067	20,522 files

LLVM/project e7bce6d — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-blocks-with-pseudo-probes

address comments

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	18,744 files not shown
+1,374,895	-489,660	18,750 files

LLVM/project c84de42 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-blocks-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	18,743 files not shown
+1,374,820	-489,573	18,749 files

LLVM/project 94991b2 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Nov 7, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/bolttest-add-callcont-fallthrutest

Drop call check

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,948	-0	llvm/test/MC/AMDGPU/gfx11_asm_vopc-fake16.s
+10,486	-0	llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc-fake16.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+77,630	-4,605	13,289 files not shown
+985,511	-356,667	13,295 files

LLVM/project 91fd9e8 — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Nov 4, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/irbuilder-extract

Merge commit 'a5345114e5ac1c767aa4cd6be2aa333bea9c5009' into users/meinersbur/irbuilder-extract

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+54,322	-12,281	6,813 files not shown
+381,470	-187,676	6,819 files

LLVM/project 57e0f7f — libcxx/include regex, libcxx/src locale.cpp

Nov 4, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/irbuilder-extract

Merge commit '4619a32ad6bde20ee1f2d8297c431c0679c2c8bf' into users/meinersbur/irbuilder-extract

Delta		File
+27,218	-219	llvm/test/CodeGen/AMDGPU/bf16.ll
+11,620	-11,712	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+4,442	-5,290	libcxx/src/locale.cpp
+3,731	-4,881	libcxx/include/regex
+2,972	-4,148	llvm/test/CodeGen/AArch64/vecreduce-add.ll
+3,242	-3,243	llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
+53,225	-29,493	7,802 files not shown
+546,928	-278,424	7,808 files

LLVM/project 2811a38 — clang/test/OpenMP atomic_compare_codegen.cpp nvptx_SPMD_codegen.cpp, libc/src/__support ryu_long_double_constants.h

Nov 3, 2024 by Michael Kruse on ⎇

users/meinersbur/irbuilder-extract

Merge commit 'dd699c1333daeaea1c50c1506a66e9c7372afbb5' into users/meinersbur/irbuilder-extract

Delta		File
+119,926	-0	libc/src/__support/ryu_long_double_constants.h
+20,887	-20,814	llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+34,181	-35	clang/test/OpenMP/atomic_compare_codegen.cpp
+12,436	-12,678	clang/test/OpenMP/nvptx_SPMD_codegen.cpp
+16,298	-0	llvm/test/CodeGen/X86/pcsections-atomics.ll
+12,455	-3,587	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
+216,183	-37,114	41,232 files not shown
+4,417,032	-1,979,316	41,238 files

LLVM/project a3e5813 — clang/test/CodeGen/RISCV/rvv-intrinsics vluxseg_mask_mf.c vloxseg_mask_mf.c, llvm/test/CodeGen/AArch64/Atomics aarch64-atomicrmw-rcpc3.ll aarch64-atomicrmw-rcpc.ll

Nov 3, 2024 by Michael Kruse on ⎇

users/meinersbur/irbuilder-extract

Merge commit 'e1acf65bc1b6fbde7f0d099003c148f9b46f7b21' into users/meinersbur/irbuilder-extract

Delta		File
+9,679	-0	llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
+9,679	-0	llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
+9,679	-0	llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
+9,679	-0	llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
+0	-9,104	clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
+0	-9,104	clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
+38,716	-18,208	15,675 files not shown
+2,473,889	-901,265	15,681 files

LLVM/project a534511 — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Nov 2, 2024 by Michael Kruse on ⎇

users/meinersbur/irbuilder-extract-refactor

Merge commit 'fa789dffb1e12c2aece0187aeacc48dfb1768340' into users/meinersbur/irbuilder-extract-refactor

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+54,322	-12,281	6,813 files not shown
+381,470	-187,676	6,819 files

LLVM/project 4619a32 — libcxx/include regex, libcxx/src locale.cpp

Nov 2, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/irbuilder-extract-refactor

Merge commit 'd041af3019984f505530bac3acb94ca2f13f33cd^' into users/meinersbur/irbuilder-extract-refactor

Delta		File
+27,218	-219	llvm/test/CodeGen/AMDGPU/bf16.ll
+11,620	-11,712	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+4,442	-5,290	libcxx/src/locale.cpp
+3,731	-4,881	libcxx/include/regex
+2,972	-4,148	llvm/test/CodeGen/AArch64/vecreduce-add.ll
+3,242	-3,243	llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
+53,225	-29,493	7,802 files not shown
+546,928	-278,424	7,808 files