LLVM / project - FreshBSD

LLVM/project 46a7cba — llvm/test/MC/AMDGPU gfx11_asm_vopcx.s gfx12_asm_vop3cx_dpp16.s, llvm/test/MC/Disassembler/AMDGPU gfx12_dasm_vop3cx_dpp16.txt gfx11_dasm_vopcx.txt

users/HighCommander4/clangd-issue-1249

Merge branch 'main' into users/HighCommander4/clangd-issue-1249

Delta		File
+1,195	-195	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
+585	-390	llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s
+533	-416	llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
+546	-390	llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
+481	-364	llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopcx.s
+650	-195	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt
+3,990	-1,950	751 files not shown
+25,101	-12,229	757 files

LLVM/project 951d0fb — llvm/test/CodeGen/RISCV/rvv intrinsic-vector-match.ll, llvm/test/MC/AMDGPU gfx11_asm_vopcx.s gfx12_asm_vop3cx_dpp16.s

Jan 23 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpimproved-reduction-costcodegen

Address comments

Created using spr 1.3.5

Delta		File
+1,195	-195	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
+640	-678	llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
+413	-682	llvm/test/CodeGen/RISCV/rvv/intrinsic-vector-match.ll
+585	-390	llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s
+533	-416	llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
+546	-390	llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
+3,912	-2,751	955 files not shown
+29,787	-15,763	961 files

LLVM/project 6a3c6bb — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

Jan 22 by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvfiximprove-max-safe-distance-analysis

Rebase, rework

Created using spr 1.3.5

Delta		File
+30,641	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,981	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,981	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+165,052	-0	6,598 files not shown
+1,277,792	-184,410	6,604 files

LLVM/project 25767fc — clang/test/CodeGen atomic-test-and-set.c, clang/unittests/Analysis ExprMutationAnalyzerTest.cpp

Jan 22 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpreduce-number-of-alternate-instruction-where-possible

Fix a crash

Created using spr 1.3.5

Delta		File
+640	-678	llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
+413	-682	llvm/test/CodeGen/RISCV/rvv/intrinsic-vector-match.ll
+395	-0	clang/unittests/Analysis/ExprMutationAnalyzerTest.cpp
+361	-0	llvm/utils/TableGen/SDNodeInfoEmitter.cpp
+345	-0	clang/test/CodeGen/atomic-test-and-set.c
+0	-285	mlir/test/Dialect/Tosa/broadcast.mlir
+2,154	-1,645	675 files not shown
+12,157	-6,435	681 files

LLVM/project e30b703 — mlir/lib/Bindings/Python IRCore.cpp IRModule.h

Jan 22 by Peter Hawkins via GitHub on ⎇

main

[mlir:python] Construct PyOperation objects in-place on the Python heap. (#123813)

Currently we make two memory allocations for each PyOperation: a Python
object, and the PyOperation class itself. With some care we can allocate
the PyOperation inline inside the Python object, saving us a malloc()
call per object and perhaps improving cache locality.

Delta		File
+20	-8	mlir/lib/Bindings/Python/IRCore.cpp
+2	-1	mlir/lib/Bindings/Python/IRModule.h
+22	-9	2 files

LLVM/project f4125e0 — mlir/lib/Bindings/Python IRCore.cpp IRModule.h, mlir/test/mlir-tblgen op-python-bindings.td

Jan 22 by Peter Hawkins via GitHub on ⎇

main

[mlir python] Change PyOpView constructor to construct operations. (#123777)

Previously ODS-generated Python operations had code like this:
```
  super().__init__(self.build_generic(attributes=attributes, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip))
```

we change it to:
```
  super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)
```

This:
a) avoids an extra call dispatch (to `build_generic`), and
b) passes the class attributes directly to the constructor. Benchmarks
show that it is faster to pass these as arguments rather than having the
C++ code look up attributes on the class.

This PR improves the timing of the following benchmark on my workstation

    [16 lines not shown]

Delta		File
+48	-32	mlir/test/mlir-tblgen/op-python-bindings.td
+60	-13	mlir/lib/Bindings/Python/IRCore.cpp
+11	-7	mlir/lib/Bindings/Python/IRModule.h
+5	-1	mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp
+124	-53	4 files

LLVM/project bba7783 — clang/include/clang/Basic BuiltinsX86.td, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll

Jan 20 by Alexey Bataev on ⎇

users/alexey-bataev/spr/riscvcodegenttiuse-processshufflemasks-for-cost-estimationsactual-per-register-shuffles

Rebase

Created using spr 1.3.5

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+233	-6,579	llvm/test/DebugInfo/NVPTX/debug-info.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+5,378	-4	clang/include/clang/Basic/BuiltinsX86.td
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+22,820	-18,715	5,948 files not shown
+312,261	-154,884	5,954 files

LLVM/project f4fb73a — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

Jan 20 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'users/meinersbur/flang_runtime' into users/meinersbur/flang_runtime_shared

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+233	-6,579	llvm/test/DebugInfo/NVPTX/debug-info.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,429	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+19,871	-21,121	4,698 files not shown
+229,000	-108,851	4,704 files

LLVM/project bed5b1f — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

Jan 20 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'users/meinersbur/flang_runtime_move-files' into users/meinersbur/flang_runtime

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+233	-6,579	llvm/test/DebugInfo/NVPTX/debug-info.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,429	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+19,871	-21,121	4,698 files not shown
+229,000	-108,851	4,704 files

LLVM/project a8c87d7 — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

Jan 20 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'users/meinersbur/flang_runtime_flang_rt' into users/meinersbur/flang_runtime_move-files

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+233	-6,579	llvm/test/DebugInfo/NVPTX/debug-info.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,429	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+19,871	-21,121	4,698 files not shown
+229,000	-108,851	4,704 files

LLVM/project 1f3d71e — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

Jan 20 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'users/meinersbur/flang_runtime_FLANG_INCLUDE_RUNTIME' into users/meinersbur/flang_runtime_flang_rt

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+233	-6,579	llvm/test/DebugInfo/NVPTX/debug-info.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,429	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+19,871	-21,121	4,698 files not shown
+229,000	-108,851	4,704 files

LLVM/project b68700b — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

Jan 20 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'users/meinersbur/flang_runtime_Testing' into users/meinersbur/flang_runtime_FLANG_INCLUDE_RUNTIME

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+233	-6,579	llvm/test/DebugInfo/NVPTX/debug-info.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,429	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+19,871	-21,121	4,698 files not shown
+229,000	-108,851	4,704 files

LLVM/project f007594 — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

Jan 20 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'users/meinersbur/flang_runtime_FortranSupport' into users/meinersbur/flang_runtime_Testing

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+233	-6,579	llvm/test/DebugInfo/NVPTX/debug-info.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,429	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+19,871	-21,121	4,698 files not shown
+229,000	-108,851	4,704 files

LLVM/project a519f98 — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

Jan 20 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'users/meinersbur/flang_runtime_FortranDecimal' into users/meinersbur/flang_runtime_FortranSupport

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+233	-6,579	llvm/test/DebugInfo/NVPTX/debug-info.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,429	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+19,871	-21,121	4,698 files not shown
+229,000	-108,850	4,704 files

LLVM/project f2abcde — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

Jan 20 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'main' into users/meinersbur/flang_runtime_FortranDecimal

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+233	-6,579	llvm/test/DebugInfo/NVPTX/debug-info.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,429	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+19,871	-21,121	4,699 files not shown
+229,007	-108,850	4,705 files

LLVM/project df1b617 — clang/include/clang/Basic BuiltinsX86.td, llvm/test/CodeGen/AMDGPU dagcombine-fmul-sel.ll

Jan 20 by ZhaoQi via GitHub on ⎇

users/zhaoqi5/pre-commit-tlsle-mergebaseoffset-tests

Merge branch 'main' into users/zhaoqi5/pre-commit-tlsle-mergebaseoffset-tests

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+5,378	-4	clang/include/clang/Basic/BuiltinsX86.td
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+3,130	-1,856	llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+25,717	-13,992	5,312 files not shown
+294,216	-135,084	5,318 files

LLVM/project eab9b11 — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

Jan 17 by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvfix-max-safe-elements-calculations

Rebase, address comments

Created using spr 1.3.5

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,429	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+2,263	-2,208	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+21,901	-16,750	3,291 files not shown
+182,635	-84,891	3,297 files

LLVM/project f1a1be0 — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

Jan 17 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpimproved-reduction-costcodegen

Rebase

Created using spr 1.3.5

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,429	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+2,263	-2,208	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+21,901	-16,750	4,167 files not shown
+210,098	-98,516	4,173 files

LLVM/project 31f9136 — clang/include/clang/Basic BuiltinsX86.td, llvm/test/CodeGen/AMDGPU dagcombine-fmul-sel.ll

Jan 17 by ZhaoQi via GitHub on ⎇

users/zhaoqi5/avoid-scheduling-and-attach-relax

Merge branch 'main' into users/zhaoqi5/avoid-scheduling-and-attach-relax

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+5,378	-4	clang/include/clang/Basic/BuiltinsX86.td
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+3,130	-1,856	llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+25,717	-13,992	4,774 files not shown
+272,955	-129,723	4,780 files

LLVM/project a8d8e9b — clang/test/CodeGen/AArch64/fp8-intrinsics acle_sve2_fp8_reinterpret.c, llvm/test/CodeGen/RISCV memcpy.ll

Jan 14 by Paul Kirth on ⎇

users/ilovepi/spr/reapply-fuchsiacmake-allow-using-fatlto-when-building-runtimes-119252

Rebase on main

Created using spr 1.3.6-beta.1

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,182	-0	clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
+2,164	-0	llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
+760	-760	llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
+1,375	-0	llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
+676	-359	llvm/test/CodeGen/RISCV/memcpy.ll
+12,996	-6,464	1,397 files not shown
+57,771	-26,846	1,403 files

LLVM/project dfe7d7b — clang/test/CodeGen/AArch64/fp8-intrinsics acle_sve2_fp8_reinterpret.c, llvm/test/CodeGen/RISCV memcpy.ll

Jan 14 by Paul Kirth on ⎇

users/ilovepi/spr/main.reapply-fuchsiacmake-allow-using-fatlto-when-building-runtimes-119252

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,182	-0	clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
+2,164	-0	llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
+760	-760	llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
+1,375	-0	llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
+676	-359	llvm/test/CodeGen/RISCV/memcpy.ll
+12,996	-6,464	1,397 files not shown
+57,771	-26,846	1,403 files

LLVM/project 31067ba — clang/test/CodeGen/AArch64/fp8-intrinsics acle_sve2_fp8_reinterpret.c, llvm/test/CodeGen/RISCV memcpy.ll

Jan 14 by Paul Kirth on ⎇

users/ilovepi/spr/libunwindcmake-compile-_unwind-routines-with-fexceptions

Rebase on main

Created using spr 1.3.6-beta.1

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,182	-0	clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
+2,164	-0	llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
+760	-760	llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
+1,375	-0	llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
+676	-359	llvm/test/CodeGen/RISCV/memcpy.ll
+12,996	-6,464	1,397 files not shown
+57,771	-26,846	1,403 files

LLVM/project 7aeb1c9 — llvm/test/MC/AMDGPU gfx12_asm_vop3c_dpp16-fake16.s gfx12_asm_vop3cx-fake16.s, llvm/test/MC/Disassembler/AMDGPU gfx11_dasm_vopc.txt gfx11_dasm_vop3_from_vopc.txt

Jan 13 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpinitial-non-power-of-2-but-still-whole-register-for-remaining-nodes

Rebase, address comments

Created using spr 1.3.5

Delta		File
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,583	-2,582	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,413	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+2,205	-2,204	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+2,065	-2,062	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
+3,414	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3cx-fake16.s
+19,327	-9,258	1,584 files not shown
+100,551	-44,646	1,590 files

LLVM/project e2c49a4 — mlir/lib/Bindings/Python IRCore.cpp IRModule.h

Jan 13 by Peter Hawkins via GitHub on ⎇

main

[mlir python] Add locking around PyMlirContext::liveOperations. (#122720)

In JAX, I observed a race between two PyOperation destructors from
different threads updating the same `liveOperations` map, despite not
intentionally sharing the context between different threads. Since I
don't think we can be completely sure when GC happens and on which
thread, it seems safest simply to add locking here.

We may also want to explicitly support sharing a context between threads
in the future, which would require this change or something similar.

Delta		File
+31	-12	mlir/lib/Bindings/Python/IRCore.cpp
+3	-0	mlir/lib/Bindings/Python/IRModule.h
+34	-12	2 files

LLVM/project f136c80 — mlir/cmake/modules AddMLIRPython.cmake, mlir/docs/Bindings Python.md

Jan 13 by vfdev via GitHub on ⎇

main

Enabled freethreading support in MLIR python bindings (#122684)

Reland reverted https://github.com/llvm/llvm-project/pull/107103 with
the fixes for Python 3.8

cc @jpienaar

Co-authored-by: Peter Hawkins <phawkins at google.com>

Delta		File
+518	-0	mlir/test/python/multithreaded_tests.py
+40	-0	mlir/docs/Bindings/Python.md
+27	-4	mlir/lib/Bindings/Python/IRCore.cpp
+20	-1	mlir/cmake/modules/AddMLIRPython.cmake
+16	-2	mlir/lib/Bindings/Python/IRModule.cpp
+11	-1	mlir/lib/Bindings/Python/Globals.h
+632	-8	4 files not shown
+640	-17	10 files

LLVM/project 3f1486f — mlir/cmake/modules AddMLIRPython.cmake, mlir/docs/Bindings Python.md

Jan 12 by Jacques Pienaar on ⎇

main

Revert "Added free-threading CPython mode support in MLIR Python bindings (#107103)"

Breaks on 3.8, rolling back to avoid breakage while fixing.

This reverts commit 9dee7c44491635ec9037b90050bcdbd3d5291e38.

Delta		File
+0	-531	mlir/test/python/multithreaded_tests.py
+0	-40	mlir/docs/Bindings/Python.md
+4	-27	mlir/lib/Bindings/Python/IRCore.cpp
+1	-20	mlir/cmake/modules/AddMLIRPython.cmake
+2	-16	mlir/lib/Bindings/Python/IRModule.cpp
+1	-11	mlir/lib/Bindings/Python/Globals.h
+8	-645	3 files not shown
+16	-649	9 files

LLVM/project 9dee7c4 — mlir/cmake/modules AddMLIRPython.cmake, mlir/docs/Bindings Python.md

Jan 12 by vfdev via GitHub on ⎇

main

Added free-threading CPython mode support in MLIR Python bindings (#107103)

Related to https://github.com/llvm/llvm-project/issues/105522

Description:

This PR is a joint work with Peter Hawkins (@hawkinsp) originally done
by myself for pybind11 and then reworked to nanobind based on Peter's
branch: https://github.com/hawkinsp/llvm-project/tree/nbdev .

- Added free-threading CPython mode support for MLIR Python bindings
- Added a test which can reveal data races when cpython and LLVM/MLIR
compiled with TSAN

Context:
- Related to https://github.com/google/jax/issues/23073

Co-authored-by: Peter Hawkins <phawkins at google.com>

Delta		File
+531	-0	mlir/test/python/multithreaded_tests.py
+40	-0	mlir/docs/Bindings/Python.md
+27	-4	mlir/lib/Bindings/Python/IRCore.cpp
+20	-1	mlir/cmake/modules/AddMLIRPython.cmake
+16	-2	mlir/lib/Bindings/Python/IRModule.cpp
+11	-1	mlir/lib/Bindings/Python/Globals.h
+645	-8	3 files not shown
+649	-16	9 files

LLVM/project f5de3e9 — clang/include/clang/Basic BuiltinsX86.td, libc/include math.yaml

Jan 9 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/tri-remove-reserved-registers-in-getregpressuresetlimit

Rebase

Created using spr 1.3.6-beta.1

Delta		File
+5,378	-4	clang/include/clang/Basic/BuiltinsX86.td
+3,130	-1,856	llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+0	-4,162	llvm/test/CodeGen/AVR/branch-relaxation-long.ll
+2,765	-0	llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
+2,715	-7	llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
+2,630	-0	libc/include/math.yaml
+16,618	-6,029	4,971 files not shown
+222,568	-106,467	4,977 files

LLVM/project 6b58c85 — clang/include/clang/Basic BuiltinsX86.td, libc/include math.yaml

Jan 9 by Pengcheng Wang via Wang Pengcheng on ⎇

users/wangpc-pp/spr/main.tri-remove-reserved-registers-in-getregpressuresetlimit

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+5,378	-4	clang/include/clang/Basic/BuiltinsX86.td
+3,130	-1,856	llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+0	-4,162	llvm/test/CodeGen/AVR/branch-relaxation-long.ll
+2,765	-0	llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
+2,715	-7	llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
+2,630	-0	libc/include/math.yaml
+16,618	-6,029	4,970 files not shown
+222,521	-106,435	4,976 files

LLVM/project bdba932 — clang/include/clang/Basic BuiltinsX86.td, libc/hdrgen/yaml math.yaml

Jan 9 by wanglei on ⎇

users/wangleiat/spr/lldbloongarch-add-lsx-and-lasx-register-definitions-and-operations

rewrite test case

Created using spr 1.3.5-bogner

Delta		File
+5,378	-4	clang/include/clang/Basic/BuiltinsX86.td
+3,130	-1,856	llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+0	-4,162	llvm/test/CodeGen/AVR/branch-relaxation-long.ll
+2,765	-0	llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
+2,630	-0	libc/include/math.yaml
+0	-2,629	libc/hdrgen/yaml/math.yaml
+13,903	-8,651	4,211 files not shown
+171,634	-84,626	4,217 files