LLVM/project 552f6c9llvm/test/CodeGen/X86 vector-interleaved-store-i8-stride-7.ll vector-interleaved-store-i16-stride-6.ll, llvm/test/Instrumentation/MemorySanitizer/AArch64 arm64-ld1.ll

rebase

Created using spr 1.3.4
DeltaFile
+3,128-3,170llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,487-2,510llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+2,099-2,096llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053-2,052llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+3,860-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,716-1,780llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
+15,343-11,6084,566 files not shown
+159,258-104,3134,572 files

LLVM/project 85e290bllvm/test/CodeGen/AMDGPU bf16.ll, llvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm70.ll

Merge branch 'main' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,350-4,196llvm/test/CodeGen/AMDGPU/bf16.ll
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+90,478-10,3696,999 files not shown
+425,286-177,3787,005 files

LLVM/project 2ece26fllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

Update OB name from `type` to `callee_type`.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+164,956-024,133 files not shown
+2,356,601-721,36324,139 files

LLVM/project 9c94049llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
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+164,956-024,129 files not shown
+2,356,435-721,19824,135 files

LLVM/project 05307cfllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

Update LTO compilation CodeGen flag for call-graph-section.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-024,129 files not shown
+2,356,435-721,19824,135 files

LLVM/project de23806llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-024,128 files not shown
+2,356,423-721,19324,134 files

LLVM/project c44c905mlir/lib/Dialect/Tosa/IR TosaOps.cpp, mlir/test/Dialect/Tosa level_check.mlir invalid.mlir

[mlir][tosa] Add error if verification to pooling operators (#130052)

This commit adds the following checks to avg_pool2d and max_pool2d TOSA
operations:
- check kernel values are >= 1
- check stride values are >= 1
- check padding values are >= 0
- check padding values are less than kernel sizes
- check output shape matches the expected output shape

Signed-off-by: Luke Hutton <luke.hutton at arm.com>
DeltaFile
+38-103mlir/test/Dialect/Tosa/level_check.mlir
+99-0mlir/test/Dialect/Tosa/invalid.mlir
+96-2mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+9-9mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
+242-1144 files

LLVM/project 2c57c89llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll

Merge branch 'main' of https://github.com/llvm/llvm-project into remove-old-res-middle
DeltaFile
+2,099-2,096llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053-2,052llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434-1,828llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+2,915-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+1,434-1,418llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940-1,896llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+10,875-9,2902,274 files not shown
+97,298-62,3572,280 files

LLVM/project ed3f871llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-cttz-vp.ll

Merge branch 'main' into users/vitalybuka/spr/ir-optimize-cfi-in-writecombinedglobalvaluesummary
DeltaFile
+2,099-2,096llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053-2,052llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434-1,828llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+1,434-1,418llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940-1,896llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+1,240-1,230llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
+9,200-10,5201,240 files not shown
+47,494-33,1451,246 files

LLVM/project 9274743llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Analysis/CostModel/AArch64 arith-widening.ll sve-intrinsics.ll

release note

Created using spr 1.3.5-bogner
DeltaFile
+940-1,896llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+741-741llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
+660-658llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+545-533llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
+464-470llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
+74-698llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+3,424-4,996379 files not shown
+13,173-12,743385 files

LLVM/project 913d077mlir/include/mlir/Dialect/Tosa/IR TosaComplianceData.h.inc, mlir/lib/Conversion/TosaToLinalg TosaToLinalg.cpp

[mlir][tosa] Change Rescale zero points to be inputs (#130340)

*Update RescaleOp to use zero-point as operands instead of attributes.
 *Check input_zp data type against the input and output_zp data type
   against the output.

Signed-off-by: Peng Sun <peng.sun at arm.com>
Co-authored-by: Peng Sun <peng.sun at arm.com>
DeltaFile
+62-35mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+54-18mlir/test/Dialect/Tosa/invalid.mlir
+45-23mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
+22-8mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
+13-10mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+10-3mlir/test/lib/Dialect/Tosa/TosaTestPasses.cpp
+206-9710 files not shown
+261-11716 files

LLVM/project 397c487llvm/test/CodeGen/AMDGPU global_atomics_scan_fadd.ll global_atomics_scan_fsub.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-cttz-vp.ll

Merge remote-tracking branch 'origin/main' into users/ccc03-08-_astmatcher_templateargumentcountis_support_functiondecl_
DeltaFile
+1,434-1,828llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+1,246-1,246llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+1,246-1,246llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+1,214-1,214llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+1,214-1,214llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+726-1,509llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
+7,080-8,2571,023 files not shown
+37,140-28,4421,029 files

LLVM/project 3fb8cb6mlir/lib/Conversion/TosaToArith TosaToArith.cpp, mlir/lib/Conversion/TosaToLinalg TosaToLinalg.cpp

[mlir][tosa] Add support for EXT-DOUBLEROUND and EXT-INEXACTROUND (#130337)

DeltaFile
+25-15mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
+20-19mlir/test/Dialect/Tosa/invalid.mlir
+32-1mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
+30-0mlir/test/Dialect/Tosa/invalid_extension.mlir
+12-4mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
+12-2mlir/lib/Conversion/TosaToArith/TosaToArith.cpp
+131-4119 files not shown
+186-6325 files

LLVM/project 483c23fmlir/lib/Dialect/Tosa/IR TosaOps.cpp ShardingInterfaceImpl.cpp, mlir/test/Conversion/TosaToLinalg tosa-to-linalg.mlir

[mlir][tosa] Switch zero point of negate to input variable type (#129758)

This commit changes the zero point attribute to an input to align with
the 1.0 spec.

Signed-off-by: Tai Ly <tai.ly at arm.com>
Co-authored-by: Luke Hutton <luke.hutton at arm.com>
DeltaFile
+86-15mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+64-0mlir/test/Dialect/Tosa/invalid.mlir
+20-30mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
+43-2mlir/test/Dialect/Tosa/canonicalize.mlir
+41-1mlir/lib/Dialect/Tosa/IR/ShardingInterfaceImpl.cpp
+27-4mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
+281-5211 files not shown
+364-9117 files

LLVM/project dc66ca4llvm/test/CodeGen/AMDGPU llvm.amdgcn.smfmac.gfx950.ll, llvm/test/CodeGen/RISCV xqccmp-push-pop-popret.ll

Rebase, address comments

Created using spr 1.3.5
DeltaFile
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+3,951-0llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+3,860-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,746-1,734llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,348-1,952llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+17,078-9,8592,714 files not shown
+131,118-67,3922,720 files

LLVM/project d4e79afllvm/test/CodeGen/AMDGPU global_atomics_scan_fsub.ll global_atomics_scan_fadd.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll qci-interrupt-attr-fpr.ll

Merge branch 'main' into users/kparzysz/spr/o03-cancel-directive-name
DeltaFile
+2,927-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821-0llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+1,246-1,246llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+1,246-1,246llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+1,214-1,214llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+1,214-1,214llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+10,668-4,9201,301 files not shown
+51,893-31,2131,307 files

LLVM/project 7dc7264llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'main' into users/ylzsx/r-tls-noie
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+29,745-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+203,722-016,100 files not shown
+2,040,184-604,85516,106 files

LLVM/project dfbadfcmlir/lib/Conversion/TosaToLinalg TosaToLinalgNamed.cpp, mlir/lib/Dialect/Tosa/IR TosaOps.cpp

[mlir][tosa] Change MatMul zero-point to inputs (#130332)

* Change zero-point attributes to inputs
* Fix relevant mlir tests
* Enhance ShardingInterface in MatMul

Signed-off-by: Udaya Ranga <udaya.ranga at arm.com>
Co-authored-by: Udaya Ranga <udaya.ranga at arm.com>
DeltaFile
+40-26mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+39-27mlir/test/Dialect/Mesh/sharding-propagation.mlir
+41-1mlir/test/Dialect/Tosa/invalid.mlir
+32-9mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
+23-13mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
+18-6mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
+193-829 files not shown
+239-10115 files

LLVM/project 2619c2emlir/lib/Conversion/TosaToLinalg TosaToLinalgNamed.cpp, mlir/lib/Dialect/Tosa/IR TosaOps.cpp

Revert "[mlir][tosa] Change MatMul zero-point to inputs" (#130330)

Reverts llvm/llvm-project#129785. Need rebase.
DeltaFile
+27-39mlir/test/Dialect/Mesh/sharding-propagation.mlir
+26-40mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+1-41mlir/test/Dialect/Tosa/invalid.mlir
+9-32mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
+13-23mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
+6-18mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
+82-1939 files not shown
+99-23315 files

LLVM/project b6b7f43clang/lib/CIR/CodeGen CIRGenExprConstant.cpp CIRGenDecl.cpp, clang/tools/amdgpu-arch AMDGPUArchByHIP.cpp

less copying

Created using spr 1.3.4
DeltaFile
+309-0clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
+291-1mlir/test/Dialect/Tosa/ops.mlir
+274-0llvm/test/CodeGen/X86/finite-libcalls.ll
+170-11clang/lib/CIR/CodeGen/CIRGenDecl.cpp
+163-0llvm/unittests/Support/Caching.cpp
+128-5clang/tools/amdgpu-arch/AMDGPUArchByHIP.cpp
+1,335-1750 files not shown
+2,482-20356 files

LLVM/project 106c964mlir/lib/Conversion/TosaToLinalg TosaToLinalgNamed.cpp, mlir/lib/Dialect/Tosa/IR TosaOps.cpp

[mlir][tosa] Change MatMul zero-point to inputs (#129785)

* Change zero-point attributes to inputs
* Fix relevant mlir tests
* Enhance ShardingInterface in MatMul

Signed-off-by: Udaya Ranga <udaya.ranga at arm.com>
Co-authored-by: Udaya Ranga <udaya.ranga at arm.com>
DeltaFile
+39-27mlir/test/Dialect/Mesh/sharding-propagation.mlir
+40-26mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+41-1mlir/test/Dialect/Tosa/invalid.mlir
+32-9mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
+23-13mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
+18-6mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
+193-829 files not shown
+233-9915 files

LLVM/project 5685defmlir/include/mlir/Dialect/Tosa/Utils QuantUtils.h, mlir/lib/Conversion/TosaToLinalg TosaToLinalg.cpp

[mlir][tosa] Convert RESCALE op multiplier and shift from attributes to inputs (#129720)

DeltaFile
+181-0mlir/test/Dialect/Tosa/invalid.mlir
+141-1mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+25-9mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
+19-3mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
+20-0mlir/include/mlir/Dialect/Tosa/Utils/QuantUtils.h
+12-8mlir/test/lib/Dialect/Tosa/TosaTestPasses.cpp
+398-218 files not shown
+435-3614 files

LLVM/project 33f623dllvm/test/CodeGen/AMDGPU vni8-across-blocks.ll shufflevector-physreg-copy.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll qci-interrupt-attr-fpr.ll

Merge branch 'main' into users/kparzysz/spr/o02-metadirective-flush
DeltaFile
+2,927-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821-0llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+603-1,206llvm/test/CodeGen/X86/matrix-multiply.ll
+706-540llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
+812-407llvm/test/CodeGen/Thumb2/mve-vld3.ll
+795-0llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
+8,664-2,153747 files not shown
+23,408-10,802753 files

LLVM/project 2ff290bllvm/test/CodeGen/RISCV xqccmp-push-pop-popret.ll qci-interrupt-attr.ll, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-7.ll vector-interleaved-store-i8-stride-7.ll

Rebase

Created using spr 1.3.5
DeltaFile
+3,951-0llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+3,860-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,746-1,734llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,532-1,534llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,927-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821-0llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+16,837-3,2681,830 files not shown
+73,594-27,5911,836 files

LLVM/project 472c2e3mlir/test/Dialect/Tosa constant-op-fold.mlir canonicalize.mlir

[mlir][tosa] Update value to values for ConstOp and ConstShapeOp (#129943)

Updated the dialect to match TOSA v1.0 specification for ConstOp and
ConstShapeOp (https://www.mlplatform.org/tosa/tosa_spec.html#_const).

Also updated lit tests

---------

Signed-off-by: Jerry Ge <jerry.ge at arm.com>
DeltaFile
+216-216mlir/test/Dialect/Tosa/constant-op-fold.mlir
+129-129mlir/test/Dialect/Tosa/canonicalize.mlir
+95-95mlir/test/Dialect/Tosa/invalid.mlir
+76-76mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
+49-49mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
+49-49mlir/test/Dialect/Tosa/tosa-reduce-transposes.mlir
+614-61429 files not shown
+980-97835 files

LLVM/project 8cb72bdllvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm60.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

reb

Created using spr 1.3.4
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+88,808-6,1733,815 files not shown
+253,453-75,5073,821 files

LLVM/project 7e10ecdmlir/lib/Conversion/TosaToTensor TosaToTensor.cpp, mlir/lib/Dialect/Tosa/IR TosaCanonicalizations.cpp TosaOps.cpp

[mlir][tosa] Remove optional for pad_const and remove input_zp attr for PadOp (#129336)

Always generated pad_const and remove input_zp attr for PadOp. 

- Co-authored-by: Udaya Ranga <udaya.ranga at arm.com>
- Co-authored-by: Tai Ly <tai.ly at arm.com>

Signed-off-by: Jerry Ge <jerry.ge at arm.com>
DeltaFile
+37-47mlir/lib/Conversion/TosaToTensor/TosaToTensor.cpp
+25-24mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
+0-47mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
+22-22mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+12-19mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
+15-10mlir/test/Conversion/TosaToTensor/tosa-to-tensor.mlir
+111-1699 files not shown
+151-21115 files

LLVM/project 8c41ae6lldb/tools/lldb-dap lldb-dap.cpp, llvm/test/CodeGen/AMDGPU bf16.ll

Merge branch 'main' into users/meinersbur/flang_runtime_premerge
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,194-3,880llvm/test/CodeGen/AMDGPU/bf16.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+309-5,049lldb/tools/lldb-dap/lldb-dap.cpp
+90,138-8,9295,013 files not shown
+307,445-100,3025,019 files

LLVM/project 25a29cemlir/include/mlir/Dialect/Tosa/IR TosaOps.td, mlir/lib/Conversion/TosaToLinalg TosaToLinalgNamed.cpp

[mlir][tosa] Switch zero point of avgpool2d to input variable type (#128983)

This commit changes the TOSA operator AvgPool2d's zero point attributes
to inputs to align with TOSA 1.0 spec.

Signed-off-by: Luke Hutton <luke.hutton at arm.com>
Co-authored-by: Luke Hutton <luke.hutton at arm.com>
DeltaFile
+96-78mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+51-23mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
+52-8mlir/test/Dialect/Tosa/invalid.mlir
+26-26mlir/test/Dialect/Tosa/level_check.mlir
+27-19mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
+17-9mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
+269-16312 files not shown
+355-20418 files

LLVM/project fd374e5llvm/test/CodeGen/AArch64 sve-partial-reduce-dot-product.ll, llvm/test/CodeGen/AMDGPU llvm.amdgcn.smfmac.gfx950.ll llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll

Rebase, address comments

Created using spr 1.3.5
DeltaFile
+1,348-1,952llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+760-23mlir/test/Dialect/Tosa/level_check.mlir
+172-258llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
+285-102mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
+192-194llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
+342-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-umaxv.ll
+3,099-2,529382 files not shown
+9,637-5,261388 files