LLVM/project 179e174mlir/lib/Dialect/Bufferization/Transforms OneShotAnalysis.cpp

[mlir][bufferization][NFC] More documentation for `runOneShotBufferize` (#90445)

DeltaFile
+17-4mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp
+17-41 files

LLVM/project 55c6bdallvm/test/CodeGen/AMDGPU rem_i128.ll, llvm/test/CodeGen/RISCV half-round-conv-sat.ll float-round-conv-sat.ll

Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."

This reverts commit 16bd10a38730fed27a3bf111076b8ef7a7e7b3ee.

Re-applies:
    b3c55b707110084a9f50a16aade34c3be6fa18da - "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)"
    8e2f6495c0bac1dd6ee32b6a0d24152c9c343624 - "[DAGCombiner] Do not always fold FREEZE over BUILD_VECTOR (#85932)"
    73472c5996716cda0dbb3ddb788304e0e7e6a323 - "[SelectionDAG] Treat CopyFromReg as freezing the value (#85932)"

with a fix in DAGCombiner::visitFREEZE.
DeltaFile
+312-336llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
+269-264llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
+246-237llvm/test/CodeGen/AMDGPU/rem_i128.ll
+192-193llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
+138-150llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
+119-149llvm/test/CodeGen/RISCV/half-convert.ll
+1,276-1,32944 files not shown
+2,255-2,32950 files

LLVM/project 95395eellvm/test/CodeGen/X86 memcmp-minsize.ll memcmp-pgso.ll

[X86] memcmp tests - merge check-prefixes. NFC.
DeltaFile
+3-3llvm/test/CodeGen/X86/memcmp-minsize.ll
+3-3llvm/test/CodeGen/X86/memcmp-pgso.ll
+3-3llvm/test/CodeGen/X86/memcmp-optsize.ll
+2-2llvm/test/CodeGen/X86/memcmp-optsize-x32.ll
+2-2llvm/test/CodeGen/X86/memcmp-minsize-x32.ll
+2-2llvm/test/CodeGen/X86/memcmp-pgso-x32.ll
+15-156 files

LLVM/project b35bdb1llvm/test/tools/llvm-rc dialog-with-menu.test, llvm/test/tools/llvm-rc/Inputs dialog-with-menu.rc

llvm-rc: add support for MENU in DIALOG(EX) (#89409)

Adds support for `MENU` in `DIALOG(EX)` to `llvm-rc`. Fixes #49559.
DeltaFile
+32-0llvm/test/tools/llvm-rc/dialog-with-menu.test
+16-0llvm/test/tools/llvm-rc/Inputs/dialog-with-menu.rc
+13-0llvm/tools/llvm-rc/ResourceScriptStmt.h
+7-3llvm/tools/llvm-rc/ResourceFileWriter.cpp
+7-0llvm/tools/llvm-rc/ResourceScriptParser.cpp
+4-1llvm/tools/llvm-rc/ResourceFileWriter.h
+79-43 files not shown
+86-49 files

LLVM/project 37f2928clang/test/CXX/drs dr24xx.cpp dr25xx.cpp, clang/www cxx_dr_status.html make_cxx_dr_status

[clang] Use `cwg_index.html` from GitHub for DR status page (#90352)

Currently we're using official publication of CWG issue list available
at https://www.open-std.org/jtc1/sc22/wg21/docs/cwg_index.html.
Unfortunately, it's not updated as frequently as we sometimes need. For
instance, recently there was a confusion during review of CWG2149 test
(https://github.com/llvm/llvm-project/pull/90079#discussion_r1580174003).
This patch changes our `make_cxx_dr_status` script to use issue list
from CWG GitHub repository. I confirmed with CWG chair that this is the
most up-to-date source of information on CWG issues.

Changing the source of issue list uncovered previously unhandled
"tentatively ready" status of an issue. This status is considered
unresolved by the script (like `open`, `drafting`, and `review`), as the
resolution might change during face-to-face CWG meeting.

I also noticed that CWG decided to handle 2561 differently from what
we're doing, so this DR is now considered not available in Clang,
despite being declared as available since 18. CC @cor3ntin.

    [3 lines not shown]
DeltaFile
+397-156clang/www/cxx_dr_status.html
+3-3clang/www/make_cxx_dr_status
+2-2clang/test/CXX/drs/dr24xx.cpp
+3-1clang/test/CXX/drs/dr25xx.cpp
+1-1clang/test/CXX/drs/cwg2149.cpp
+1-1clang/test/CXX/drs/dr20xx.cpp
+407-1642 files not shown
+410-1658 files

LLVM/project f2452d4clang/lib/AST/Interp ByteCodeExprGen.cpp, clang/test/AST/Interp records.cpp

[clang][Interp] Implement zero-init for record types
DeltaFile
+25-2clang/lib/AST/Interp/ByteCodeExprGen.cpp
+13-2clang/test/AST/Interp/records.cpp
+38-42 files

LLVM/project 5b18775llvm/lib/Target/AMDGPU SIMachineFunctionInfo.cpp

[AMDGPU] Fix typo in #89773

Fixes #90281
DeltaFile
+1-1llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+1-11 files

LLVM/project 2914a11llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU hard-clauses.mir hard-clauses-img-gfx11.mir

[AMDGPU] Fix hard clausing for image instructions on gfx12 (#90221)

Also updated hard-clauses.mir to have separate versions for gfx11 and
gfx12 since
the MIR instructions are different for each of them.
DeltaFile
+184-51llvm/test/CodeGen/AMDGPU/hard-clauses.mir
+40-0llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx11.mir
+40-0llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx12.mir
+34-0llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx10.mir
+4-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+302-535 files

LLVM/project 0c8151alldb/test/API/functionalities/fork/concurrent_vfork TestConcurrentVFork.py

[lldb][Test] Disable concurrent vfork tests on Arm and AArch64 Linux (again)

5f3e106de3cd5ce6d7ba37fb11f6ad740cb430c5 made them a lot more stable but
there are still occasions where they will timeout and leave behind stale
processes.

For example https://lab.llvm.org/buildbot/#/builders/96/builds/56699.
DeltaFile
+16-0lldb/test/API/functionalities/fork/concurrent_vfork/TestConcurrentVFork.py
+16-01 files

LLVM/project d72146fclang/lib/CodeGen CodeGenFunction.h CGExprAgg.cpp, clang/test/CodeGenCXX control-flow-in-stmt-expr.cpp

Re-apply "Emit missing cleanups for stmt-expr" and other commits (#89154)

Latest diff:
https://github.com/llvm/llvm-project/pull/89154/files/f1ab4c2677394bbfc985d9680d5eecd7b2e6a882..adf9bc902baddb156c83ce0f8ec03c142e806d45

We address two additional bugs here: 

### Problem 1: Deactivated normal cleanup still runs, leading to
double-free
Consider the following:
```cpp

struct A { };

struct B { B(const A&); };

struct S {
  A a;
  B b;

    [57 lines not shown]
DeltaFile
+522-0clang/test/CodeGenCXX/control-flow-in-stmt-expr.cpp
+96-3clang/lib/CodeGen/CodeGenFunction.h
+93-0clang/test/CodeGenCoroutines/coro-suspend-cleanups.cpp
+26-61clang/lib/CodeGen/CGExprAgg.cpp
+56-25clang/lib/CodeGen/CGDecl.cpp
+38-38clang/lib/CodeGen/CGCleanup.cpp
+831-1279 files not shown
+946-16515 files

LLVM/project df762a1clang/docs ReleaseNotes.rst, clang/lib/Sema SemaDeclCXX.cpp SemaInit.cpp

[SemaCXX] Recognise initializer_list injected-class-name types as initializer_lists (#90210)

This allows the implicitly-generated deduction guide for the copy
constructor to be recognised as an initializer-list constructor,
allowing CTAD for std::initializer_list
DeltaFile
+11-5clang/lib/Sema/SemaDeclCXX.cpp
+8-3clang/test/SemaCXX/cxx1z-class-template-argument-deduction.cpp
+2-0clang/docs/ReleaseNotes.rst
+0-2clang/lib/Sema/SemaInit.cpp
+21-104 files

LLVM/project ba09cc6mlir/lib/Dialect/Bufferization/Transforms OneShotAnalysis.cpp

[mlir][bufferization][NFC] More documentation for `runOneShotBufferize`
DeltaFile
+17-4mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp
+17-41 files

LLVM/project 93e69abllvm/test/CodeGen/X86 avgceils.ll avgfloors.ll

[X86] avg*.ll - add nounwind to silence cfi noise
DeltaFile
+24-214llvm/test/CodeGen/X86/avgceils.ll
+24-214llvm/test/CodeGen/X86/avgfloors.ll
+24-114llvm/test/CodeGen/X86/avgceilu.ll
+24-114llvm/test/CodeGen/X86/avgflooru.ll
+96-6564 files

LLVM/project 0edb5c3flang/lib/Optimizer/Transforms DebugTypeGenerator.cpp DebugTypeGenerator.h, flang/test/Transforms debug-fn-info.f90 debug-line-table-inc-file.fir

Revert "[flang] Improve debug info for functions." (#90444)

Reverts llvm/llvm-project#90083 due to a test suite failure:
https://lab.llvm.org/buildbot/#/builders/184/builds/11961

```
flang-new: ../llvm/mlir/lib/IR/Types.cpp:126: unsigned int mlir::Type::getIntOrFloatBitWidth() const: Assertion `isIntOrFloat() && "only integers and floats have a bitwidth"' failed.
```
DeltaFile
+0-63flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
+0-43flang/test/Transforms/debug-fn-info.f90
+0-40flang/lib/Optimizer/Transforms/DebugTypeGenerator.h
+10-26flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
+1-1flang/test/Transforms/debug-line-table-inc-file.fir
+0-1flang/lib/Optimizer/Transforms/CMakeLists.txt
+11-1746 files

LLVM/project bf57d2ellvm/lib/CodeGen/GlobalISel GISelKnownBits.cpp, llvm/unittests/CodeGen/GlobalISel KnownBitsTest.cpp

[AArch64][GlobalISel] Enable computeNumSignBits for G_XOR, G_AND, G_OR (#89896)

DeltaFile
+114-0llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
+14-0llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
+128-02 files

LLVM/project 75d52f5llvm/lib/Target/X86 X86ISelLowering.cpp

[X86] matchTruncateWithPACK - merge equivalent calls to getSizeInBits/getScalarSizeInBits. NFC.
DeltaFile
+6-5llvm/lib/Target/X86/X86ISelLowering.cpp
+6-51 files

LLVM/project d30f6bclibcxx/include/__string constexpr_c_functions.h, libcxx/include/__type_traits datasizeof.h

[libc++][NFC] Refactor __libcpp_datasizeof to be a variable template (#87769)

This decreases memory consumption and compiles times slightly and
removes a bit of boilderplate.
DeltaFile
+23-24libcxx/include/__type_traits/datasizeof.h
+11-11libcxx/test/libcxx/utilities/expected/expected.expected/no_unique_address.compile.pass.cpp
+9-9libcxx/test/libcxx/utilities/expected/expected.void/no_unique_address.compile.pass.cpp
+7-7libcxx/test/libcxx/type_traits/datasizeof.compile.pass.cpp
+1-1libcxx/include/__string/constexpr_c_functions.h
+1-1libcxx/test/std/containers/sequences/array/size_and_alignment.compile.pass.cpp
+52-536 files

LLVM/project bfc0317llvm/test/Analysis/CostModel/AArch64 sve-intrinsics.ll, llvm/test/Analysis/CostModel/RISCV splice.ll rvv-shuffle.ll

Move several vector intrinsics out of experimental namespace (#88748)

This patch is moving out following intrinsics:
* vector.interleave2/deinterleave2
* vector.reverse
* vector.splice

from the experimental namespace.

All these intrinsics exist in LLVM for more than a year now, and are
widely used, so should not be considered as experimental.
DeltaFile
+328-328llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
+206-206llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
+196-196llvm/test/Analysis/CostModel/RISCV/splice.ll
+146-146llvm/test/Transforms/InstCombine/vector-reverse.ll
+125-125llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
+94-94llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
+1,095-1,09596 files not shown
+2,642-2,544102 files

LLVM/project 16bd10allvm/test/CodeGen/AMDGPU rem_i128.ll, llvm/test/CodeGen/RISCV half-round-conv-sat.ll float-round-conv-sat.ll

Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more...

This reverts:
b3c55b707110084a9f50a16aade34c3be6fa18da - "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)"
(because it updates a test case that I don't know how to resolve the conflict for)
8e2f6495c0bac1dd6ee32b6a0d24152c9c343624 - "[DAGCombiner] Do not always fold FREEZE over BUILD_VECTOR (#85932)"
73472c5996716cda0dbb3ddb788304e0e7e6a323 - "[SelectionDAG] Treat CopyFromReg as freezing the value (#85932)"

Due to a test suite failure on AArch64 when compiling for SVE.
https://lab.llvm.org/buildbot/#/builders/197/builds/13955

clang: ../llvm/llvm/include/llvm/CodeGen/ValueTypes.h:307: MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed.
DeltaFile
+348-324llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
+264-269llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
+237-246llvm/test/CodeGen/AMDGPU/rem_i128.ll
+193-192llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
+174-162llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
+150-120llvm/test/CodeGen/RISCV/half-convert.ll
+1,366-1,31343 files not shown
+2,369-2,27549 files

LLVM/project f029da5flang/lib/Optimizer/Transforms DebugTypeGenerator.cpp DebugTypeGenerator.h, flang/test/Transforms debug-fn-info.f90 debug-line-table-inc-file.fir

[flang] Improve debug info for functions. (#90083)

This PR improves the debug information for functions in the following
ways:

1. Get line number information from FuncOp and remove hard-coded line
numbers.
2. Use proper type for function signature. I have a added a type
converter. Currently, it is very limited but will be enhanced with time.
3. Use de-constructed function name.
DeltaFile
+63-0flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
+43-0flang/test/Transforms/debug-fn-info.f90
+40-0flang/lib/Optimizer/Transforms/DebugTypeGenerator.h
+26-10flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
+1-1flang/test/Transforms/debug-line-table-inc-file.fir
+1-0flang/lib/Optimizer/Transforms/CMakeLists.txt
+174-116 files

LLVM/project a19a411llvm/test/tools/llvm-mca/X86/BtVer2 skip-unsupported-instructions-none-remain.s unsupported-instruction.s

[llvm-mca] Fix -skip-unsupported-instruction tests on Windows

Builder alerted me to the failing test, attempt #1 in the blind.
DeltaFile
+2-2llvm/test/tools/llvm-mca/X86/BtVer2/skip-unsupported-instructions-none-remain.s
+2-2llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s
+4-42 files

LLVM/project ab12bballvm/lib/CodeGen CodeGenPrepare.cpp, llvm/test/Transforms/CodeGenPrepare/ARM branch-on-zero.ll

 [CGP] Drop poison-generating flags after hoisting (#90382)

See the following case:
```
define i8 @src1(i8 %x) {
entry:
  %cmp = icmp eq i8 %x, -1
  br i1 %cmp, label %exit, label %if.then

if.then:
  %inc = add nuw nsw i8 %x, 1
  br label %exit

exit:
  %retval = phi i8 [ %inc, %if.then ], [ -1, %entry ]
  ret i8 %retval
}

define i8 @tgt1(i8 %x) {

    [18 lines not shown]
DeltaFile
+80-0llvm/test/Transforms/CodeGenPrepare/RISCV/convert-to-eqz.ll
+23-0llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll
+2-0llvm/lib/CodeGen/CodeGenPrepare.cpp
+105-03 files

LLVM/project 41942c8lldb/docs/resources lldbgdbremote.md

[lldb[Docs] Reduce title noise in packets doc (#90183)

This removes the "Brief" and "Description" subtitles and merges the text
of both so that the contents listing is clearer.
DeltaFile
+170-363lldb/docs/resources/lldbgdbremote.md
+170-3631 files

LLVM/project 5f79f75llvm/lib/MCA InstrBuilder.cpp, llvm/test/tools/llvm-mca/X86/BtVer2 unsupported-instruction.s skip-unsupported-instructions-none-remain.s

[llvm-mca] Add -skip-unsupported-instructions option (#89733)

Prior to this patch, if llvm-mca encountered an instruction which parses
but has no scheduler info, the instruction is always reported as
unsupported, and llvm-mca halts with an error.

However, it would still be useful to allow MCA to continue even in the
case of instructions lacking scheduling information. Obviously if
scheduling information is lacking, it's not possible to give an accurate
analysis for those instructions, and therefore a warning is emitted.

A user could previously have worked around such unsupported instructions
manually by deleting such instructions from the input, but this provides
them a way of doing this for bulk inputs where they may not have a list
of such unsupported instructions to drop up front.

Note that this behaviour of instructions with no scheduling information
under -skip-unsupported-instructions is analagous to current
instructions which fail to parse: those are currently dropped from the

    [12 lines not shown]
DeltaFile
+52-3llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s
+34-5llvm/tools/llvm-mca/llvm-mca.cpp
+15-0llvm/tools/llvm-mca/CodeRegion.h
+14-0llvm/test/tools/llvm-mca/X86/BtVer2/skip-unsupported-instructions-none-remain.s
+1-2llvm/lib/MCA/InstrBuilder.cpp
+116-105 files

LLVM/project e1622e1llvm/test/Transforms/InstCombine icmp-of-trunc-ext.ll

[InstCombine] Add tests for trunc nuw/nsw in icmp (NFC)
DeltaFile
+325-0llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll
+325-01 files

LLVM/project bd9fdceflang/lib/Lower ConvertVariable.cpp, flang/lib/Optimizer/CodeGen CodeGen.cpp

[flang] Use `isa/dyn_cast/cast/...` free functions. (#90432)

The corresponding member functions are deprecated.
DeltaFile
+10-10flang/lib/Optimizer/Dialect/FIRType.cpp
+4-4flang/lib/Optimizer/CodeGen/CodeGen.cpp
+3-5flang/lib/Optimizer/Dialect/FIROps.cpp
+2-4flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp
+2-2flang/lib/Lower/ConvertVariable.cpp
+21-255 files

LLVM/project 4a8f2f2llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/lib/Target/ARM ARMISelLowering.cpp

[Legalizer] Expand fmaximum and fminimum (#67301)

According to langref, llvm.maximum/minimum has -0.0 < +0.0 semantics and
propagates NaN.

Expand the nodes on targets not supporting the operation, by adding
extra check for NaN and using is_fpclass to check zero signs.
DeltaFile
+847-0llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll
+97-0llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll
+58-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+10-18llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
+5-9llvm/lib/Target/ARM/ARMISelLowering.cpp
+7-4llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+1,024-313 files not shown
+1,040-319 files

LLVM/project e2b8af7llvm/lib/Target/RISCV RISCVInsertVSETVLI.cpp

[RISCV] Don't use MachineInstr::isIdenticalTo in hasSameAVL (#90431)

MachineInstr::isIdenticalTo compares that the operands and flags are the
same IIUC, but I think we actually want to check that it's the same
MachineInstr * with respect to position in the block etc.
DeltaFile
+2-2llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+2-21 files

LLVM/project 66274ebclang/docs UsersManual.rst

Improve documented sampling profiler steps to best known methods (#88438)

1. Add `-fdebug-info-for-profiling -funique-internal-linkage-names`,
which improve the usefulness of debug info for profiling.

2. Recommend the use of `br_inst_retired.near_taken:uppp`, which
provides the most precise results on supporting hardware. Mention
`branches:u` as a more portable backup.

Both should portray execution counts better than the default event
(`cycles`) and have a better chance of working as an unprivileged user
due to the `:u` modifier.
DeltaFile
+55-16clang/docs/UsersManual.rst
+55-161 files

LLVM/project ec6c0a2llvm/test/CodeGen/LoongArch sextw-removal.ll

[LoongArch] Pre-commit tests for OptWInstrs. NFC
DeltaFile
+921-0llvm/test/CodeGen/LoongArch/sextw-removal.ll
+921-01 files