LLVM/project bf57d2e — llvm/lib/CodeGen/GlobalISel GISelKnownBits.cpp, llvm/unittests/CodeGen/GlobalISel KnownBitsTest.cpp

by chuongg3 via GitHub on ⎇
[AArch64][GlobalISel] Enable computeNumSignBits for G_XOR, G_AND, G_OR (#89896)
DeltaFile
+114-0llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
+14-0llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
+128-02 files

LLVM/project 75d52f5 — llvm/lib/Target/X86 X86ISelLowering.cpp

by Simon Pilgrim on ⎇
[X86] matchTruncateWithPACK - merge equivalent calls to getSizeInBits/getScalarSizeInBits. NFC.
DeltaFile
+6-5llvm/lib/Target/X86/X86ISelLowering.cpp
+6-51 files

LLVM/project d30f6bc — libcxx/include/__string constexpr_c_functions.h, libcxx/include/__type_traits datasizeof.h

by Nikolas Klauser via GitHub on ⎇
[libc++][NFC] Refactor __libcpp_datasizeof to be a variable template (#87769)

This decreases memory consumption and compiles times slightly and
removes a bit of boilderplate.
DeltaFile
+23-24libcxx/include/__type_traits/datasizeof.h
+11-11libcxx/test/libcxx/utilities/expected/expected.expected/no_unique_address.compile.pass.cpp
+9-9libcxx/test/libcxx/utilities/expected/expected.void/no_unique_address.compile.pass.cpp
+7-7libcxx/test/libcxx/type_traits/datasizeof.compile.pass.cpp
+1-1libcxx/include/__string/constexpr_c_functions.h
+1-1libcxx/test/std/containers/sequences/array/size_and_alignment.compile.pass.cpp
+52-536 files

LLVM/project bfc0317 — llvm/test/Analysis/CostModel/AArch64 sve-intrinsics.ll, llvm/test/Analysis/CostModel/RISCV splice.ll rvv-shuffle.ll

by Maciej Gabka via GitHub on ⎇
Move several vector intrinsics out of experimental namespace (#88748)

This patch is moving out following intrinsics:
* vector.interleave2/deinterleave2
* vector.reverse
* vector.splice

from the experimental namespace.

All these intrinsics exist in LLVM for more than a year now, and are
widely used, so should not be considered as experimental.
DeltaFile
+328-328llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
+206-206llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
+196-196llvm/test/Analysis/CostModel/RISCV/splice.ll
+146-146llvm/test/Transforms/InstCombine/vector-reverse.ll
+125-125llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
+94-94llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
+1,095-1,09596 files not shown
+2,642-2,544102 files

LLVM/project 16bd10a — llvm/test/CodeGen/AMDGPU rem_i128.ll, llvm/test/CodeGen/RISCV half-round-conv-sat.ll float-round-conv-sat.ll

by David Spickett on ⎇
Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more...

This reverts:
b3c55b707110084a9f50a16aade34c3be6fa18da - "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)"
(because it updates a test case that I don't know how to resolve the conflict for)
8e2f6495c0bac1dd6ee32b6a0d24152c9c343624 - "[DAGCombiner] Do not always fold FREEZE over BUILD_VECTOR (#85932)"
73472c5996716cda0dbb3ddb788304e0e7e6a323 - "[SelectionDAG] Treat CopyFromReg as freezing the value (#85932)"

Due to a test suite failure on AArch64 when compiling for SVE.
https://lab.llvm.org/buildbot/#/builders/197/builds/13955

clang: ../llvm/llvm/include/llvm/CodeGen/ValueTypes.h:307: MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed.
DeltaFile
+348-324llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
+264-269llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
+237-246llvm/test/CodeGen/AMDGPU/rem_i128.ll
+193-192llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
+174-162llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
+150-120llvm/test/CodeGen/RISCV/half-convert.ll
+1,366-1,31343 files not shown
+2,369-2,27549 files

LLVM/project f029da5 — flang/lib/Optimizer/Transforms DebugTypeGenerator.cpp DebugTypeGenerator.h, flang/test/Transforms debug-fn-info.f90 debug-line-table-inc-file.fir

by Abid Qadeer via GitHub on ⎇
[flang] Improve debug info for functions. (#90083)

This PR improves the debug information for functions in the following
ways:

1. Get line number information from FuncOp and remove hard-coded line
numbers.
2. Use proper type for function signature. I have a added a type
converter. Currently, it is very limited but will be enhanced with time.
3. Use de-constructed function name.
DeltaFile
+63-0flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
+43-0flang/test/Transforms/debug-fn-info.f90
+40-0flang/lib/Optimizer/Transforms/DebugTypeGenerator.h
+26-10flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
+1-1flang/test/Transforms/debug-line-table-inc-file.fir
+1-0flang/lib/Optimizer/Transforms/CMakeLists.txt
+174-116 files

LLVM/project a19a411 — llvm/test/tools/llvm-mca/X86/BtVer2 skip-unsupported-instructions-none-remain.s unsupported-instruction.s

by Peter Waller on ⎇
[llvm-mca] Fix -skip-unsupported-instruction tests on Windows

Builder alerted me to the failing test, attempt #1 in the blind.
DeltaFile
+2-2llvm/test/tools/llvm-mca/X86/BtVer2/skip-unsupported-instructions-none-remain.s
+2-2llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s
+4-42 files

LLVM/project ab12bba — llvm/lib/CodeGen CodeGenPrepare.cpp, llvm/test/Transforms/CodeGenPrepare/ARM branch-on-zero.ll

by Yingwei Zheng via GitHub on ⎇
 [CGP] Drop poison-generating flags after hoisting (#90382)

See the following case:
```
define i8 @src1(i8 %x) {
entry:
  %cmp = icmp eq i8 %x, -1
  br i1 %cmp, label %exit, label %if.then

if.then:
  %inc = add nuw nsw i8 %x, 1
  br label %exit

exit:
  %retval = phi i8 [ %inc, %if.then ], [ -1, %entry ]
  ret i8 %retval
}

define i8 @tgt1(i8 %x) {

    [18 lines not shown]
DeltaFile
+80-0llvm/test/Transforms/CodeGenPrepare/RISCV/convert-to-eqz.ll
+23-0llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll
+2-0llvm/lib/CodeGen/CodeGenPrepare.cpp
+105-03 files

LLVM/project 41942c8 — lldb/docs/resources lldbgdbremote.md

by David Spickett via GitHub on ⎇
[lldb[Docs] Reduce title noise in packets doc (#90183)

This removes the "Brief" and "Description" subtitles and merges the text
of both so that the contents listing is clearer.
DeltaFile
+170-363lldb/docs/resources/lldbgdbremote.md
+170-3631 files

LLVM/project 5f79f75 — llvm/lib/MCA InstrBuilder.cpp, llvm/test/tools/llvm-mca/X86/BtVer2 unsupported-instruction.s skip-unsupported-instructions-none-remain.s

by Peter Waller via GitHub on ⎇
[llvm-mca] Add -skip-unsupported-instructions option (#89733)

Prior to this patch, if llvm-mca encountered an instruction which parses
but has no scheduler info, the instruction is always reported as
unsupported, and llvm-mca halts with an error.

However, it would still be useful to allow MCA to continue even in the
case of instructions lacking scheduling information. Obviously if
scheduling information is lacking, it's not possible to give an accurate
analysis for those instructions, and therefore a warning is emitted.

A user could previously have worked around such unsupported instructions
manually by deleting such instructions from the input, but this provides
them a way of doing this for bulk inputs where they may not have a list
of such unsupported instructions to drop up front.

Note that this behaviour of instructions with no scheduling information
under -skip-unsupported-instructions is analagous to current
instructions which fail to parse: those are currently dropped from the

    [12 lines not shown]
DeltaFile
+52-3llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s
+34-5llvm/tools/llvm-mca/llvm-mca.cpp
+15-0llvm/tools/llvm-mca/CodeRegion.h
+14-0llvm/test/tools/llvm-mca/X86/BtVer2/skip-unsupported-instructions-none-remain.s
+1-2llvm/lib/MCA/InstrBuilder.cpp
+116-105 files

LLVM/project e1622e1 — llvm/test/Transforms/InstCombine icmp-of-trunc-ext.ll

by Nikita Popov on ⎇
[InstCombine] Add tests for trunc nuw/nsw in icmp (NFC)
DeltaFile
+325-0llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll
+325-01 files

LLVM/project bd9fdce — flang/lib/Lower ConvertVariable.cpp, flang/lib/Optimizer/CodeGen CodeGen.cpp

by Christian Sigg via GitHub on ⎇
[flang] Use `isa/dyn_cast/cast/...` free functions. (#90432)

The corresponding member functions are deprecated.
DeltaFile
+10-10flang/lib/Optimizer/Dialect/FIRType.cpp
+4-4flang/lib/Optimizer/CodeGen/CodeGen.cpp
+3-5flang/lib/Optimizer/Dialect/FIROps.cpp
+2-4flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp
+2-2flang/lib/Lower/ConvertVariable.cpp
+21-255 files

LLVM/project 4a8f2f2 — llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/lib/Target/ARM ARMISelLowering.cpp

by Qiu Chaofan via GitHub on ⎇
[Legalizer] Expand fmaximum and fminimum (#67301)

According to langref, llvm.maximum/minimum has -0.0 < +0.0 semantics and
propagates NaN.

Expand the nodes on targets not supporting the operation, by adding
extra check for NaN and using is_fpclass to check zero signs.
DeltaFile
+847-0llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll
+97-0llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll
+58-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+10-18llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
+5-9llvm/lib/Target/ARM/ARMISelLowering.cpp
+7-4llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+1,024-313 files not shown
+1,040-319 files

LLVM/project e2b8af7 — llvm/lib/Target/RISCV RISCVInsertVSETVLI.cpp

by Luke Lau via GitHub on ⎇
[RISCV] Don't use MachineInstr::isIdenticalTo in hasSameAVL (#90431)

MachineInstr::isIdenticalTo compares that the operands and flags are the
same IIUC, but I think we actually want to check that it's the same
MachineInstr * with respect to position in the block etc.
DeltaFile
+2-2llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+2-21 files

LLVM/project 66274eb — clang/docs UsersManual.rst

by Tim Creech via GitHub on ⎇
Improve documented sampling profiler steps to best known methods (#88438)

1. Add `-fdebug-info-for-profiling -funique-internal-linkage-names`,
which improve the usefulness of debug info for profiling.

2. Recommend the use of `br_inst_retired.near_taken:uppp`, which
provides the most precise results on supporting hardware. Mention
`branches:u` as a more portable backup.

Both should portray execution counts better than the default event
(`cycles`) and have a better chance of working as an unprivileged user
due to the `:u` modifier.
DeltaFile
+55-16clang/docs/UsersManual.rst
+55-161 files

LLVM/project ec6c0a2 — llvm/test/CodeGen/LoongArch sextw-removal.ll

by WANG Rui on ⎇
[LoongArch] Pre-commit tests for OptWInstrs. NFC
DeltaFile
+921-0llvm/test/CodeGen/LoongArch/sextw-removal.ll
+921-01 files

LLVM/project dc7834b — llvm/lib/ProfileData InstrProfWriter.cpp

by Kazu Hirata on ⎇
[ProfileData] Use static_assert instead of assert (NFC)

Identified with misc-static-assert.
DeltaFile
+2-2llvm/lib/ProfileData/InstrProfWriter.cpp
+2-21 files

LLVM/project b3c55b7 — llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/AMDGPU rem_i128.ll div_i128.ll

by Björn Pettersson via GitHub on ⎇
[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)

[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison

Handle SELECT_CC similarly as SETCC.

Handle these operations that only propagate poison/undef based on the
input operands:
  SADDSAT, UADDSAT, SSUBSAT, USUBSAT, MULHU, MULHS,
  SMIN, SMAX, UMIN, UMAX

These operations may create poison based on shift amount and exact
flag being violated:
  SRL, SRA

One goal here is to allow pushing freeze through these operations
when allowed, as well as letting analyses such as
isGuaranteedNotToBeUndefOrPoison to not break on such operations.


    [5 lines not shown]
DeltaFile
+246-237llvm/test/CodeGen/AMDGPU/rem_i128.ll
+197-201llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
+55-45llvm/test/CodeGen/AMDGPU/div_i128.ll
+38-42llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
+6-44llvm/test/CodeGen/X86/freeze-binary.ll
+15-1llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+557-5701 files not shown
+563-5707 files

LLVM/project 6cd6bde — llvm/test/Analysis/CostModel/RISCV arith-fp.ll arith-int.ll

by Shih-Po Hung via GitHub on ⎇
[RISCV] Remove -riscv-v-fixed-length-vector-lmul-max from arith tests (#89886)

This patch splits off from #89170 to clean up the tests.
DeltaFile
+31-31llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
+26-26llvm/test/Analysis/CostModel/RISCV/arith-int.ll
+57-572 files

LLVM/project 501cfd5 — llvm/lib/Target/X86 X86RegisterInfo.cpp, llvm/lib/Target/X86/MCTargetDesc X86BaseInfo.h

by Kazu Hirata on ⎇
[X86] Use static_asserts instead of assert (NFC)

Identified with misc-static-assert.
DeltaFile
+11-10llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
+5-4llvm/lib/Target/X86/X86RegisterInfo.cpp
+16-142 files

LLVM/project fa8fda8 — utils/bazel/llvm-project-overlay/mlir BUILD.bazel

by Adrian Kuegel on ⎇
[mlir][Bazel] Add missing dependency after 145176dc0c93566ce4aef721044d49ab8ba50f87
DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-01 files

LLVM/project b7457cc — bolt/docs BAT.md, bolt/include/bolt/Utils NameResolver.h

by Amir Ayupov on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.5

[skip ci]
DeltaFile
+118-27bolt/lib/Rewrite/RewriteInstance.cpp
+42-44bolt/lib/Profile/BoltAddressTranslation.cpp
+44-10bolt/test/X86/fragment-lite.s
+15-2bolt/include/bolt/Utils/NameResolver.h
+13-2bolt/test/X86/cdsplit-symbol-names.s
+4-5bolt/docs/BAT.md
+236-904 files not shown
+251-9410 files

LLVM/project 72bf9f9 — bolt/docs BAT.md, bolt/include/bolt/Utils NameResolver.h

by Amir Ayupov on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.5
DeltaFile
+123-27bolt/lib/Rewrite/RewriteInstance.cpp
+42-44bolt/lib/Profile/BoltAddressTranslation.cpp
+44-10bolt/test/X86/fragment-lite.s
+15-2bolt/include/bolt/Utils/NameResolver.h
+13-2bolt/test/X86/cdsplit-symbol-names.s
+4-5bolt/docs/BAT.md
+241-904 files not shown
+256-9410 files

LLVM/project caa794b — llvm/lib/Target/RISCV/MCTargetDesc RISCVBaseInfo.h

by wangpc via Wang Pengcheng on ⎇
Fix typo

Created using spr 1.3.6-beta.1
DeltaFile
+3-3llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+3-31 files

LLVM/project 5800052 — bolt/test/X86 cdsplit-symbol-names.s

by Amir Ayupov on ⎇
Split cdsplit-symbol-names.s to avoid symbol already defined error

Created using spr 1.3.5
DeltaFile
+7-2bolt/test/X86/cdsplit-symbol-names.s
+7-21 files

LLVM/project 4c7fd2b —

by Amir Ayupov on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5

[skip ci]
DeltaFile
+0-00 files

LLVM/project 3785d74 — flang/lib/Optimizer/CodeGen FIROpPatterns.cpp, flang/test/Driver mlir-debug-pass-pipeline.f90 mlir-pass-pipeline.f90

by Kareem Ergawy via GitHub on ⎇
[flang][OpenMP][LLVMIR] Support CFG and LLVM IR conversion for `omp.p… (#90164)

…rivate`

Adds support for CFG conversion and conversion to LLVM IR for
`omp.private` ops. This bridges a gap between FIR and LLVM to provide
more support for lowering `omp.private` ops for things like
allocatables.
DeltaFile
+54-0flang/test/Lower/OpenMP/cfg-conversion-omp.private.f90
+10-4flang/test/Fir/basic-program.fir
+9-3flang/test/Driver/mlir-debug-pass-pipeline.f90
+9-3flang/test/Driver/mlir-pass-pipeline.f90
+6-2flang/test/Driver/bbc-mlir-pass-pipeline.f90
+3-0flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp
+91-121 files not shown
+92-137 files

LLVM/project 53cda4c — llvm/lib/Transforms/Utils BasicBlockUtils.cpp

by Kazu Hirata on ⎇
[Transforms] Use LLVMContext::MD_loop (NFC)
DeltaFile
+3-3llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
+3-31 files

LLVM/project 42bc4f6 — llvm/lib/Target/X86 X86LowerTileCopy.cpp, llvm/test/CodeGen/X86/AMX amx-lower-tile-copy.ll

by Phoebe Wang on ⎇
Reland "[X86] X86LowerTileCopy: Find dead register to use to prevent save-reload of tile register (#83628)"

Fixes compile time regression in previous commit.
DeltaFile
+54-19llvm/lib/Target/X86/X86LowerTileCopy.cpp
+0-10llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll
+54-292 files

LLVM/project 99ea7b7 — bolt/docs BAT.md, bolt/include/bolt/Utils NameResolver.h

by Amir Ayupov on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.5
DeltaFile
+118-27bolt/lib/Rewrite/RewriteInstance.cpp
+42-44bolt/lib/Profile/BoltAddressTranslation.cpp
+44-10bolt/test/X86/fragment-lite.s
+15-2bolt/include/bolt/Utils/NameResolver.h
+13-2bolt/test/X86/cdsplit-symbol-names.s
+4-5bolt/docs/BAT.md
+236-904 files not shown
+251-9410 files