.ci/metrics/metrics.py

		@@ -130,34 +130,6 @@ def get_per_workflow_metrics(
		workflow_jobs = workflow_run.jobs()
		if workflow_jobs.totalCount == 0:
		continue
		- if workflow_jobs.totalCount > 1:
		- raise ValueError(
		- f"Encountered an unexpected number of jobs: {workflow_jobs.totalCount}"
		- )
		-
		- created_at = workflow_jobs[0].created_at
		- started_at = workflow_jobs[0].started_at
		- completed_at = workflow_jobs[0].completed_at
		-
		- job_result = int(workflow_jobs[0].conclusion == "success")
		- if job_result:
		- # We still might want to mark the job as a failure if one of the steps
		- # failed. This is required due to use setting continue-on-error in
		- # the premerge pipeline to prevent sending emails while we are
		- # testing the infrastructure.
		- # TODO(boomanaiden154): Remove this once the premerge pipeline is no
		- # longer in a testing state and we can directly assert the workflow
		- # result.
		- for step in workflow_jobs[0].steps:
		- if step.conclusion != "success":
		- job_result = 0
		- break
		-
		- queue_time = started_at - created_at
		- run_time = completed_at - started_at
		-
		- if run_time.seconds == 0:
		- continue
		if (
		workflows_to_track[workflow_run.name] is None
		@@ -170,20 +142,45 @@ def get_per_workflow_metrics(
		):
		break
		- # The timestamp associated with the event is expected by Grafana to be
		- # in nanoseconds.
		- created_at_ns = int(created_at.timestamp()) * 10**9
		-
		- workflow_metrics.append(
		- JobMetrics(
		- workflow_run.name,
		- queue_time.seconds,
		- run_time.seconds,
		- job_result,
		- created_at_ns,
		- workflow_run.id,
		+ for workflow_job in workflow_jobs:
		+ created_at = workflow_job.created_at
		+ started_at = workflow_job.started_at
		+ completed_at = workflow_job.completed_at
		+
		+ job_result = int(workflow_job.conclusion == "success")
		+ if job_result:
		+ # We still might want to mark the job as a failure if one of the steps
		+ # failed. This is required due to use setting continue-on-error in
		+ # the premerge pipeline to prevent sending emails while we are
		+ # testing the infrastructure.
		+ # TODO(boomanaiden154): Remove this once the premerge pipeline is no
		+ # longer in a testing state and we can directly assert the workflow
		+ # result.
		+ for step in workflow_job.steps:
		+ if step.conclusion != "success":
		+ job_result = 0
		+ break
		+
		+ queue_time = started_at - created_at
		+ run_time = completed_at - started_at
		+
		+ if run_time.seconds == 0:
		+ continue
		+
		+ # The timestamp associated with the event is expected by Grafana to be
		+ # in nanoseconds.
		+ created_at_ns = int(created_at.timestamp()) * 10**9
		+
		+ workflow_metrics.append(
		+ JobMetrics(
		+ workflow_run.name + "-" + workflow_job.name,
		+ queue_time.seconds,
		+ run_time.seconds,
		+ job_result,
		+ created_at_ns,
		+ workflow_run.id,
		+ )
		)
		- )
		return workflow_metrics

.github/workflows/libcxx-build-and-test.yaml

		@@ -48,8 +48,8 @@ jobs:
		'generic-cxx26',
		'generic-modules'
		]
		- cc: [ 'clang-19' ]
		- cxx: [ 'clang++-19' ]
		+ cc: [ 'clang-20' ]
		+ cxx: [ 'clang++-20' ]
		include:
		- config: 'generic-gcc'
		cc: 'gcc-14'
		@@ -88,18 +88,18 @@ jobs:
		'generic-cxx20',
		'generic-cxx23'
		]
		- cc: [ 'clang-19' ]
		- cxx: [ 'clang++-19' ]
		+ cc: [ 'clang-20' ]
		+ cxx: [ 'clang++-20' ]
		include:
		- config: 'generic-gcc-cxx11'
		cc: 'gcc-14'
		cxx: 'g++-14'
		- config: 'generic-cxx23'
		- cc: 'clang-17'
		- cxx: 'clang++-17'
		- - config: 'generic-cxx26'
		cc: 'clang-18'
		cxx: 'clang++-18'
		+ - config: 'generic-cxx26'
		+ cc: 'clang-19'
		+ cxx: 'clang++-19'
		steps:
		- uses: actions/checkout@v4
		- name: ${{ matrix.config }}
		@@ -169,8 +169,8 @@ jobs:
		- name: ${{ matrix.config }}
		run: libcxx/utils/ci/run-buildbot ${{ matrix.config }}
		env:
		- CC: clang-19
		- CXX: clang++-19
		+ CC: clang-20
		+ CXX: clang++-20
		- uses: actions/upload-artifact@26f96dfa697d77e81fd5907df203aa23a56210a8 # v4.3.0
		if: always()
		with:

.github/workflows/release-binaries.yml

		@@ -226,14 +226,6 @@ jobs:
		id: setup-stage
		uses: ./workflows-main/.github/workflows/release-binaries-setup-stage
		- - name: Setup sccache
		- uses: hendrikmuhs/ccache-action@ca3acd2731eef11f1572ccb126356c2f9298d35e # v1.2.9
		- with:
		- # Default to 2G to workaround: https://github.com/hendrikmuhs/ccache-action/issues/174
		- max-size: 2G
		- key: ${{ needs.prepare.outputs.ccache }}-${{ runner.os }}-${{ runner.arch }}-release
		- variant: ${{ needs.prepare.outputs.ccache }}
		-
		- name: Configure
		id: build
		shell: bash
		@@ -246,9 +238,8 @@ jobs:
		${{ needs.prepare.outputs.target-cmake-flags }} \
		-C clang/cmake/caches/Release.cmake \
		-DBOOTSTRAP_LLVM_PARALLEL_LINK_JOBS=1 \
		- -DBOOTSTRAP_CPACK_PACKAGE_FILE_NAME="${{ needs.prepare.outputs.release-binary-basename }}" \
		- -DCMAKE_C_COMPILER_LAUNCHER=$CCACHE_BIN \
		- -DCMAKE_CXX_COMPILER_LAUNCHER=$CCACHE_BIN
		+ -DBOOTSTRAP_CPACK_PACKAGE_FILE_NAME="${{ needs.prepare.outputs.release-binary-basename }}"
		+
		- name: Build
		shell: bash
		run: |

bolt/lib/Core/BinaryFunction.cpp

		@@ -795,7 +795,6 @@ BinaryFunction::processIndirectBranch(MCInst &Instruction, unsigned Size,
		auto Begin = Instructions.begin();
		if (BC.isAArch64()) {
		- PreserveNops = BC.HasRelocations;
		// Start at the last label as an approximation of the current basic block.
		// This is a heuristic, since the full set of labels have yet to be
		// determined
		@@ -2300,6 +2299,10 @@ Error BinaryFunction::buildCFG(MCPlusBuilder::AllocatorIdTy AllocatorId) {
		BC.errs() << "BOLT-WARNING: failed to post-process indirect branches for "
		<< *this << '\n';
		}
		+
		+ if (BC.isAArch64())
		+ PreserveNops = BC.HasRelocations;
		+
		// In relocation mode we want to keep processing the function but avoid
		// optimizing it.
		setSimple(false);

bolt/test/AArch64/pad-before-funcs.s

		@@ -15,7 +15,7 @@
		# RUN: llvm-bolt %t.exe -o %t.bolt.4.4 --pad-funcs-before=_start:4 --pad-funcs=_start:4
		# RUN: llvm-bolt %t.exe -o %t.bolt.4.8 --pad-funcs-before=_start:4 --pad-funcs=_start:8
		-# RUN: not llvm-bolt %t.exe -o %t.bolt.8 --pad-funcs-before=_start:1 2>&1 | FileCheck --check-prefix=CHECK-BAD-ALIGN %s
		+# RUN: not llvm-bolt %t.exe -o %t.bolt.1 --pad-funcs-before=_start:1 2>&1 | FileCheck --check-prefix=CHECK-BAD-ALIGN %s
		# CHECK-BAD-ALIGN: user-requested 1 padding bytes before function _start(*2) is not a multiple of the minimum function alignment (4).

bolt/test/AArch64/remove-nops.s

		@@ -0,0 +1,28 @@
		+## Verify that llvm-bolt removes nop instructions from functions with indirect
		+## branches that have defined control flow.
		+
		+# REQUIRES: system-linux
		+
		+# RUN: llvm-mc -filetype=obj -triple aarch64-unknown-unknown %s -o %t.o
		+# RUN: %clang %cflags --target=aarch64-unknown-linux %t.o -o %t.exe -Wl,-q
		+# RUN: llvm-bolt %t.exe -o %t.bolt --print-normalized 2>&1 | FileCheck %s
		+# RUN: llvm-objdump -d --disassemble-symbols=_start %t.bolt \
		+# RUN: | FileCheck %s --check-prefix=CHECK-OBJDUMP
		+
		+# CHECK-OBJDUMP-LABEL: _start
		+# CHECK-OBJDUMP-NOT: nop
		+
		+ .section .text
		+ .align 4
		+ .globl _start
		+ .type _start, %function
		+_start:
		+# CHECK-LABEL: Binary Function "_start"
		+ nop
		+# CHECK-NOT: nop
		+ br x0
		+# CHECK: br x0 # TAILCALL
		+.size _start, .-_start
		+
		+## Force relocation mode.
		+ .reloc 0, R_AARCH64_NONE

clang-tools-extra/clangd/Diagnostics.cpp

		@@ -577,7 +577,17 @@ std::vector<Diag> StoreDiags::take(const clang::tidy::ClangTidyContext *Tidy) {
		for (auto &Diag : Output) {
		if (const char *ClangDiag = getDiagnosticCode(Diag.ID)) {
		// Warnings controlled by -Wfoo are better recognized by that name.
		- StringRef Warning = DiagnosticIDs::getWarningOptionForDiag(Diag.ID);
		+ StringRef Warning = [&] {
		+ if (OrigSrcMgr) {
		+ return OrigSrcMgr->getDiagnostics()
		+ .getDiagnosticIDs()
		+ ->getWarningOptionForDiag(Diag.ID);
		+ }
		+ if (!DiagnosticIDs::IsCustomDiag(Diag.ID))
		+ return DiagnosticIDs{}.getWarningOptionForDiag(Diag.ID);
		+ return StringRef{};
		+ }();
		+
		if (!Warning.empty()) {
		Diag.Name = ("-W" + Warning).str();
		} else {
		@@ -894,20 +904,23 @@ void StoreDiags::flushLastDiag() {
		Output.push_back(std::move(*LastDiag));
		}
		-bool isBuiltinDiagnosticSuppressed(unsigned ID,
		- const llvm::StringSet<> &Suppress,
		- const LangOptions &LangOpts) {
		+bool isDiagnosticSuppressed(const clang::Diagnostic &Diag,
		+ const llvm::StringSet<> &Suppress,
		+ const LangOptions &LangOpts) {
		// Don't complain about header-only stuff in mainfiles if it's a header.
		// FIXME: would be cleaner to suppress in clang, once we decide whether the
		// behavior should be to silently-ignore or respect the pragma.
		- if (ID == diag::pp_pragma_sysheader_in_main_file && LangOpts.IsHeaderFile)
		+ if (Diag.getID() == diag::pp_pragma_sysheader_in_main_file &&
		+ LangOpts.IsHeaderFile)
		return true;
		- if (const char *CodePtr = getDiagnosticCode(ID)) {
		+ if (const char *CodePtr = getDiagnosticCode(Diag.getID())) {
		if (Suppress.contains(normalizeSuppressedCode(CodePtr)))
		return true;
		}
		- StringRef Warning = DiagnosticIDs::getWarningOptionForDiag(ID);
		+ StringRef Warning =
		+ Diag.getDiags()->getDiagnosticIDs()->getWarningOptionForDiag(
		+ Diag.getID());
		if (!Warning.empty() && Suppress.contains(Warning))
		return true;
		return false;

clang-tools-extra/clangd/Diagnostics.h

		@@ -181,11 +181,11 @@ private:
		};
		/// Determine whether a (non-clang-tidy) diagnostic is suppressed by config.
		-bool isBuiltinDiagnosticSuppressed(unsigned ID,
		- const llvm::StringSet<> &Suppressed,
		- const LangOptions &);
		+bool isDiagnosticSuppressed(const clang::Diagnostic &Diag,
		+ const llvm::StringSet<> &Suppressed,
		+ const LangOptions &);
		/// Take a user-specified diagnostic code, and convert it to a normalized form
		-/// stored in the config and consumed by isBuiltinDiagnosticsSuppressed.
		+/// stored in the config and consumed by isDiagnosticsSuppressed.
		///
		/// (This strips err_ and -W prefix so we can match with or without them.)
		llvm::StringRef normalizeSuppressedCode(llvm::StringRef);

clang-tools-extra/clangd/ParsedAST.cpp

		@@ -342,7 +342,7 @@ void applyWarningOptions(llvm::ArrayRef<std::string> ExtraArgs,
		if (Enable) {
		if (Diags.getDiagnosticLevel(ID, SourceLocation()) <
		DiagnosticsEngine::Warning) {
		- auto Group = DiagnosticIDs::getGroupForDiag(ID);
		+ auto Group = Diags.getDiagnosticIDs()->getGroupForDiag(ID);
		if (!Group || !EnabledGroups(*Group))
		continue;
		Diags.setSeverity(ID, diag::Severity::Warning, SourceLocation());
		@@ -585,8 +585,8 @@ ParsedAST::build(llvm::StringRef Filename, const ParseInputs &Inputs,
		ASTDiags.setLevelAdjuster([&](DiagnosticsEngine::Level DiagLevel,
		const clang::Diagnostic &Info) {
		if (Cfg.Diagnostics.SuppressAll ||
		- isBuiltinDiagnosticSuppressed(Info.getID(), Cfg.Diagnostics.Suppress,
		- Clang->getLangOpts()))
		+ isDiagnosticSuppressed(Info, Cfg.Diagnostics.Suppress,
		+ Clang->getLangOpts()))
		return DiagnosticsEngine::Ignored;
		auto It = OverriddenSeverity.find(Info.getID());

clang-tools-extra/clangd/Preamble.cpp

		@@ -622,8 +622,8 @@ buildPreamble(PathRef FileName, CompilerInvocation CI,
		PreambleDiagnostics.setLevelAdjuster([&](DiagnosticsEngine::Level DiagLevel,
		const clang::Diagnostic &Info) {
		if (Cfg.Diagnostics.SuppressAll ||
		- isBuiltinDiagnosticSuppressed(Info.getID(), Cfg.Diagnostics.Suppress,
		- CI.getLangOpts()))
		+ isDiagnosticSuppressed(Info, Cfg.Diagnostics.Suppress,
		+ CI.getLangOpts()))
		return DiagnosticsEngine::Ignored;
		switch (Info.getID()) {
		case diag::warn_no_newline_eof:

clang-tools-extra/clangd/unittests/ConfigCompileTests.cpp

		@@ -298,20 +298,41 @@ TEST_F(ConfigCompileTests, DiagnosticSuppression) {
		"unreachable-code", "unused-variable",
		"typecheck_bool_condition",
		"unexpected_friend", "warn_alloca"));
		- EXPECT_TRUE(isBuiltinDiagnosticSuppressed(
		- diag::warn_unreachable, Conf.Diagnostics.Suppress, LangOptions()));
		+ clang::DiagnosticsEngine DiagEngine(new DiagnosticIDs, nullptr,
		+ new clang::IgnoringDiagConsumer);
		+
		+ using Diag = clang::Diagnostic;
		+ {
		+ auto D = DiagEngine.Report(diag::warn_unreachable);
		+ EXPECT_TRUE(isDiagnosticSuppressed(
		+ Diag{&DiagEngine, D}, Conf.Diagnostics.Suppress, LangOptions()));
		+ }
		// Subcategory not respected/suppressed.
		- EXPECT_FALSE(isBuiltinDiagnosticSuppressed(
		- diag::warn_unreachable_break, Conf.Diagnostics.Suppress, LangOptions()));
		- EXPECT_TRUE(isBuiltinDiagnosticSuppressed(
		- diag::warn_unused_variable, Conf.Diagnostics.Suppress, LangOptions()));
		- EXPECT_TRUE(isBuiltinDiagnosticSuppressed(diag::err_typecheck_bool_condition,
		- Conf.Diagnostics.Suppress,
		- LangOptions()));
		- EXPECT_TRUE(isBuiltinDiagnosticSuppressed(
		- diag::err_unexpected_friend, Conf.Diagnostics.Suppress, LangOptions()));
		- EXPECT_TRUE(isBuiltinDiagnosticSuppressed(
		- diag::warn_alloca, Conf.Diagnostics.Suppress, LangOptions()));
		+ {
		+ auto D = DiagEngine.Report(diag::warn_unreachable_break);
		+ EXPECT_FALSE(isDiagnosticSuppressed(
		+ Diag{&DiagEngine, D}, Conf.Diagnostics.Suppress, LangOptions()));
		+ }
		+ {
		+ auto D = DiagEngine.Report(diag::warn_unused_variable);
		+ EXPECT_TRUE(isDiagnosticSuppressed(
		+ Diag{&DiagEngine, D}, Conf.Diagnostics.Suppress, LangOptions()));
		+ }
		+ {
		+ auto D = DiagEngine.Report(diag::err_typecheck_bool_condition);
		+ EXPECT_TRUE(isDiagnosticSuppressed(
		+ Diag{&DiagEngine, D}, Conf.Diagnostics.Suppress, LangOptions()));
		+ }
		+ {
		+ auto D = DiagEngine.Report(diag::err_unexpected_friend);
		+ EXPECT_TRUE(isDiagnosticSuppressed(
		+ Diag{&DiagEngine, D}, Conf.Diagnostics.Suppress, LangOptions()));
		+ }
		+ {
		+ auto D = DiagEngine.Report(diag::warn_alloca);
		+ EXPECT_TRUE(isDiagnosticSuppressed(
		+ Diag{&DiagEngine, D}, Conf.Diagnostics.Suppress, LangOptions()));
		+ }
		Frag.Diagnostics.Suppress.emplace_back("*");
		EXPECT_TRUE(compileAndApply());

clang-tools-extra/docs/ReleaseNotes.rst

		@@ -43,21 +43,12 @@ infrastructure are described first, followed by tool-specific sections.
		Major New Features
		------------------
		-- The ``clang-pseudo`` tool is incomplete and does not have active maintainers,
		- so it has been removed. See
		- `the RFC <https://discourse.llvm.org/t/removing-pseudo-parser/71131/>`_ for
		- more details.
		-
		-...
		-
		Improvements to clangd
		----------------------
		Inlay hints
		^^^^^^^^^^^
		-- Added `DefaultArguments` Inlay Hints option.
		-
		Diagnostics
		^^^^^^^^^^^
		@@ -73,16 +64,9 @@ Hover
		Code completion
		^^^^^^^^^^^^^^^
		-- Added completion for C++20 keywords.
		-
		Code actions
		^^^^^^^^^^^^
		-- Added `Swap operands` tweak for certain binary operators.
		-
		-- Improved the extract-to-function code action to allow extracting statements
		- with overloaded operators like ``<<`` of ``std::ostream``.
		-
		Signature help
		^^^^^^^^^^^^^^
		@@ -95,326 +79,30 @@ Objective-C
		Miscellaneous
		^^^^^^^^^^^^^
		-- The DefineOutline tweak now handles member functions of class templates.
		-
		Improvements to clang-doc
		-------------------------
		Improvements to clang-query
		---------------------------
		-- Added `set enable-profile true/false` command for basic matcher profiling.
		-
		Improvements to clang-tidy
		--------------------------
		-- Improved :program:`clang-tidy-diff.py` script. Add the `-only-check-in-db`
		- option to exclude files not present in the compilation database, avoiding
		- false-negative results.
		-
		-- Improved :program:`run-clang-tidy.py` script. Fixed minor shutdown noise
		- happening on certain platforms when interrupting the script.
		-
		-- Improved :program:`clang-tidy`:
		-
		- - add support for `--verify-config` flag to check the configuration options of
		- the `Clang Static Analyzer Checks <https://clang.llvm.org/docs/analyzer/checkers.html>`_.
		- - accept parameters file in command line.
		- - fix incorrect configuration file path resolving when file paths contain ``..``.
		- - remove global options for most of checks. All options are changed to local
		- options except `IncludeStyle`, `StrictMode` and `IgnoreMacros`. Global scoped
		- `StrictMode` and `IgnoreMacros` are deprecated and will be removed in further
		- releases.
		-
		-.. csv-table::
		- :header: "Check", "Options removed from global option"
		-
		- :doc:`bugprone-reserved-identifier <clang-tidy/checks/bugprone/reserved-identifier>`, AggressiveDependentMemberLookup
		- :doc:`bugprone-unchecked-optional-access <clang-tidy/checks/bugprone/unchecked-optional-access>`, IgnoreSmartPointerDereference
		- :doc:`cppcoreguidelines-pro-type-member-init <clang-tidy/checks/cppcoreguidelines/pro-type-member-init>`, UseAssignment
		- :doc:`cppcoreguidelines-rvalue-reference-param-not-moved <clang-tidy/checks/cppcoreguidelines/rvalue-reference-param-not-moved>`, AllowPartialMove; IgnoreUnnamedParams; IgnoreNonDeducedTemplateTypes
		- :doc:`misc-include-cleaner <clang-tidy/checks/misc/include-cleaner>`, IgnoreHeaders; DeduplicateFindings
		- :doc:`performance-inefficient-vector-operation <clang-tidy/checks/performance/inefficient-vector-operation>`, EnableProto
		- :doc:`readability-identifier-naming <clang-tidy/checks/readability/identifier-naming>`, AggressiveDependentMemberLookup
		- :doc:`readability-inconsistent-declaration-parameter-name <clang-tidy/checks/readability/inconsistent-declaration-parameter-name>`, Strict
		- :doc:`readability-redundant-access-specifiers <clang-tidy/checks/readability/redundant-access-specifiers>`, CheckFirstDeclaration
		- :doc:`readability-redundant-casting <clang-tidy/checks/readability/redundant-casting>`, IgnoreTypeAliases
		-
		New checks
		^^^^^^^^^^
		-- New :doc:`bugprone-bitwise-pointer-cast
		- <clang-tidy/checks/bugprone/bitwise-pointer-cast>` check.
		-
		- Warns about code that tries to cast between pointers by means of
		- ``std::bit_cast`` or ``memcpy``.
		-
		-- New :doc:`bugprone-incorrect-enable-shared-from-this
		- <clang-tidy/checks/bugprone/incorrect-enable-shared-from-this>` check.
		-
		- Detect classes or structs that do not publicly inherit from
		- ``std::enable_shared_from_this``, because unintended behavior will
		- otherwise occur when calling ``shared_from_this``.
		-
		-- New :doc:`bugprone-nondeterministic-pointer-iteration-order
		- <clang-tidy/checks/bugprone/nondeterministic-pointer-iteration-order>`
		- check.
		-
		- Finds nondeterministic usages of pointers in unordered containers.
		-
		-- New :doc:`bugprone-tagged-union-member-count
		- <clang-tidy/checks/bugprone/tagged-union-member-count>` check.
		-
		- Gives warnings for tagged unions, where the number of tags is
		- different from the number of data members inside the union.
		-
		-- New :doc:`modernize-use-integer-sign-comparison
		- <clang-tidy/checks/modernize/use-integer-sign-comparison>` check.
		-
		- Replace comparisons between signed and unsigned integers with their safe
		- C++20 ``std::cmp_*`` alternative, if available.
		-
		-- New :doc:`portability-template-virtual-member-function
		- <clang-tidy/checks/portability/template-virtual-member-function>` check.
		-
		- Finds cases when an uninstantiated virtual member function in a template class
		- causes cross-compiler incompatibility.
		-
		New check aliases
		^^^^^^^^^^^^^^^^^
		-- New alias :doc:`cert-arr39-c <clang-tidy/checks/cert/arr39-c>` to
		- :doc:`bugprone-sizeof-expression
		- <clang-tidy/checks/bugprone/sizeof-expression>` was added.
		-
		Changes in existing checks
		^^^^^^^^^^^^^^^^^^^^^^^^^^
		-- Improved :doc:`altera-id-dependent-backward-branch
		- <clang-tidy/checks/altera/id-dependent-backward-branch>` check by fixing
		- crashes from invalid code.
		-
		-- Improved :doc:`bugprone-branch-clone
		- <clang-tidy/checks/bugprone/branch-clone>` check to improve detection of
		- branch clones by now detecting duplicate inner and outer if statements.
		-
		-- Improved :doc:`bugprone-casting-through-void
		- <clang-tidy/checks/bugprone/casting-through-void>` check to suggest replacing
		- the offending code with ``reinterpret_cast``, to more clearly express intent.
		-
		-- Improved :doc:`bugprone-dangling-handle
		- <clang-tidy/checks/bugprone/dangling-handle>` check to treat ``std::span`` as a
		- handle class.
		-
		-- Improved :doc:`bugprone-exception-escape
		- <clang-tidy/checks/bugprone/exception-escape>` by fixing false positives
		- when a consteval function with throw statements.
		-
		-- Improved :doc:`bugprone-forwarding-reference-overload
		- <clang-tidy/checks/bugprone/forwarding-reference-overload>` check by fixing
		- a crash when determining if an ``enable_if[_t]`` was found.
		-
		-- Improve :doc:`bugprone-narrowing-conversions
		- <clang-tidy/checks/bugprone/narrowing-conversions>` to avoid incorrect check
		- results when floating point type is not ``float``, ``double`` and
		- ``long double``.
		-
		-- Improved :doc:`bugprone-optional-value-conversion
		- <clang-tidy/checks/bugprone/optional-value-conversion>` to support detecting
		- conversion directly by ``std::make_unique`` and ``std::make_shared``.
		-
		-- Improved :doc:`bugprone-posix-return
		- <clang-tidy/checks/bugprone/posix-return>` check to support integer literals
		- as LHS and posix call as RHS of comparison.
		-
		-- Improved :doc:`bugprone-return-const-ref-from-parameter
		- <clang-tidy/checks/bugprone/return-const-ref-from-parameter>` check to
		- diagnose potential dangling references when returning a ``const &`` parameter
		- by using the conditional operator ``cond ? var1 : var2`` and fixing false
		- positives for functions which contain lambda and ignore parameters
		- with ``[[clang::lifetimebound]]`` attribute.
		-
		-- Improved :doc:`bugprone-sizeof-expression
		- <clang-tidy/checks/bugprone/sizeof-expression>` check to find suspicious
		- usages of ``sizeof()``, ``alignof()``, and ``offsetof()`` when adding or
		- subtracting from a pointer directly or when used to scale a numeric value and
		- fix false positive when sizeof expression with template types.
		-
		-- Improved :doc:`bugprone-throw-keyword-missing
		- <clang-tidy/checks/bugprone/throw-keyword-missing>` by fixing a false positive
		- when using non-static member initializers and a constructor.
		-
		-- Improved :doc:`bugprone-unchecked-optional-access
		- <clang-tidy/checks/bugprone/unchecked-optional-access>` to support
		- ``bsl::optional`` and ``bdlb::NullableValue`` from
		- <https://github.com/bloomberg/bde>_.
		-
		-- Improved :doc:`bugprone-unhandled-self-assignment
		- <clang-tidy/checks/bugprone/unhandled-self-assignment>` check by fixing smart
		- pointer check against std::unique_ptr type.
		-
		-- Improved :doc:`bugprone-unsafe-functions
		- <clang-tidy/checks/bugprone/unsafe-functions>` check to allow specifying
		- additional functions to match.
		-
		-- Improved :doc:`bugprone-unused-local-non-trivial-variable
		- <clang-tidy/checks/bugprone/unused-local-non-trivial-variable>` check to avoid
		- false positives when using name-independent variables after C++26.
		-
		-- Improved :doc:`bugprone-use-after-move
		- <clang-tidy/checks/bugprone/use-after-move>` to avoid triggering on
		- ``reset()`` calls on moved-from ``std::optional`` and ``std::any`` objects,
		- similarly to smart pointers.
		-
		-- Improved :doc:`cert-flp30-c <clang-tidy/checks/cert/flp30-c>` check to
		- fix false positive that floating point variable is only used in increment
		- expression.
		-
		-- Improved :doc:`cppcoreguidelines-avoid-const-or-ref-data-members
		- <clang-tidy/checks/cppcoreguidelines/avoid-const-or-ref-data-members>` check to
		- avoid false positives when detecting a templated class with inheritance.
		-
		-- Improved :doc:`cppcoreguidelines-init-variables
		- <clang-tidy/checks/cppcoreguidelines/init-variables>` check by fixing the
		- insertion location for function pointers.
		-
		-- Improved :doc:`cppcoreguidelines-prefer-member-initializer
		- <clang-tidy/checks/cppcoreguidelines/prefer-member-initializer>` check to
		- avoid false positive when member initialization depends on a structured
		- binding variable.
		-
		-- Fixed :doc:`cppcoreguidelines-pro-type-union-access
		- <clang-tidy/checks/cppcoreguidelines/pro-type-union-access>` check to
		- report a location even when the member location is not valid.
		-
		-- Improved :doc:`misc-definitions-in-headers
		- <clang-tidy/checks/misc/definitions-in-headers>` check by rewording the
		- diagnostic note that suggests adding ``inline``.
		-
		-- Improved :doc:`misc-redundant-expression
		- <clang-tidy/checks/misc/redundant-expression>` check by extending the
		- checker to detect floating point and integer literals in redundant
		- expressions.
		-
		-- Improved :doc:`misc-unconventional-assign-operator
		- <clang-tidy/checks/misc/unconventional-assign-operator>` check to avoid
		- false positive for C++23 deducing this.
		-
		-- Improved :doc:`misc-use-internal-linkage
		- <clang-tidy/checks/misc/use-internal-linkage>` check to insert ``static``
		- keyword before type qualifiers such as ``const`` and ``volatile``. Also, fix
		- false positives for function declaration without body, C++20 consteval
		- functions, C++20 export declarations, and global scoped
		- overloaded ``operator new`` and ``operator delete``.
		-
		-- Improved :doc:`modernize-avoid-c-arrays
		- <clang-tidy/checks/modernize/avoid-c-arrays>` check to suggest using
		- ``std::span`` as a replacement for parameters of incomplete C array type in
		- C++20 and ``std::array`` or ``std::vector`` before C++20.
		-
		-- Improved :doc:`modernize-loop-convert
		- <clang-tidy/checks/modernize/loop-convert>` check to fix false positive when
		- using loop variable in initializer of lambda capture.
		-
		-- Improved :doc:`modernize-min-max-use-initializer-list
		- <clang-tidy/checks/modernize/min-max-use-initializer-list>` check by fixing
		- a false positive when only an implicit conversion happened inside an
		- initializer list.
		-
		-- Improved :doc:`modernize-raw-string-literal
		- <clang-tidy/checks/modernize/raw-string-literal>` check to fix incorrect
		- fix-it when the string contains a user-defined suffix.
		-
		-- Improved :doc:`modernize-use-designated-initializers
		- <clang-tidy/checks/modernize/use-designated-initializers>` check to fix a
		- crash when a class is declared but not defined.
		-
		-- Improved :doc:`modernize-use-integer-sign-comparison
		- <clang-tidy/checks/modernize/use-integer-sign-comparison>` check to
		- add an option ``EnableQtSupport``, that makes C++17 ``q20::cmp_*`` alternative
		- available for Qt-based applications.
		-
		-- Improved :doc:`modernize-use-nullptr
		- <clang-tidy/checks/modernize/use-nullptr>` check to also recognize
		- ``NULL``/``__null`` (but not ``0``) when used with a templated type.
		-
		-- Improved :doc:`modernize-use-starts-ends-with
		- <clang-tidy/checks/modernize/use-starts-ends-with>` check to handle two new
		- cases from ``rfind`` and ``compare`` to ``ends_with``, and one new case from
		- ``substr`` to ``starts_with``, and a small adjustment to the diagnostic message.
		-
		-- Improved :doc:`modernize-use-std-format
		- <clang-tidy/checks/modernize/use-std-format>` check to support replacing
		- member function calls too and to only expand macros starting with ``PRI``
		- and ``__PRI`` from ``<inttypes.h>`` in the format string.
		-
		-- Improved :doc:`modernize-use-std-print
		- <clang-tidy/checks/modernize/use-std-print>` check to support replacing
		- member function calls too and to only expand macros starting with ``PRI``
		- and ``__PRI`` from ``<inttypes.h>`` in the format string.
		-
		-- Improved :doc:`modernize-use-using
		- <clang-tidy/checks/modernize/use-using>` check by not expanding macros.
		-
		-- Improved :doc:`performance-avoid-endl
		- <clang-tidy/checks/performance/avoid-endl>` check to use ``std::endl`` as
		- placeholder when lexer cannot get source text.
		-
		-- Improved :doc:`performance-move-const-arg
		- <clang-tidy/checks/performance/move-const-arg>` check to fix a crash when
		- an argument type is declared but not defined.
		-
		-- Improved :doc:`performance-unnecessary-copy-initialization
		- <clang-tidy/checks/performance/unnecessary-copy-initialization>` check
		- to consider static member functions the same way as free functions.
		-
		-- Improved :doc:`readability-container-contains
		- <clang-tidy/checks/readability/container-contains>` check to let it work on
		- any class that has a ``contains`` method. Fix some false negatives in the
		- ``find()`` case.
		-
		-- Improved :doc:`readability-enum-initial-value
		- <clang-tidy/checks/readability/enum-initial-value>` check by only issuing
		- diagnostics for the definition of an ``enum``, by not emitting a redundant
		- file path for anonymous enums in the diagnostic, and by fixing a typo in the
		- diagnostic.
		-
		-- Improved :doc:`readability-identifier-naming
		- <clang-tidy/checks/readability/identifier-naming>` check to
		- validate ``namespace`` aliases.
		-
		-- Improved :doc:`readability-implicit-bool-conversion
		- <clang-tidy/checks/readability/implicit-bool-conversion>` check
		- by adding the option `UseUpperCaseLiteralSuffix` to select the
		- case of the literal suffix in fixes and fixing false positive for implicit
		- conversion of comparison result in C23.
		-
		-- Improved :doc:`readability-redundant-casting
		- <clang-tidy/checks/readability/redundant-casting>` check
		- by addressing a false positive in aggregate initialization through
		- parenthesized list.
		-
		-- Improved :doc:`readability-redundant-smartptr-get
		- <clang-tidy/checks/readability/redundant-smartptr-get>` check to
		- remove ``->``, when redundant ``get()`` is removed.
		-
		-- Improved :doc:`readability-use-std-min-max
		- <clang-tidy/checks/readability/use-std-min-max>` check to use correct template
		- type in ``std::min`` and ``std::max`` when operand is integer literal.
		-
		Removed checks
		^^^^^^^^^^^^^^
		Miscellaneous
		^^^^^^^^^^^^^
		-- The :doc:`bugprone-narrowing-conversions <clang-tidy/checks/bugprone/narrowing-conversions>`
		- check is no longer an alias of :doc:`cppcoreguidelines-narrowing-conversions
		- <clang-tidy/checks/cppcoreguidelines/narrowing-conversions>`. Instead,
		- :doc:`cppcoreguidelines-narrowing-conversions
		- <clang-tidy/checks/cppcoreguidelines/narrowing-conversions>` is now an alias
		- of :doc:`bugprone-narrowing-conversions <clang-tidy/checks/bugprone/narrowing-conversions>`.
		-
		Improvements to include-fixer
		-----------------------------

clang-tools-extra/docs/clang-tidy/checks/bugprone/assert-side-effect.rst

		@@ -26,8 +26,8 @@ Options
		A semicolon-separated list of the names of functions or methods to be
		considered as not having side-effects. Regular expressions are accepted,
		- e.g. `[Rr]ef(erence)?$` matches every type with suffix `Ref`, `ref`,
		- `Reference` and `reference`. The default is empty. If a name in the list
		- contains the sequence `::` it is matched against the qualified typename
		- (i.e. `namespace::Type`, otherwise it is matched against only
		- the type name (i.e. `Type`).
		+ e.g. ``[Rr]ef(erence)?$`` matches every type with suffix ``Ref``, ``ref``,
		+ ``Reference`` and ``reference``. The default is empty. If a name in the list
		+ contains the sequence `::` it is matched against the qualified type name
		+ (i.e. ``namespace::Type``), otherwise it is matched against only
		+ the type name (i.e. ``Type``).

clang-tools-extra/docs/clang-tidy/checks/performance/for-range-copy.rst

		@@ -23,14 +23,15 @@ Options
		.. option:: WarnOnAllAutoCopies
		- When `true`, warns on any use of `auto` as the type of the range-based for
		+ When `true`, warns on any use of ``auto`` as the type of the range-based for
		loop variable. Default is `false`.
		.. option:: AllowedTypes
		A semicolon-separated list of names of types allowed to be copied in each
		- iteration. Regular expressions are accepted, e.g. `[Rr]ef(erence)?$` matches
		- every type with suffix `Ref`, `ref`, `Reference` and `reference`. The default
		- is empty. If a name in the list contains the sequence `::` it is matched
		- against the qualified typename (i.e. `namespace::Type`, otherwise it is
		- matched against only the type name (i.e. `Type`).
		+ iteration. Regular expressions are accepted, e.g. ``[Rr]ef(erence)?$``
		+ matches every type with suffix ``Ref``, ``ref``, ``Reference`` and
		+ ``reference``. The default is empty. If a name in the list contains the
		+ sequence `::`, it is matched against the qualified type name
		+ (i.e. ``namespace::Type``), otherwise it is matched against only the
		+ type name (i.e. ``Type``).

clang-tools-extra/docs/clang-tidy/checks/performance/unnecessary-copy-initialization.rst

		@@ -42,11 +42,11 @@ Options
		.. option:: AllowedTypes
		A semicolon-separated list of names of types allowed to be initialized by
		- copying. Regular expressions are accepted, e.g. `[Rr]ef(erence)?$` matches
		- every type with suffix `Ref`, `ref`, `Reference` and `reference`. The default
		- is empty. If a name in the list contains the sequence `::` it is matched
		- against the qualified typename (i.e. `namespace::Type`, otherwise it is
		- matched against only the type name (i.e. `Type`).
		+ copying. Regular expressions are accepted, e.g. ``[Rr]ef(erence)?$`` matches
		+ every type with suffix ``Ref``, ``ref``, ``Reference`` and ``reference``.
		+ The default is empty. If a name in the list contains the sequence `::`, it
		+ is matched against the qualified type name (i.e. ``namespace::Type``),
		+ otherwise it is matched against only the type name (i.e. ``Type``).
		.. option:: ExcludedContainerTypes

clang-tools-extra/docs/clang-tidy/checks/performance/unnecessary-value-param.rst

		@@ -65,8 +65,8 @@ Options
		.. option:: AllowedTypes
		A semicolon-separated list of names of types allowed to be passed by value.
		- Regular expressions are accepted, e.g. `[Rr]ef(erence)?$` matches every type
		- with suffix `Ref`, `ref`, `Reference` and `reference`. The default is
		- empty. If a name in the list contains the sequence `::` it is matched against
		- the qualified typename (i.e. `namespace::Type`, otherwise it is matched
		- against only the type name (i.e. `Type`).
		+ Regular expressions are accepted, e.g. ``[Rr]ef(erence)?$`` matches every
		+ type with suffix ``Ref``, ``ref``, ``Reference`` and ``reference``. The
		+ default is empty. If a name in the list contains the sequence `::`, it is
		+ matched against the qualified type name (i.e. ``namespace::Type``),
		+ otherwise it is matched against only the type name (i.e. ``Type``).

clang/CMakeLists.txt

		@@ -331,6 +331,7 @@ if(NOT DEFINED CLANG_VERSION_SUFFIX)
		set(CLANG_VERSION_SUFFIX ${LLVM_VERSION_SUFFIX})
		endif()
		set(CLANG_VERSION "${CLANG_VERSION_MAJOR}.${CLANG_VERSION_MINOR}.${CLANG_VERSION_PATCHLEVEL}${CLANG_VERSION_SUFFIX}")
		+set(MAX_CLANG_ABI_COMPAT_VERSION "${LLVM_VERSION_MAJOR}")
		message(STATUS "Clang version: ${CLANG_VERSION}")
		# Configure the Version.inc file.
		@@ -431,18 +432,16 @@ if(NOT LLVM_STATIC_LINK_CXX_STDLIB)
		set(HAVE_CLANG_REPL_SUPPORT ON)
		endif()
		-option(CLANG_ENABLE_ARCMT "Build ARCMT." ON)
		+option(CLANG_ENABLE_OBJC_REWRITER "Build the Objective-C rewriter tool" OFF)
		+
		option(CLANG_ENABLE_STATIC_ANALYZER
		"Include static analyzer in clang binary." ON)
		option(CLANG_ENABLE_PROTO_FUZZER "Build Clang protobuf fuzzer." OFF)
		-if(NOT CLANG_ENABLE_STATIC_ANALYZER AND CLANG_ENABLE_ARCMT)
		- message(FATAL_ERROR "Cannot disable static analyzer while enabling ARCMT or Z3")
		-endif()
		-
		-if(CLANG_ENABLE_ARCMT)
		- set(CLANG_ENABLE_OBJC_REWRITER ON)
		+if (DEFINED CLANG_ENABLE_ARCMT)
		+ set(CLANG_ENABLE_OBJC_REWRITER ${CLANG_ENABLE_ARCMT})
		+ message(DEPRECATION "'CLANG_ENABLE_ARCMT' is deprecated as ARCMigrate has been removed from Clang. Please use 'CLANG_ENABLE_OBJC_REWRITER' instead to enable or disable the Objective-C rewriter.")
		endif()
		# This option is a stop-gap, we should commit to removing this as

clang/cmake/caches/Android.cmake

		@@ -2,7 +2,6 @@
		set(LLVM_TARGETS_TO_BUILD X86 CACHE STRING "")
		-set(CLANG_ENABLE_ARCMT OFF CACHE BOOL "")
		set(CLANG_ENABLE_STATIC_ANALYZER OFF CACHE BOOL "")
		set(CLANG_TIDY_ENABLE_STATIC_ANALYZER OFF CACHE BOOL "")
		set(CLANG_VENDOR Android CACHE STRING "")

clang/cmake/caches/Fuchsia-stage2.cmake

		@@ -44,7 +44,6 @@ set(CLANG_DEFAULT_LINKER lld CACHE STRING "")
		set(CLANG_DEFAULT_OBJCOPY llvm-objcopy CACHE STRING "")
		set(CLANG_DEFAULT_RTLIB compiler-rt CACHE STRING "")
		set(CLANG_DEFAULT_UNWINDLIB libunwind CACHE STRING "")
		-set(CLANG_ENABLE_ARCMT OFF CACHE BOOL "")
		set(CLANG_ENABLE_STATIC_ANALYZER ON CACHE BOOL "")
		set(CLANG_PLUGIN_SUPPORT OFF CACHE BOOL "")
		@@ -190,6 +189,10 @@ foreach(target aarch64-unknown-linux-gnu;armv7-unknown-linux-gnueabihf;i386-unkn
		set(RUNTIMES_${target}_LLVM_TOOLS_DIR "${CMAKE_BINARY_DIR}/bin" CACHE BOOL "")
		set(RUNTIMES_${target}_LLVM_ENABLE_RUNTIMES "compiler-rt;libcxx;libcxxabi;libunwind" CACHE STRING "")
		+ # Enable FatLTO for Linux and baremetal runtimes
		+ set(RUNTIMES_${target}_LLVM_ENABLE_LTO ON CACHE BOOL "")
		+ set(RUNTIMES_${target}_LLVM_ENABLE_FATLTO ON CACHE BOOL "")
		+
		# Use .build-id link.
		list(APPEND RUNTIME_BUILD_ID_LINK "${target}")
		endif()
		@@ -272,6 +275,10 @@ if(FUCHSIA_SDK)
		set(RUNTIMES_${target}+asan+noexcept_LIBCXXABI_ENABLE_EXCEPTIONS OFF CACHE BOOL "")
		set(RUNTIMES_${target}+asan+noexcept_LIBCXX_ENABLE_EXCEPTIONS OFF CACHE BOOL "")
		+ # Enable FatLTO for Fuchsia runtimes
		+ set(RUNTIMES_${target}_LLVM_ENABLE_LTO ON CACHE BOOL "")
		+ set(RUNTIMES_${target}_LLVM_ENABLE_FATLTO ON CACHE BOOL "")
		+
		# Use .build-id link.
		list(APPEND RUNTIME_BUILD_ID_LINK "${target}")
		endforeach()
		@@ -369,6 +376,10 @@ foreach(target armv6m-none-eabi;armv7m-none-eabi;armv7em-none-eabi;armv8m.main-n
		set(RUNTIMES_${target}_LLVM_INCLUDE_TESTS OFF CACHE BOOL "")
		set(RUNTIMES_${target}_LLVM_ENABLE_ASSERTIONS OFF CACHE BOOL "")
		set(RUNTIMES_${target}_LLVM_ENABLE_RUNTIMES "libc;libcxx" CACHE STRING "")
		+
		+ # Enable FatLTO for baremetal runtimes
		+ set(RUNTIMES_${target}_LLVM_ENABLE_LTO ON CACHE BOOL "")
		+ set(RUNTIMES_${target}_LLVM_ENABLE_FATLTO ON CACHE BOOL "")
		endforeach()
		foreach(target riscv32-unknown-elf)
		@@ -420,6 +431,10 @@ foreach(target riscv32-unknown-elf)
		set(RUNTIMES_${target}_LLVM_INCLUDE_TESTS OFF CACHE BOOL "")
		set(RUNTIMES_${target}_LLVM_ENABLE_ASSERTIONS OFF CACHE BOOL "")
		set(RUNTIMES_${target}_LLVM_ENABLE_RUNTIMES "libc;libcxx" CACHE STRING "")
		+
		+ # Enable FatLTO for baremetal runtimes
		+ set(RUNTIMES_${target}_LLVM_ENABLE_LTO ON CACHE BOOL "")
		+ set(RUNTIMES_${target}_LLVM_ENABLE_FATLTO ON CACHE BOOL "")
		endforeach()
		set(LLVM_BUILTIN_TARGETS "${BUILTIN_TARGETS}" CACHE STRING "")

clang/cmake/caches/Fuchsia.cmake

		@@ -84,7 +84,6 @@ set(CLANG_DEFAULT_LINKER lld CACHE STRING "")
		set(CLANG_DEFAULT_OBJCOPY llvm-objcopy CACHE STRING "")
		set(CLANG_DEFAULT_RTLIB compiler-rt CACHE STRING "")
		set(CLANG_DEFAULT_UNWINDLIB libunwind CACHE STRING "")
		-set(CLANG_ENABLE_ARCMT OFF CACHE BOOL "")
		set(CLANG_ENABLE_STATIC_ANALYZER OFF CACHE BOOL "")
		set(CLANG_PLUGIN_SUPPORT OFF CACHE BOOL "")

clang/docs/ClangFormatStyleOptions.rst

		@@ -5198,6 +5198,11 @@ the configuration (without a prefix: ``Auto``).
		**PenaltyBreakBeforeFirstCallParameter** (``Unsigned``) :versionbadge:`clang-format 3.7` :ref:`¶ <PenaltyBreakBeforeFirstCallParameter>`
		The penalty for breaking a function call after ``call(``.
		+.. _PenaltyBreakBeforeMemberAccess:
		+
		+**PenaltyBreakBeforeMemberAccess** (``Unsigned``) :versionbadge:`clang-format 20` :ref:`¶ <PenaltyBreakBeforeMemberAccess>`
		+ The penalty for breaking before a member access operator (``.``, ``->``).
		+
		.. _PenaltyBreakComment:
		**PenaltyBreakComment** (``Unsigned``) :versionbadge:`clang-format 3.7` :ref:`¶ <PenaltyBreakComment>`

clang/docs/HIPSupport.rst

		@@ -27,7 +27,8 @@ AMD GPU Support
		Clang provides HIP support on AMD GPUs via the ROCm platform `<https://rocm.docs.amd.com/en/latest/#>`_.
		The ROCm runtime forms the base for HIP host APIs, while HIP device APIs are realized through HIP header
		files and the ROCm device library. The Clang driver uses the HIPAMD toolchain to compile HIP device code
		-to AMDGPU ISA via the AMDGPU backend. The compiled code is then bundled and embedded in the host executables.
		+to AMDGPU ISA via the AMDGPU backend, or SPIR-V via the workflow outlined below.
		+The compiled code is then bundled and embedded in the host executables.
		Intel GPU Support
		=================
		@@ -285,6 +286,401 @@ Example Usage
		basePtr->virtualFunction(); // Allowed since obj is constructed in device code
		}
		+C++ Standard Parallelism Offload Support: Compiler And Runtime
		+==============================================================
		+
		+Introduction
		+============
		+
		+This section describes the implementation of support for offloading the
		+execution of standard C++ algorithms to accelerators that can be targeted via
		+HIP. Furthermore, it enumerates restrictions on user defined code, as well as
		+the interactions with runtimes.
		+
		+Algorithm Offload: What, Why, Where
		+===================================
		+
		+C++17 introduced overloads
		+`for most algorithms in the standard library <https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0024r2.html>`_
		+which allow the user to specify a desired
		+`execution policy <https://en.cppreference.com/w/cpp/algorithm#Execution_policies>`_.
		+The `parallel_unsequenced_policy <https://en.cppreference.com/w/cpp/algorithm/execution_policy_tag_t>`_
		+maps relatively well to the execution model of AMD GPUs. This, coupled with the
		+the availability and maturity of GPU accelerated algorithm libraries that
		+implement most / all corresponding algorithms in the standard library
		+(e.g. `rocThrust <https://github.com/ROCmSoftwarePlatform/rocThrust>`__), makes
		+it feasible to provide seamless accelerator offload for supported algorithms,
		+when an accelerated version exists. Thus, it becomes possible to easily access
		+the computational resources of an AMD accelerator, via a well specified,
		+familiar, algorithmic interface, without having to delve into low-level hardware
		+specific details. Putting it all together:
		+
		+- **What**: standard library algorithms, when invoked with the
		+ ``parallel_unsequenced_policy``
		+- **Why**: democratise AMDGPU accelerator programming, without loss of user
		+ familiarity
		+- **Where**: only AMDGPU accelerators targeted by Clang/LLVM via HIP
		+
		+Small Example
		+=============
		+
		+Given the following C++ code:
		+
		+.. code-block:: C++
		+
		+ bool has_the_answer(const std::vector<int>& v) {
		+ return std::find(std::execution::par_unseq, std::cbegin(v), std::cend(v), 42) != std::cend(v);
		+ }
		+
		+if Clang is invoked with the ``--hipstdpar --offload-arch=foo`` flags, the call
		+to ``find`` will be offloaded to an accelerator that is part of the ``foo``
		+target family. If either ``foo`` or its runtime environment do not support
		+transparent on-demand paging (such as e.g. that provided in Linux via
		+`HMM <https://docs.kernel.org/mm/hmm.html>`_), it is necessary to also include
		+the ``--hipstdpar-interpose-alloc`` flag. If the accelerator specific algorithm
		+library ``foo`` uses doesn't have an implementation of a particular algorithm,
		+execution seamlessly falls back to the host CPU. It is legal to specify multiple
		+``--offload-arch``\s. All the flags we introduce, as well as a thorough view of
		+various restrictions an their implementations, will be provided below.
		+
		+Implementation - General View
		+=============================
		+
		+We built support for Algorithm Offload support atop the pre-existing HIP
		+infrastructure. More specifically, when one requests offload via ``--hipstdpar``,
		+compilation is switched to HIP compilation, as if ``-x hip`` was specified.
		+Similarly, linking is also switched to HIP linking, as if ``--hip-link`` was
		+specified. Note that these are implicit, and one should not assume that any
		+interop with HIP specific language constructs is available e.g. ``__device__``
		+annotations are neither necessary nor guaranteed to work.
		+
		+Since there are no language restriction mechanisms in place, it is necessary to
		+relax HIP language specific semantic checks performed by the FE; they would
		+identify otherwise valid, offloadable code, as invalid HIP code. Given that we
		+know that the user intended only for certain algorithms to be offloaded, and
		+encoded this by specifying the ``parallel_unsequenced_policy``, we rely on a
		+pass over IR to clean up any and all code that was not "meant" for offload. If
		+requested, allocation interposition is also handled via a separate pass over IR.
		+
		+To interface with the client HIP runtime, and to forward offloaded algorithm
		+invocations to the corresponding accelerator specific library implementation, an
		+implementation detail forwarding header is implicitly included by the driver,
		+when compiling with ``--hipstdpar``. In what follows, we will delve into each
		+component that contributes to implementing Algorithm Offload support.
		+
		+Implementation - Driver
		+=======================
		+
		+We augment the ``clang`` driver with the following flags:
		+
		+- ``--hipstdpar`` enables algorithm offload, which depending on phase, has the
		+ following effects:
		+
		+ - when compiling:
		+
		+ - ``-x hip`` gets prepended to enable HIP support;
		+ - the ``ROCmToolchain`` component checks for the ``hipstdpar_lib.hpp``
		+ forwarding header,
		+ `rocThrust <https://rocm.docs.amd.com/projects/rocThrust/en/latest/>`_ and
		+ `rocPrim <https://rocm.docs.amd.com/projects/rocPRIM/en/latest/>`_ in
		+ their canonical locations, which can be overriden via flags found below;
		+ if all are found, the forwarding header gets implicitly included,
		+ otherwise an error listing the missing component is generated;
		+ - the ``LangOpts.HIPStdPar`` member is set.
		+
		+ - when linking:
		+
		+ - ``--hip-link`` and ``-frtlib-add-rpath`` gets appended to enable HIP
		+ support.
		+
		+- ``--hipstdpar-interpose-alloc`` enables the interposition of standard
		+ allocation / deallocation functions with accelerator aware equivalents; the
		+ ``LangOpts.HIPStdParInterposeAlloc`` member is set;
		+- ``--hipstdpar-path=`` specifies a non-canonical path for the forwarding
		+ header; it must point to the folder where the header is located and not to the
		+ header itself;
		+- ``--hipstdpar-thrust-path=`` specifies a non-canonical path for
		+ `rocThrust <https://rocm.docs.amd.com/projects/rocThrust/en/latest/>`_; it
		+ must point to the folder where the library is installed / built under a
		+ ``/thrust`` subfolder;
		+- ``--hipstdpar-prim-path=`` specifies a non-canonical path for
		+ `rocPrim <https://rocm.docs.amd.com/projects/rocPRIM/en/latest/>`_; it must
		+ point to the folder where the library is installed / built under a
		+ ``/rocprim`` subfolder;
		+
		+The `--offload-arch <https://llvm.org/docs/AMDGPUUsage.html#amdgpu-processors>`_
		+flag can be used to specify the accelerator for which offload code is to be
		+generated.
		+
		+Implementation - Front-End
		+==========================
		+
		+When ``LangOpts.HIPStdPar`` is set, we relax some of the HIP language specific
		+``Sema`` checks to account for the fact that we want to consume pure unannotated
		+C++ code:
		+
		+1. ``__device__`` / ``__host__ __device__`` functions (which would originate in
		+ the accelerator specific algorithm library) are allowed to call implicitly
		+ ``__host__`` functions;
		+2. ``__global__`` functions (which would originate in the accelerator specific
		+ algorithm library) are allowed to call implicitly ``__host__`` functions;
		+3. resolving ``__builtin`` availability is deferred, because it is possible that
		+ a ``__builtin`` that is unavailable on the target accelerator is not
		+ reachable from any offloaded algorithm, and thus will be safely removed in
		+ the middle-end;
		+4. ASM parsing / checking is deferred, because it is possible that an ASM block
		+ that e.g. uses some constraints that are incompatible with the target
		+ accelerator is not reachable from any offloaded algorithm, and thus will be
		+ safely removed in the middle-end.
		+
		+``CodeGen`` is similarly relaxed, with implicitly ``__host__`` functions being
		+emitted as well.
		+
		+Implementation - Middle-End
		+===========================
		+
		+We add two ``opt`` passes:
		+
		+1. ``HipStdParAcceleratorCodeSelectionPass``
		+
		+ - For all kernels in a ``Module``, compute reachability, where a function
		+ ``F`` is reachable from a kernel ``K`` if and only if there exists a direct
		+ call-chain rooted in ``F`` that includes ``K``;
		+ - Remove all functions that are not reachable from kernels;
		+ - This pass is only run when compiling for the accelerator.
		+
		+The first pass assumes that the only code that the user intended to offload was
		+that which was directly or transitively invocable as part of an algorithm
		+execution. It also assumes that an accelerator aware algorithm implementation
		+would rely on accelerator specific special functions (kernels), and that these
		+effectively constitute the only roots for accelerator execution graphs. Both of
		+these assumptions are based on observing how widespread accelerators,
		+such as GPUs, work.
		+
		+1. ``HipStdParAllocationInterpositionPass``
		+
		+ - Iterate through all functions in a ``Module``, and replace standard
		+ allocation / deallocation functions with accelerator-aware equivalents,
		+ based on a pre-established table; the list of functions that can be
		+ interposed is available
		+ `here <https://github.com/ROCmSoftwarePlatform/roc-stdpar#allocation--deallocation-interposition-status>`__;
		+ - This is only run when compiling for the host.
		+
		+The second pass is optional.
		+
		+Implementation - Forwarding Header
		+==================================
		+
		+The forwarding header implements two pieces of functionality:
		+
		+1. It forwards algorithms to a target accelerator, which is done by relying on
		+ C++ language rules around overloading:
		+
		+ - overloads taking an explicit argument of type
		+ ``parallel_unsequenced_policy`` are introduced into the ``std`` namespace;
		+ - these will get preferentially selected versus the master template;
		+ - the body forwards to the equivalent algorithm from the accelerator specific
		+ library
		+
		+2. It provides allocation / deallocation functions that are equivalent to the
		+ standard ones, but obtain memory by invoking
		+ `hipMallocManaged <https://rocm.docs.amd.com/projects/HIP/en/latest/.doxygen/docBin/html/group___memory_m.html#gab8cfa0e292193fa37e0cc2e4911fa90a>`_
		+ and release it via `hipFree <https://rocm.docs.amd.com/projects/HIP/en/latest/.doxygen/docBin/html/group___memory.html#ga740d08da65cae1441ba32f8fedb863d1>`_.
		+
		+Predefined Macros
		+=================
		+
		+.. list-table::
		+ :header-rows: 1
		+
		+ * - Macro
		+ - Description
		+ * - ``__HIPSTDPAR__``
		+ - Defined when Clang is compiling code in algorithm offload mode, enabled
		+ with the ``--hipstdpar`` compiler option.
		+ * - ``__HIPSTDPAR_INTERPOSE_ALLOC__``
		+ - Defined only when compiling in algorithm offload mode, when the user
		+ enables interposition mode with the ``--hipstdpar-interpose-alloc``
		+ compiler option, indicating that all dynamic memory allocation /
		+ deallocation functions should be replaced with accelerator aware
		+ variants.
		+
		+Restrictions
		+============
		+
		+We define two modes in which runtime execution can occur:
		+
		+1. **HMM Mode** - this assumes that the
		+ `HMM <https://docs.kernel.org/mm/hmm.html>`_ subsystem of the Linux kernel
		+ is used to provide transparent on-demand paging i.e. memory obtained from a
		+ system / OS allocator such as via a call to ``malloc`` or ``operator new`` is
		+ directly accessible to the accelerator and it follows the C++ memory model;
		+2. **Interposition Mode** - this is a fallback mode for cases where transparent
		+ on-demand paging is unavailable (e.g. in the Windows OS), which means that
		+ memory must be allocated via an accelerator aware mechanism, and system
		+ allocated memory is inaccessible for the accelerator.
		+
		+The following restrictions imposed on user code apply to both modes:
		+
		+1. Pointers to function, and all associated features, such as e.g. dynamic
		+ polymorphism, cannot be used (directly or transitively) by the user provided
		+ callable passed to an algorithm invocation;
		+2. Global / namespace scope / ``static`` / ``thread`` storage duration variables
		+ cannot be used (directly or transitively) in name by the user provided
		+ callable;
		+
		+ - When executing in **HMM Mode** they can be used in address e.g.:
		+
		+ .. code-block:: C++
		+
		+ namespace { int foo = 42; }
		+
		+ bool never(const std::vector<int>& v) {
		+ return std::any_of(std::execution::par_unseq, std::cbegin(v), std::cend(v), [](auto&& x) {
		+ return x == foo;
		+ });
		+ }
		+
		+ bool only_in_hmm_mode(const std::vector<int>& v) {
		+ return std::any_of(std::execution::par_unseq, std::cbegin(v), std::cend(v),
		+ [p = &foo](auto&& x) { return x == *p; });
		+ }
		+
		+3. Only algorithms that are invoked with the ``parallel_unsequenced_policy`` are
		+ candidates for offload;
		+4. Only algorithms that are invoked with iterator arguments that model
		+ `random_access_iterator <https://en.cppreference.com/w/cpp/iterator/random_access_iterator>`_
		+ are candidates for offload;
		+5. `Exceptions <https://en.cppreference.com/w/cpp/language/exceptions>`_ cannot
		+ be used by the user provided callable;
		+6. Dynamic memory allocation (e.g. ``operator new``) cannot be used by the user
		+ provided callable;
		+7. Selective offload is not possible i.e. it is not possible to indicate that
		+ only some algorithms invoked with the ``parallel_unsequenced_policy`` are to
		+ be executed on the accelerator.
		+
		+In addition to the above, using **Interposition Mode** imposes the following
		+additional restrictions:
		+
		+1. All code that is expected to interoperate has to be recompiled with the
		+ ``--hipstdpar-interpose-alloc`` flag i.e. it is not safe to compose libraries
		+ that have been independently compiled;
		+2. automatic storage duration (i.e. stack allocated) variables cannot be used
		+ (directly or transitively) by the user provided callable e.g.
		+
		+ .. code-block:: c++
		+
		+ bool never(const std::vector<int>& v, int n) {
		+ return std::any_of(std::execution::par_unseq, std::cbegin(v), std::cend(v),
		+ [p = &n](auto&& x) { return x == *p; });
		+ }
		+
		+Current Support
		+===============
		+
		+At the moment, C++ Standard Parallelism Offload is only available for AMD GPUs,
		+when the `ROCm <https://rocm.docs.amd.com/en/latest/>`_ stack is used, on the
		+Linux operating system. Support is synthesised in the following table:
		+
		+.. list-table::
		+ :header-rows: 1
		+
		+ * - `Processor <https://llvm.org/docs/AMDGPUUsage.html#amdgpu-processors>`_
		+ - HMM Mode
		+ - Interposition Mode
		+ * - GCN GFX9 (Vega)
		+ - YES
		+ - YES
		+ * - GCN GFX10.1 (RDNA 1)
		+ - *NO*
		+ - YES
		+ * - GCN GFX10.3 (RDNA 2)
		+ - *NO*
		+ - YES
		+ * - GCN GFX11 (RDNA 3)
		+ - *NO*
		+ - YES
		+ * - GCN GFX12 (RDNA 4)
		+ - *NO*
		+ - YES
		+
		+The minimum Linux kernel version for running in HMM mode is 6.4.
		+
		+The forwarding header can be obtained from
		+`its GitHub repository <https://github.com/ROCmSoftwarePlatform/roc-stdpar>`_.
		+It will be packaged with a future `ROCm <https://rocm.docs.amd.com/en/latest/>`_
		+release. Because accelerated algorithms are provided via
		+`rocThrust <https://rocm.docs.amd.com/projects/rocThrust/en/latest/>`_, a
		+transitive dependency on
		+`rocPrim <https://rocm.docs.amd.com/projects/rocPRIM/en/latest/>`_ exists. Both
		+can be obtained either by installing their associated components of the
		+`ROCm <https://rocm.docs.amd.com/en/latest/>`_ stack, or from their respective
		+repositories. The list algorithms that can be offloaded is available
		+`here <https://github.com/ROCmSoftwarePlatform/roc-stdpar#algorithm-support-status>`_.
		+
		+HIP Specific Elements
		+---------------------
		+
		+1. There is no defined interop with the
		+ `HIP kernel language <https://rocm.docs.amd.com/projects/HIP/en/latest/reference/kernel_language.html>`_;
		+ whilst things like using `__device__` annotations might accidentally "work",
		+ they are not guaranteed to, and thus cannot be relied upon by user code;
		+
		+ - A consequence of the above is that both bitcode linking and linking
		+ relocatable object files will "work", but it is not guaranteed to remain
		+ working or actively tested at the moment; this restriction might be relaxed
		+ in the future.
		+
		+2. Combining explicit HIP, CUDA or OpenMP Offload compilation with
		+ ``--hipstdpar`` based offloading is not allowed or supported in any way.
		+3. There is no way to target different accelerators via a standard algorithm
		+ invocation (`this might be addressed in future C++ standards <https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2023/p2500r1.html>`_);
		+ an unsafe (per the point above) way of achieving this is to spawn new threads
		+ and invoke the `hipSetDevice <https://rocm.docs.amd.com/projects/HIP/en/latest/.doxygen/docBin/html/group___device.html#ga43c1e7f15925eeb762195ccb5e063eae>`_
		+ interface e.g.:
		+
		+ .. code-block:: c++
		+
		+ int accelerator_0 = ...;
		+ int accelerator_1 = ...;
		+
		+ bool multiple_accelerators(const std::vector<int>& u, const std::vector<int>& v) {
		+ std::atomic<unsigned int> r{0u};
		+
		+ thread t0{[&]() {
		+ hipSetDevice(accelerator_0);
		+
		+ r += std::count(std::execution::par_unseq, std::cbegin(u), std::cend(u), 42);
		+ }};
		+ thread t1{[&]() {
		+ hitSetDevice(accelerator_1);
		+
		+ r += std::count(std::execution::par_unseq, std::cbegin(v), std::cend(v), 314152)
		+ }};
		+
		+ t0.join();
		+ t1.join();
		+
		+ return r;
		+ }
		+
		+ Note that this is a temporary, unsafe workaround for a deficiency in the C++
		+ Standard.
		+
		+Open Questions / Future Developments
		+====================================
		+
		+1. The restriction on the use of global / namespace scope / ``static`` /
		+ ``thread`` storage duration variables in offloaded algorithms will be lifted
		+ in the future, when running in **HMM Mode**;
		+2. The restriction on the use of dynamic memory allocation in offloaded
		+ algorithms will be lifted in the future.
		+3. The restriction on the use of pointers to function, and associated features
		+ such as dynamic polymorphism might be lifted in the future, when running in
		+ **HMM Mode**;
		+4. Offload support might be extended to cases where the ``parallel_policy`` is
		+ used for some or all targets.
		+
		SPIR-V Support on HIPAMD ToolChain
		==================================
		@@ -316,13 +712,6 @@ Using ``--offload-arch=amdgcnspirv``
		- **Clang Offload Bundler**: The resulting SPIR-V is embedded in the Clang
		offload bundler with the bundle ID ``hip-spirv64-amd-amdhsa--amdgcnspirv``.
		-Mixed with Normal ``--offload-arch``
		-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
		-
		-**Mixing ``amdgcnspirv`` and concrete ``gfx###`` targets via ``--offload-arch``
		-is not currently supported; this limitation is temporary and will be removed in
		-a future release**
		-
		Architecture Specific Macros
		----------------------------

clang/docs/LanguageExtensions.rst

		@@ -514,9 +514,7 @@ available in all language modes.
		__nullptr
		---------
		-``__nullptr`` is an alternate spelling for ``nullptr``, but is also available in
		-C++ modes prior to C++11. Note that it's currently not availbale in C despite
		-C23 having support for ``nullptr``.
		+``__nullptr`` is an alternate spelling for ``nullptr``. It is available in all C and C++ language modes.
		__signed, __signed__
		--------------------
		@@ -759,6 +757,9 @@ The integer elementwise intrinsics, including ``__builtin_elementwise_popcount``
		``__builtin_elementwise_bitreverse``, ``__builtin_elementwise_add_sat``,
		``__builtin_elementwise_sub_sat`` can be called in a ``constexpr`` context.
		+No implicit promotion of integer types takes place. The mixing of integer types
		+of different sizes and signs is forbidden in binary and ternary builtins.
		+
		============================================== ====================================================================== =========================================
		Name Operation Supported element types
		============================================== ====================================================================== =========================================

clang/docs/ReleaseNotes.rst

		@@ -33,219 +33,18 @@ latest release, please see the `Clang Web Site <https://clang.llvm.org>`_ or the
		Potentially Breaking Changes
		============================
		-These changes are ones which we think may surprise users when upgrading to
		-Clang |release| because of the opportunity they pose for disruption to existing
		-code bases.
		-
		-- The ``le32`` and ``le64`` targets have been removed.
		-
		-- ``clang -m32`` defaults to ``-mcpu=v9`` on SPARC Linux now. Distros
		- still supporting SPARC V8 CPUs need to specify ``-mcpu=v8`` with a
		- `config file
		- <https://clang.llvm.org/docs/UsersManual.html#configuration-files>`_.
		-
		-- The ``clang-rename`` tool has been removed.
		-
		-- Removed support for RenderScript targets. This technology is
		- `officially deprecated <https://developer.android.com/guide/topics/renderscript/compute>`_
		- and users are encouraged to
		- `migrate to Vulkan <https://developer.android.com/guide/topics/renderscript/migrate>`_
		- or other options.
		-
		-- Clang now emits distinct type-based alias analysis tags for incompatible
		- pointers by default, enabling more powerful alias analysis when accessing
		- pointer types. This change may silently change code behavior for code
		- containing strict-aliasing violations. The new default behavior can be
		- disabled using ``-fno-pointer-tbaa``.
		-
		-- Clang will now more aggressively use undefined behavior on pointer addition
		- overflow for optimization purposes. For example, a check like
		- ``ptr + unsigned_offset < ptr`` will now optimize to ``false``, because
		- ``ptr + unsigned_offset`` will cause undefined behavior if it overflows (or
		- advances past the end of the object).
		-
		- Previously, ``ptr + unsigned_offset < ptr`` was optimized (by both Clang and
		- GCC) to ``(ssize_t)unsigned_offset < 0``. This also results in an incorrect
		- overflow check, but in a way that is less apparent when only testing with
		- pointers in the low half of the address space.
		-
		- To avoid pointer addition overflow, it is necessary to perform the addition
		- on integers, for example using
		- ``(uintptr_t)ptr + unsigned_offset < (uintptr_t)ptr``. Sometimes, it is also
		- possible to rewrite checks by only comparing the offset. For example,
		- ``ptr + offset < end_ptr && ptr + offset >= ptr`` can be written as
		- ``offset < (uintptr_t)(end_ptr - ptr)``.
		-
		- Undefined behavior due to pointer addition overflow can be reliably detected
		- using ``-fsanitize=pointer-overflow``. It is also possible to use
		- ``-fno-strict-overflow`` to opt-in to a language dialect where signed integer
		- and pointer overflow are well-defined.
		+
		+- The Objective-C ARC migrator (ARCMigrate) has been removed.
		C/C++ Language Potentially Breaking Changes
		-------------------------------------------
		-- Clang now rejects ``_Complex _BitInt`` types.
		-
		C++ Specific Potentially Breaking Changes
		-----------------------------------------
		-- The type trait builtin ``__is_nullptr`` has been removed, since it has very
		- few users and can be written as ``__is_same(__remove_cv(T), decltype(nullptr))``,
		- which GCC supports as well.
		-
		-- The type trait builtin ``__is_referenceable`` has been deprecated, since it has
		- very few users and all the type traits that could benefit from it in the
		- standard library already have their own bespoke builtins. It will be removed in
		- Clang 21.
		-
		-- Clang will now correctly diagnose as ill-formed a constant expression where an
		- enum without a fixed underlying type is set to a value outside the range of
		- the enumeration's values.
		-
		- .. code-block:: c++
		-
		- enum E { Zero, One, Two, Three, Four };
		- constexpr E Val1 = (E)3; // Ok
		- constexpr E Val2 = (E)7; // Ok
		- constexpr E Val3 = (E)8; // Now ill-formed, out of the range [0, 7]
		- constexpr E Val4 = (E)-1; // Now ill-formed, out of the range [0, 7]
		-
		- Since Clang 16, it has been possible to suppress the diagnostic via
		- `-Wno-enum-constexpr-conversion`, to allow for a transition period for users.
		- Now, in Clang 20, **it is no longer possible to suppress the diagnostic**.
		-
		-- Extraneous template headers are now ill-formed by default.
		- This error can be disable with ``-Wno-error=extraneous-template-head``.
		-
		- .. code-block:: c++
		-
		- template <> // error: extraneous template head
		- template <typename T>
		- void f();
		-
		-- During constant evaluation, comparisons between different evaluations of the
		- same string literal are now correctly treated as non-constant, and comparisons
		- between string literals that cannot possibly overlap in memory are now treated
		- as constant. This updates Clang to match the anticipated direction of open core
		- issue `CWG2765 <http://wg21.link/CWG2765>`, but is subject to change once that
		- issue is resolved.
		-
		- .. code-block:: c++
		-
		- constexpr const char *f() { return "hello"; }
		- constexpr const char *g() { return "world"; }
		- // Used to evaluate to false, now error: non-constant comparison.
		- constexpr bool a = f() == f();
		- // Might evaluate to true or false, as before.
		- bool at_runtime() { return f() == f(); }
		- // Was error, now evaluates to false.
		- constexpr bool b = f() == g();
		-
		-- Clang will now correctly not consider pointers to non classes for covariance
		- and disallow changing return type to a type that doesn't have the same or less cv-qualifications.
		-
		- .. code-block:: c++
		-
		- struct A {
		- virtual const int *f() const;
		- virtual const std::string *g() const;
		- };
		- struct B : A {
		- // Return type has less cv-qualification but doesn't point to a class.
		- // Error will be generated.
		- int *f() const override;
		-
		- // Return type doesn't have more cv-qualification also not the same or
		- // less cv-qualification.
		- // Error will be generated.
		- volatile std::string *g() const override;
		- };
		-
		-- The warning ``-Wdeprecated-literal-operator`` is now on by default, as this is
		- something that WG21 has shown interest in removing from the language. The
		- result is that anyone who is compiling with ``-Werror`` should see this
		- diagnostic. To fix this diagnostic, simply removing the space character from
		- between the ``operator""`` and the user defined literal name will make the
		- source no longer deprecated. This is consistent with `CWG2521 <https://cplusplus.github.io/CWG/issues/2521.html>_`.
		-
		- .. code-block:: c++
		-
		- // Now diagnoses by default.
		- unsigned operator"" _udl_name(unsigned long long);
		- // Fixed version:
		- unsigned operator""_udl_name(unsigned long long);
		-
		-- Clang will now produce an error diagnostic when ``[[clang::lifetimebound]]`` is
		- applied on a parameter or an implicit object parameter of a function that
		- returns void. This was previously ignored and had no effect. (#GH107556)
		-
		- .. code-block:: c++
		-
		- // Now diagnoses with an error.
		- void f(int& i [[clang::lifetimebound]]);
		-
		-- Clang will now produce an error diagnostic when ``[[clang::lifetimebound]]``
		- is applied on a type (instead of a function parameter or an implicit object
		- parameter); this includes the case when the attribute is specified for an
		- unnamed function parameter. These were previously ignored and had no effect.
		- (#GH118281)
		-
		- .. code-block:: c++
		-
		- // Now diagnoses with an error.
		- int* [[clang::lifetimebound]] x;
		- // Now diagnoses with an error.
		- void f(int* [[clang::lifetimebound]] i);
		- // Now diagnoses with an error.
		- void g(int* [[clang::lifetimebound]]);
		-
		-- Clang now rejects all field accesses on null pointers in constant expressions. The following code
		- used to work but will now be rejected:
		-
		- .. code-block:: c++
		-
		- struct S { int a; int b; };
		- constexpr const int *p = &((S*)nullptr)->b;
		-
		- Previously, this code was erroneously accepted.
		-
		-- Clang will now consider the implicitly deleted destructor of a union or
		- a non-union class without virtual base class to be ``constexpr`` in C++20
		- mode (Clang 19 only did so in C++23 mode but the standard specification for
		- this changed in C++20). (#GH85550)
		-
		- .. code-block:: c++
		-
		- struct NonLiteral {
		- NonLiteral() {}
		- ~NonLiteral() {}
		- };
		-
		- template <class T>
		- struct Opt {
		- union {
		- char c;
		- T data;
		- };
		- bool engaged = false;
		-
		- constexpr Opt() {}
		- constexpr ~Opt() {
		- if (engaged)
		- data.~T();
		- }
		- };
		-
		- // Previously only accepted in C++23 and later, now also accepted in C++20.
		- consteval void foo() { Opt<NonLiteral>{}; }
		-
		ABI Changes in This Version
		---------------------------
		Bulk data, 387 bytes
		-- Fixed the Itanium mangling of the construction vtable name. This change will introduce incompatibilities with code compiled by Clang 19 and earlier versions, unless the -fclang-abi-compat=19 option is used. (#GH108015)
		-- Mangle member-like friend function templates as members of the enclosing class. (#GH110247, #GH110503)
		-
		AST Dumping Potentially Breaking Changes
		----------------------------------------
		@@ -254,581 +53,63 @@ Clang Frontend Potentially Breaking Changes
		Clang Python Bindings Potentially Breaking Changes
		--------------------------------------------------
		-- Parts of the interface returning string results will now return
		- the empty string ``""`` when no result is available, instead of ``None``.
		-- Calling a property on the ``CompletionChunk`` or ``CompletionString`` class
		- statically now leads to an error, instead of returning a ``CachedProperty`` object
		- that is used internally. Properties are only available on instances.
		-- For a single-line ``SourceRange`` and a ``SourceLocation`` in the same line,
		- but after the end of the ``SourceRange``, ``SourceRange.__contains__``
		- used to incorrectly return ``True``. (#GH22617), (#GH52827)
		What's New in Clang |release|?
		==============================
		-Some of the major new features and improvements to Clang are listed
		-here. Generic improvements to Clang as a whole or to its underlying
		-infrastructure are described first, followed by language-specific
		-sections with improvements to Clang's support for those languages.
		C++ Language Changes
		--------------------
		-- Allow single element access of GCC vector/ext_vector_type object to be
		- constant expression. Supports the `V.xyzw` syntax and other tidbits
		- as seen in OpenCL. Selecting multiple elements is left as a future work.
		-- Implement `CWG1815 <https://wg21.link/CWG1815>`_. Support lifetime extension
		- of temporary created by aggregate initialization using a default member
		- initializer.
		-
		-- Accept C++26 user-defined ``static_assert`` messages in C++11 as an extension.
		-
		-- Add ``__builtin_elementwise_popcount`` builtin for integer types only.
		-
		-- Add ``__builtin_elementwise_fmod`` builtin for floating point types only.
		-
		-- Add ``__builtin_elementwise_minimum`` and ``__builtin_elementwise_maximum``
		- builtin for floating point types only.
		-
		-- The builtin type alias ``__builtin_common_type`` has been added to improve the
		- performance of ``std::common_type``.
		C++2c Feature Support
		^^^^^^^^^^^^^^^^^^^^^
		-- Add ``__builtin_is_virtual_base_of`` intrinsic, which supports
		- `P2985R0 A type trait for detecting virtual base classes <https://wg21.link/p2985r0>`_
		-
		-- Implemented `P2893R3 Variadic Friends <https://wg21.link/P2893>`_
		-
		-- Implemented `P2747R2 constexpr placement new <https://wg21.link/P2747R2>`_.
		-
		-- Added the ``__builtin_is_within_lifetime`` builtin, which supports
		- `P2641R4 Checking if a union alternative is active <https://wg21.link/p2641r4>`_
		-
		-- Implemented `P3176R1 The Oxford variadic comma <https://wg21.link/P3176R1>`_
		-
		C++23 Feature Support
		^^^^^^^^^^^^^^^^^^^^^
		-- Removed the restriction to literal types in constexpr functions in C++23 mode.
		-
		-- Extend lifetime of temporaries in mem-default-init for P2718R0. Clang now fully
		- supports `P2718R0 Lifetime extension in range-based for loops <https://wg21.link/P2718R0>`_.
		-
		-- ``__cpp_explicit_this_parameter`` is now defined. (#GH82780)
		-
		-- Add ``__builtin_is_implicit_lifetime`` intrinsic, which supports
		- `P2674R1 A trait for implicit lifetime types <https://wg21.link/p2674r1>`_
		-
		-- Add support for `P2280R4 Using unknown pointers and references in constant expressions <https://wg21.link/P2280R4>`_. (#GH63139)
		C++20 Feature Support
		^^^^^^^^^^^^^^^^^^^^^
		-- Implemented module level lookup for C++20 modules. (#GH90154)
		-
		C++17 Feature Support
		^^^^^^^^^^^^^^^^^^^^^
		-- The implementation of the relaxed template template argument matching rules is
		- more complete and reliable, and should provide more accurate diagnostics.
		Resolutions to C++ Defect Reports
		^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
		-- Allow calling initializer list constructors from initializer lists with
		- a single element of the same type instead of always copying.
		- (`CWG2137: List-initialization from object of same type <https://cplusplus.github.io/CWG/issues/2137.html>`)
		-
		-- Speculative resolution for CWG2311 implemented so that the implementation of CWG2137 doesn't remove
		- previous cases where guaranteed copy elision was done. Given a prvalue ``e`` of class type
		- ``T``, ``T{e}`` will try to resolve an initializer list constructor and will use it if successful.
		- Otherwise, if there is no initializer list constructor, the copy will be elided as if it was ``T(e)``.
		- (`CWG2311: Missed case for guaranteed copy elision <https://cplusplus.github.io/CWG/issues/2311.html>`)
		-
		-- Casts from a bit-field to an integral type is now not considered narrowing if the
		- width of the bit-field means that all potential values are in the range
		- of the target type, even if the type of the bit-field is larger.
		- (`CWG2627: Bit-fields and narrowing conversions <https://cplusplus.github.io/CWG/issues/2627.html>`_)
		-
		-- ``nullptr`` is now promoted to ``void*`` when passed to a C-style variadic function.
		- (`CWG722: Can nullptr be passed to an ellipsis? <https://cplusplus.github.io/CWG/issues/722.html>`_)
		-
		-- Allow ``void{}`` as a prvalue of type ``void``.
		- (`CWG2351: void{} <https://cplusplus.github.io/CWG/issues/2351.html>`_).
		-
		-- Clang now has improved resolution to CWG2398, allowing class templates to have
		- default arguments deduced when partial ordering, and better backwards compatibility
		- in overload resolution.
		-
		-- Clang now allows comparing unequal object pointers that have been cast to ``void *``
		- in constant expressions. These comparisons always worked in non-constant expressions.
		- (`CWG2749: Treatment of "pointer to void" for relational comparisons <https://cplusplus.github.io/CWG/issues/2749.html>`_).
		-
		-- Reject explicit object parameters with type ``void`` (``this void``).
		- (`CWG2915: Explicit object parameters of type void <https://cplusplus.github.io/CWG/issues/2915.html>`_).
		-
		-- Clang now allows trailing requires clause on explicit deduction guides.
		- (`CWG2707: Deduction guides cannot have a trailing requires-clause <https://cplusplus.github.io/CWG/issues/2707.html>`_).
		-
		-- Respect constructor constraints during CTAD.
		- (`CWG2628: Implicit deduction guides should propagate constraints <https://cplusplus.github.io/CWG/issues/2628.html>`_).
		-
		-- Clang now diagnoses a space in the first production of a ``literal-operator-id``
		- by default.
		- (`CWG2521: User-defined literals and reserved identifiers <https://cplusplus.github.io/CWG/issues/2521.html>`_).
		-
		-- Fix name lookup for a dependent base class that is the current instantiation.
		- (`CWG591: When a dependent base class is the current instantiation <https://cplusplus.github.io/CWG/issues/591.html>`_).
		-
		-- Clang now allows calling explicit object member functions directly with prvalues
		- instead of always materializing a temporary, meaning by-value explicit object parameters
		- do not need to move from a temporary.
		- (`CWG2813: Class member access with prvalues <https://cplusplus.github.io/CWG/issues/2813.html>`_).
		+- The flag `-frelaxed-template-template-args`
		+ and its negation have been removed, having been deprecated since the previous
		+ two releases. The improvements to template template parameter matching implemented
		+ in the previous release, as described in P3310 and P3579, made this flag unnecessary.
		C Language Changes
		------------------
		-- Extend clang's ``<limits.h>`` to define ``LONG_LONG_*`` macros for Android's bionic.
		-
		C2y Feature Support
		^^^^^^^^^^^^^^^^^^^
		-- Updated conformance for `N3298 <https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3298.htm>`_
		- which adds the ``i`` and ``j`` suffixes for the creation of a ``_Complex``
		- constant value. Clang has always supported these suffixes as a GNU extension,
		- so ``-Wgnu-imaginary-constant`` no longer has effect in C modes, as this is
		- now a C2y extension in C. ``-Wgnu-imaginary-constant`` still applies in C++
		- modes.
		-
		-- Clang updated conformance for `N3370 <https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3370.htm>`_
		- case range expressions. This feature was previously supported by Clang as a
		- GNU extension, so ``-Wgnu-case-range`` no longer has effect in C modes, as
		- this is now a C2y extension in C. ``-Wgnu-case-range`` still applies in C++
		- modes.
		-
		-- Clang implemented support for `N3344 <https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3344.pdf>`_
		- which disallows a ``void`` parameter from having a qualifier or storage class
		- specifier. Note that ``register void`` was previously accepted in all C
		- language modes but is now rejected (all of the other qualifiers and storage
		- class specifiers were previously rejected).
		-
		-- Updated conformance for `N3364 <https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3364.pdf>`_
		- on floating-point translation-time initialization with signaling NaN. This
		- paper adopts Clang's existing practice, so there were no changes to compiler
		- behavior.
		-
		-- Implemented support for `N3341 <https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3341.pdf>`_
		- which makes empty structure and union objects implementation-defined in C.
		- ``-Wgnu-empty-struct`` will be emitted in C23 and earlier modes because the
		- behavior is a conforming GNU extension in those modes, but will no longer
		- have an effect in C2y mode.
		-
		-- Updated conformance for `N3342 <https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3342.pdf>`_
		- which made qualified function types implementation-defined rather than
		- undefined. Clang has always accepted ``const`` and ``volatile`` qualified
		- function types by ignoring the qualifiers.
		-
		-- Updated conformance for `N3346 <https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3346.pdf>`_
		- which changes some undefined behavior around initialization to instead be
		- constraint violations. This paper adopts Clang's existing practice, so there
		- were no changes to compiler behavior.
		-
		C23 Feature Support
		^^^^^^^^^^^^^^^^^^^
		-- Clang now supports `N3029 <https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3029.htm>`_ Improved Normal Enumerations.
		-- Clang now officially supports `N3030 <https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3030.htm>`_ Enhancements to Enumerations. Clang already supported it as an extension, so there were no changes to compiler behavior.
		-- Fixed the value of ``BOOL_WIDTH`` in ``<limits.h>`` to return ``1``
		- explicitly, as mandated by the standard. Fixes #GH117348
		-
		Non-comprehensive list of changes in this release
		-------------------------------------------------
		-- The floating point comparison builtins (``__builtin_isgreater``,
		- ``__builtin_isgreaterequal``, ``__builtin_isless``, etc.) and
		- ``__builtin_signbit`` can now be used in constant expressions.
		-- Plugins can now define custom attributes that apply to statements
		- as well as declarations.
		-- ``__builtin_abs`` function can now be used in constant expressions.
		-
		-- The new builtin ``__builtin_counted_by_ref`` was added. In contexts where the
		- programmer needs access to the ``counted_by`` attribute's field, but it's not
		- available --- e.g. in macros. For instance, it can be used to automatically
		- set the counter during allocation in the Linux kernel:
		-
		- .. code-block:: c
		-
		- /* A simplified version of Linux allocation macros */
		- #define alloc(PTR, FAM, COUNT) ({ \
		- sizeof_t __ignored_assignment; \
		- typeof(P) __p; \
		- size_t __size = sizeof(*P) + sizeof(*P->FAM) * COUNT; \
		- __p = malloc(__size); \
		- *_Generic( \
		- __builtin_counted_by_ref(__p->FAM), \
		- void *: &__ignored_assignment, \
		- default: __builtin_counted_by_ref(__p->FAM)) = COUNT; \
		- __p; \
		- })
		-
		- The flexible array member (FAM) can now be accessed immediately without causing
		- issues with the sanitizer because the counter is automatically set.
		-
		-- The following builtins can now be used in constant expressions: ``__builtin_reduce_add``,
		- ``__builtin_reduce_mul``, ``__builtin_reduce_and``, ``__builtin_reduce_or``,
		- ``__builtin_reduce_xor``, ``__builtin_elementwise_popcount``,
		- ``__builtin_elementwise_bitreverse``, ``__builtin_elementwise_add_sat``,
		- ``__builtin_elementwise_sub_sat``, ``__builtin_reduce_min`` (For integral element type),
		- ``__builtin_reduce_max`` (For integral element type).
		-
		-- The builtin macros ``__INT8_C``, ``__INT16_C``, ``__INT32_C``, ``__INT64_C``,
		- ``__INTMAX_C``, ``__UINT8_C``, ``__UINT16_C``, ``__UINT32_C``, ``__UINT64_C``
		- and ``__UINTMAX_C`` have been introduced to ease the implementaton of section
		- 7.18.4 of ISO/IEC 9899:1999. These macros are also defined by GCC and should
		- be used instead of others that expand and paste the suffixes provided by
		- ``__INT8_C_SUFFIX__``, ``__INT16_C_SUFFIX__``, ``__INT32_C_SUFFIX__``,
		- ``__INT64_C_SUFFIX__``, ``__INTMAX_C_SUFFIX__``, ``__UINT8_C_SUFFIX__``,
		- ``__UINT16_C_SUFFIX__``, ``__UINT32_C_SUFFIX__``, ``__UINT64_C_SUFFIX__`` and
		- ``__UINTMAX_C_SUFFIX__``. Pasting suffixes after the expansion of their
		- respective macros is unsafe, as users can define the suffixes as macros.
		-
		-- Clang now rejects ``_BitInt`` matrix element types if the bit width is less than ``CHAR_WIDTH`` or
		- not a power of two, matching preexisting behaviour for vector types.
		-
		-- Matrix types (a Clang extension) can now be used in pseudo-destructor expressions,
		- which allows them to be stored in STL containers.
		-
		-- In the ``-ftime-report`` output, the new "Clang time report" group replaces
		- the old "Clang front-end time report" and includes "Front end", "LLVM IR
		- generation", "Optimizer", and "Machine code generation".
		-
		New Compiler Flags
		------------------
		-- The ``-fc++-static-destructors={all,thread-local,none}`` flag was
		- added to control which C++ variables have static destructors
		- registered: all (the default) does so for all variables, thread-local
		- only for thread-local variables, and none (which corresponds to the
		- existing ``-fno-c++-static-destructors`` flag) skips all static
		- destructors registration.
		-
		-- The ``-Warray-compare`` warning has been added to warn about array comparison
		- on versions older than C++20.
		-
		-- The ``-Warray-compare-cxx26`` warning has been added to warn about array comparison
		- starting from C++26, this warning is enabled as an error by default.
		-
		-- clang-cl and clang-dxc now support ``-fdiagnostics-color=[auto|never|always]``
		- in addition to ``-f[no-]color-diagnostics``.
		-
		Deprecated Compiler Flags
		-------------------------
		-- ``-fheinous-gnu-extensions`` is deprecated; it is now equivalent to
		- specifying ``-Wno-error=invalid-gnu-asm-cast`` and may be removed in the
		- future.
		-
		Modified Compiler Flags
		-----------------------
		-- The ``-ffp-model`` option has been updated to enable a more limited set of
		- optimizations when the ``fast`` argument is used and to accept a new argument,
		- ``aggressive``. The behavior of ``-ffp-model=aggressive`` is equivalent
		- to the previous behavior of ``-ffp-model=fast``. The updated
		- ``-ffp-model=fast`` behavior no longer assumes finite math only and uses
		- the ``promoted`` algorithm for complex division when possible rather than the
		- less basic (limited range) algorithm.
		-
		-- The ``-fveclib`` option has been updated to enable ``-fno-math-errno`` for
		- ``-fveclib=ArmPL`` and ``-fveclib=SLEEF``. This gives Clang more opportunities
		- to utilize these vector libraries. The behavior for all other vector function
		- libraries remains unchanged.
		-
		-- The ``-Wnontrivial-memcall`` warning has been added to warn about
		- passing non-trivially-copyable destination parameter to ``memcpy``,
		- ``memset`` and similar functions for which it is a documented undefined
		- behavior. It is implied by ``-Wnontrivial-memaccess``
		-
		-- Added ``-fmodules-reduced-bmi`` flag corresponding to
		- ``-fexperimental-modules-reduced-bmi`` flag. The ``-fmodules-reduced-bmi`` flag
		- is intended to be enabled by default in the future.
		-
		Removed Compiler Flags
		-------------------------
		-- The compiler flag `-Wenum-constexpr-conversion` (and the `Wno-`, `Wno-error-`
		- derivatives) is now removed, since it's no longer possible to suppress the
		- diagnostic (see above). Users can expect an `unknown warning` diagnostic if
		- it's still in use.
		-
		Attribute Changes in Clang
		--------------------------
		-- The ``swift_attr`` can now be applied to types. To make it possible to use imported APIs
		- in Swift safely there has to be a way to annotate individual parameters and result types
		- with relevant attributes that indicate that e.g. a block is called on a particular actor
		- or it accepts a Sendable or global-actor (i.e. ``@MainActor``) isolated parameter.
		-
		- For example:
		-
		- .. code-block:: objc
		-
		- @interface MyService
		- -(void) handle: (void (^ __attribute__((swift_attr("@Sendable"))))(id)) handler;
		- @end
		-
		-- Clang now disallows more than one ``__attribute__((ownership_returns(class, idx)))`` with
		- different class names attached to one function.
		-
		-- Introduced a new format attribute ``__attribute__((format(syslog, 1, 2)))`` from OpenBSD.
		-
		-- The ``hybrid_patchable`` attribute is now supported on ARM64EC targets. It can be used to specify
		- that a function requires an additional x86-64 thunk, which may be patched at runtime.
		-
		-- The attribute ``[[clang::no_specializations]]`` has been added to warn
		- users that a specific template shouldn't be specialized. This is useful for
		- e.g. standard library type traits, where adding a specialization results in
		- undefined behaviour.
		-
		-- ``[[clang::lifetimebound]]`` is now explicitly disallowed on explicit object member functions
		- where they were previously silently ignored.
		-
		-- Clang now automatically adds ``[[clang::lifetimebound]]`` to the parameters of
		- ``std::span, std::string_view`` constructors, this enables Clang to capture
		- more cases where the returned reference outlives the object.
		- (#GH100567)
		-
		-- Clang now correctly diagnoses the use of ``btf_type_tag`` in C++ and ignores
		- it; this attribute is a C-only attribute, and caused crashes with template
		- instantiation by accidentally allowing it in C++ in some circumstances.
		- (#GH106864)
		-
		-- Introduced a new attribute ``[[clang::coro_await_elidable]]`` on coroutine return types
		- to express elideability at call sites where the coroutine is invoked under a safe elide context.
		-
		-- Introduced a new attribute ``[[clang::coro_await_elidable_argument]]`` on function parameters
		- to propagate safe elide context to arguments if such function is also under a safe elide context.
		-
		-- The documentation of the ``[[clang::musttail]]`` attribute was updated to
		- note that the lifetimes of all local variables end before the call. This does
		- not change the behaviour of the compiler, as this was true for previous
		- versions.
		-
		-- Fix a bug where clang doesn't automatically apply the ``[[gsl::Owner]]`` or
		- ``[[gsl::Pointer]]`` to STL explicit template specialization decls. (#GH109442)
		-
		-- Clang now supports ``[[clang::lifetime_capture_by(X)]]``. Similar to lifetimebound, this can be
		- used to specify when a reference to a function parameter is captured by another capturing entity ``X``.
		-
		-- The ``target_version`` attribute is now only supported for AArch64 and RISC-V architectures.
		-
		-- Clang now permits the usage of the placement new operator in ``[[msvc::constexpr]]``
		- context outside of the std namespace. (#GH74924)
		-
		-- Clang now disallows the use of attributes after the namespace name. (#GH121407)
		-
		Improvements to Clang's diagnostics
		-----------------------------------
		-- Some template related diagnostics have been improved.
		-
		- .. code-block:: c++
		-
		- void foo() { template <typename> int i; } // error: templates can only be declared in namespace or class scope
		-
		- struct S {
		- template <typename> int i; // error: non-static data member 'i' cannot be declared as a template
		- };
		-
		-- Clang now has improved diagnostics for functions with explicit 'this' parameters. Fixes #GH97878
		-
		-- Clang now diagnoses dangling references to fields of temporary objects. Fixes #GH81589.
		-
		-- Clang now diagnoses undefined behavior in constant expressions more consistently. This includes invalid shifts, and signed overflow in arithmetic.
		-
		-- -Wdangling-assignment-gsl is enabled by default.
		-- Clang now always preserves the template arguments as written used
		- to specialize template type aliases.
		-
		-- Clang now diagnoses the use of ``main`` in an ``extern`` context as invalid according to [basic.start.main] p3. Fixes #GH101512.
		-
		-- Clang now diagnoses when the result of a [[nodiscard]] function is discarded after being cast in C. Fixes #GH104391.
		-
		-- Clang now properly explains the reason a template template argument failed to
		- match a template template parameter, in terms of the C++17 relaxed matching rules
		- instead of the old ones.
		-
		-- Don't emit duplicated dangling diagnostics. (#GH93386).
		-
		-- Improved diagnostic when trying to befriend a concept. (#GH45182).
		-
		-- Added the ``-Winvalid-gnu-asm-cast`` diagnostic group to control warnings
		- about use of "noop" casts for lvalues (a GNU extension). This diagnostic is
		- a warning which defaults to being an error, is enabled by default, and is
		- also controlled by the now-deprecated ``-fheinous-gnu-extensions`` flag.
		-
		-- Added the ``-Wdecls-in-multiple-modules`` option to assist users to identify
		- multiple declarations in different modules, which is the major reason of the slow
		- compilation speed with modules. This warning is disabled by default and it needs
		- to be explicitly enabled or by ``-Weverything``.
		-
		-- Improved diagnostic when trying to overload a function in an ``extern "C"`` context. (#GH80235)
		-
		-- Clang now respects lifetimebound attribute for the assignment operator parameter. (#GH106372).
		-
		-- The lifetimebound and GSL analysis in clang are coherent, allowing clang to
		- detect more use-after-free bugs. (#GH100549).
		-
		-- Clang now diagnoses dangling cases where a gsl-pointer is constructed from a gsl-owner object inside a container (#GH100384).
		-
		-- Clang now warns for u8 character literals used in C23 with ``-Wpre-c23-compat`` instead of ``-Wpre-c++17-compat``.
		-
		-- Clang now diagnose when importing module implementation partition units in module interface units.
		-
		-- Don't emit bogus dangling diagnostics when ``[[gsl::Owner]]`` and `[[clang::lifetimebound]]` are used together (#GH108272).
		-
		-- Don't emit bogus dignostic about an undefined behavior on ``reinterpret_cast<T>`` for non-instantiated template functions without sufficient knowledge whether it can actually lead to undefined behavior for ``T`` (#GH109430).
		-
		-- The ``-Wreturn-stack-address`` warning now also warns about addresses of
		- local variables passed to function calls using the ``[[clang::musttail]]``
		- attribute.
		-
		-- Clang now diagnoses cases where a dangling ``GSLOwner<GSLPointer>`` object is constructed, e.g. ``std::vector<string_view> v = {std::string()};`` (#GH100526).
		-
		-- Clang now diagnoses when a ``requires`` expression has a local parameter of void type, aligning with the function parameter (#GH109831).
		-
		-- Clang now emits a diagnostic note at the class declaration when the method definition does not match any declaration (#GH110638).
		-
		-- Clang now omits warnings for extra parentheses in fold expressions with single expansion (#GH101863).
		-
		-- The warning for an unsupported type for a named register variable is now phrased ``unsupported type for named register variable``,
		- instead of ``bad type for named register variable``. This makes it clear that the type is not supported at all, rather than being
		- suboptimal in some way the error fails to mention (#GH111550).
		-
		-- Clang now emits a ``-Wdepredcated-literal-operator`` diagnostic, even if the
		- name was a reserved name, which we improperly allowed to suppress the
		- diagnostic.
		-
		-- Clang now diagnoses ``[[deprecated]]`` attribute usage on local variables (#GH90073).
		-
		-- Fix false positives when `[[gsl::Owner/Pointer]]` and `[[clang::lifetimebound]]` are used together.
		-
		-- Improved diagnostic message for ``__builtin_bit_cast`` size mismatch (#GH115870).
		-
		-- Clang now omits shadow warnings for enum constants in separate class scopes (#GH62588).
		-
		-- When diagnosing an unused return value of a type declared ``[[nodiscard]]``, the type
		- itself is now included in the diagnostic.
		-
		-- Clang will now prefer the ``[[nodiscard]]`` declaration on function declarations over ``[[nodiscard]]``
		- declaration on the return type of a function. Previously, when both have a ``[[nodiscard]]`` declaration attached,
		- the one on the return type would be preferred. This may affect the generated warning message:
		-
		- .. code-block:: c++
		-
		- struct [[nodiscard("Reason 1")]] S {};
		- [[nodiscard("Reason 2")]] S getS();
		- void use()
		- {
		- getS(); // Now diagnoses "Reason 2", previously diagnoses "Reason 1"
		- }
		-
		-- Clang now diagnoses ``= delete("reason")`` extension warnings only in pedantic mode rather than on by default. (#GH109311).
		-
		-- Clang now diagnoses missing return value in functions containing ``if consteval`` (#GH116485).
		-
		-- Clang now correctly recognises code after a call to a ``[[noreturn]]`` constructor
		- as unreachable (#GH63009).
		-
		-- Clang now omits shadowing warnings for parameter names in explicit object member functions (#GH95707).
		-
		-- Improved error recovery for function call arguments with trailing commas (#GH100921).
		-
		-- For an rvalue reference bound to a temporary struct with an integer member, Clang will detect constant integer overflow
		- in the initializer for the integer member (#GH46755).
		-
		-- Fixed a false negative ``-Wunused-private-field`` diagnostic when a defaulted comparison operator is defined out of class (#GH116961).
		-
		-- Clang now diagnoses dangling references for C++20's parenthesized aggregate initialization (#101957).
		-
		-- Fixed a bug where Clang would not emit ``-Wunused-private-field`` warnings when an unrelated class
		- defined a defaulted comparison operator (#GH116270).
		-
		- .. code-block:: c++
		-
		- class A {
		- private:
		- int a; // warning: private field 'a' is not used, no diagnostic previously
		- };
		-
		- class C {
		- bool operator==(const C&) = default;
		- };
		-
		-- Clang now emits `-Wdangling-capture` diangostic when a STL container captures a dangling reference.
		-
		- .. code-block:: c++
		-
		- void test() {
		- std::vector<std::string_view> views;
		- views.push_back(std::string("123")); // warning
		- }
		-
		-- Clang now emits a ``-Wtautological-compare`` diagnostic when a check for
		- pointer addition overflow is always true or false, because overflow would
		- be undefined behavior.
		-
		- .. code-block:: c++
		-
		- bool incorrect_overflow_check(const char *ptr, size_t index) {
		- return ptr + index < ptr; // warning
		- }
		-
		-- Clang now emits a ``-Wvarargs`` diagnostic when the second argument
		- to ``va_arg`` is of array type, which is an undefined behavior (#GH119360).
		-
		- .. code-block:: c++
		-
		- void test() {
		- va_list va;
		- va_arg(va, int[10]); // warning
		- }
		-
		-- Fix -Wdangling false positives on conditional operators (#120206).
		-
		-- Fixed a bug where Clang hung on an unsupported optional scope specifier ``::`` when parsing
		- Objective-C. Clang now emits a diagnostic message instead of hanging.
		-
		-- The :doc:`ThreadSafetyAnalysis` now supports passing scoped capabilities into functions:
		- an attribute on the scoped capability parameter indicates both the expected associated capabilities and,
		- like in the case of attributes on the function declaration itself, their state before and after the call.
		-
		- .. code-block:: c++
		-
		- #include "mutex.h"
		-
		- Mutex mu1, mu2;
		- int a GUARDED_BY(mu1);
		-
		- void require(MutexLocker& scope REQUIRES(mu1)) {
		- scope.Unlock();
		- a = 0; // Warning! Requires mu1.
		- scope.Lock();
		- }
		-
		- void testParameter() {
		- MutexLocker scope(&mu1), scope2(&mu2);
		- require(scope2); // Warning! Mutex managed by 'scope2' is 'mu2' instead of 'mu1'
		- require(scope); // OK.
		- scope.Unlock();
		- require(scope); // Warning! Requires mu1.
		- }
		-- Diagnose invalid declarators in the declaration of constructors and destructors (#GH121706).
		-
		-- Fix false positives warning for non-std functions with name `infinity` (#123231).
		-
		-- Clang now emits a ``-Wignored-qualifiers`` diagnostic when a base class includes cv-qualifiers (#GH55474).
		-
		-- Clang now diagnoses the use of attribute names reserved by the C++ standard (#GH92196).
		-
		Improvements to Clang's time-trace
		----------------------------------
		@@ -838,367 +119,61 @@ Improvements to Coverage Mapping
		Bug Fixes in This Version
		-------------------------
		-- Fixed the definition of ``ATOMIC_FLAG_INIT`` in ``<stdatomic.h>`` so it can
		- be used in C++.
		-- Fixed a failed assertion when checking required literal types in C context. (#GH101304).
		-- Fixed a crash when trying to transform a dependent address space type. Fixes #GH101685.
		-- Fixed a crash when diagnosing format strings and encountering an empty
		- delimited escape sequence (e.g., ``"\o{}"``). #GH102218
		-- Fixed a crash using ``__array_rank`` on 64-bit targets. (#GH113044).
		-- The warning emitted for an unsupported register variable type now points to
		- the unsupported type instead of the ``register`` keyword (#GH109776).
		-- Fixed a crash when emit ctor for global variant with flexible array init (#GH113187).
		-- Fixed a crash when GNU statement expression contains invalid statement (#GH113468).
		-- Fixed a crash when passing the variable length array type to ``va_arg`` (#GH119360).
		-- Fixed a failed assertion when using ``__attribute__((noderef))`` on an
		- ``_Atomic``-qualified type (#GH116124).
		-- No longer incorrectly diagnosing use of a deleted destructor when the
		- selected overload of ``operator delete`` for that type is a destroying delete
		- (#GH46818).
		-- No longer return ``false`` for ``noexcept`` expressions involving a
		- ``delete`` which resolves to a destroying delete but the type of the object
		- being deleted has a potentially throwing destructor (#GH118660).
		-
		Bug Fixes to Compiler Builtins
		^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
		-- Fix crash when atomic builtins are called with pointer to zero-size struct (#GH90330)
		-
		-- Clang now allows pointee types of atomic builtin arguments to be complete template types
		- that was not instantiated elsewhere.
		-
		-- ``__noop`` can now be used in a constant expression. (#GH102064)
		-
		-- Fix ``__has_builtin`` incorrectly returning ``false`` for some C++ type traits. (#GH111477)
		-
		-- Fix ``__builtin_source_location`` incorrectly returning wrong column for method chains. (#GH119129)
		-
		Bug Fixes to Attribute Support
		^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
		Bug Fixes to C++ Support
		^^^^^^^^^^^^^^^^^^^^^^^^
		-- Fixed a crash when an expression with a dependent ``__typeof__`` type is used as the operand of a unary operator. (#GH97646)
		-- Fixed incorrect pack expansion of init-capture references in requires expresssions.
		-- Fixed a failed assertion when checking invalid delete operator declaration. (#GH96191)
		-- Fix a crash when checking destructor reference with an invalid initializer. (#GH97230)
		-- Clang now correctly parses potentially declarative nested-name-specifiers in pointer-to-member declarators.
		-- Fix a crash when checking the initializer of an object that was initialized
		- with a string literal. (#GH82167)
		-- Fix a crash when matching template template parameters with templates which have
		- parameters of different class type. (#GH101394)
		-- Clang now correctly recognizes the correct context for parameter
		- substitutions in concepts, so it doesn't incorrectly complain of missing
		- module imports in those situations. (#GH60336)
		-- Fix init-capture packs having a size of one before being instantiated. (#GH63677)
		-- Clang now preserves the unexpanded flag in a lambda transform used for pack expansion. (#GH56852), (#GH85667),
		- (#GH99877), (#GH122417).
		-- Fixed a bug when diagnosing ambiguous explicit specializations of constrained member functions.
		-- Fixed an assertion failure when selecting a function from an overload set that includes a
		- specialization of a conversion function template.
		-- Correctly diagnose attempts to use a concept name in its own definition;
		- A concept name is introduced to its scope sooner to match the C++ standard. (#GH55875)
		-- Properly reject defaulted relational operators with invalid types for explicit object parameters,
		- e.g., ``bool operator==(this int, const Foo&)`` (#GH100329), and rvalue reference parameters.
		-- Properly reject defaulted copy/move assignment operators that have a non-reference explicit object parameter.
		-- Clang now properly handles the order of attributes in `extern` blocks. (#GH101990).
		-- Fixed an assertion failure by preventing null explicit object arguments from being deduced. (#GH102025).
		-- Correctly check constraints of explicit instantiations of member functions. (#GH46029)
		-- When performing partial ordering of function templates, clang now checks that
		- the deduction was consistent. Fixes (#GH18291).
		-- Fixes to several issues in partial ordering of template template parameters, which
		- were documented in the test suite.
		-- Fixed an assertion failure about a constraint of a friend function template references to a value with greater
		- template depth than the friend function template. (#GH98258)
		-- Clang now rebuilds the template parameters of out-of-line declarations and specializations in the context
		- of the current instantiation in all cases.
		-- Fix evaluation of the index of dependent pack indexing expressions/types specifiers (#GH105900)
		-- Correctly handle subexpressions of an immediate invocation in the presence of implicit casts. (#GH105558)
		-- Clang now correctly handles direct-list-initialization of a structured bindings from an array. (#GH31813)
		-- Mangle placeholders for deduced types as a template-prefix, such that mangling
		- of template template parameters uses the correct production. (#GH106182)
		-- Fixed an assertion failure when converting vectors to int/float with invalid expressions. (#GH105486)
		-- Template parameter names are considered in the name lookup of out-of-line class template
		- specialization right before its declaration context. (#GH64082)
		-- Fixed a constraint comparison bug for friend declarations. (#GH78101)
		-- Fix handling of ``_`` as the name of a lambda's init capture variable. (#GH107024)
		-- Fix an issue with dependent source location expressions (#GH106428), (#GH81155), (#GH80210), (#GH85373)
		-- Fixed a bug in the substitution of empty pack indexing types. (#GH105903)
		-- Clang no longer tries to capture non-odr used default arguments of template parameters of generic lambdas (#GH107048)
		-- Fixed a bug where defaulted comparison operators would remove ``const`` from base classes. (#GH102588)
		-- Fix a crash when using ``source_location`` in the trailing return type of a lambda expression. (#GH67134)
		-- A follow-up fix was added for (#GH61460), as the previous fix was not entirely correct. (#GH86361), (#GH112352)
		-- Fixed a crash in the typo correction of an invalid CTAD guide. (#GH107887)
		-- Fixed a crash when clang tries to substitute parameter pack while retaining the parameter
		- pack. (#GH63819), (#GH107560)
		-- Fix a crash when a static assert declaration has an invalid close location. (#GH108687)
		-- Avoided a redundant friend declaration instantiation under a certain ``consteval`` context. (#GH107175)
		-- Fixed an assertion failure in debug mode, and potential crashes in release mode, when
		- diagnosing a failed cast caused indirectly by a failed implicit conversion to the type of the constructor parameter.
		-- Fixed an assertion failure by adjusting integral to boolean vector conversions (#GH108326)
		-- Fixed a crash when mixture of designated and non-designated initializers in union. (#GH113855)
		-- Fixed an issue deducing non-type template arguments of reference type. (#GH73460)
		-- Fixed an issue in constraint evaluation, where type constraints on the lambda expression
		- containing outer unexpanded parameters were not correctly expanded. (#GH101754)
		-- Fixes crashes with function template member specializations, and increases
		- conformance of explicit instantiation behaviour with MSVC. (#GH111266)
		-- Fixed a bug in constraint expression comparison where the ``sizeof...`` expression was not handled properly
		- in certain friend declarations. (#GH93099)
		-- Clang now instantiates the correct lambda call operator when a lambda's class type is
		- merged across modules. (#GH110401)
		-- Fix a crash when parsing a pseudo destructor involving an invalid type. (#GH111460)
		-- Fixed an assertion failure when invoking recovery call expressions with explicit attributes
		- and undeclared templates. (#GH107047), (#GH49093)
		-- Clang no longer crashes when a lambda contains an invalid block declaration that contains an unexpanded
		- parameter pack. (#GH109148)
		-- Fixed overload handling for object parameters with top-level cv-qualifiers in explicit member functions (#GH100394)
		-- Fixed a bug in lambda captures where ``constexpr`` class-type objects were not properly considered ODR-used in
		- certain situations. (#GH47400), (#GH90896)
		-- Fix erroneous templated array size calculation leading to crashes in generated code. (#GH41441)
		-- During the lookup for a base class name, non-type names are ignored. (#GH16855)
		-- Fix a crash when recovering an invalid expression involving an explicit object member conversion operator. (#GH112559)
		-- Clang incorrectly considered a class with an anonymous union member to not be
		- const-default-constructible even if a union member has a default member initializer.
		- (#GH95854).
		-- Fixed an assertion failure when evaluating an invalid expression in an array initializer. (#GH112140)
		-- Fixed an assertion failure in range calculations for conditional throw expressions. (#GH111854)
		-- Clang now correctly ignores previous partial specializations of member templates explicitly specialized for
		- an implicitly instantiated class template specialization. (#GH51051)
		-- Fixed an assertion failure caused by invalid enum forward declarations. (#GH112208)
		-- Name independent data members were not correctly initialized from default member initializers. (#GH114069)
		-- Fixed expression transformation for ``[[assume(...)]]``, allowing using pack indexing expressions within the
		- assumption if they also occur inside of a dependent lambda. (#GH114787)
		-- Lambdas now capture function types without considering top-level const qualifiers. (#GH84961)
		-- Clang now uses valid deduced type locations when diagnosing functions with trailing return type
		- missing placeholder return type. (#GH78694)
		-- Fixed a bug where bounds of partially expanded pack indexing expressions were checked too early. (#GH116105)
		-- Fixed an assertion failure caused by using ``consteval`` in condition in consumed analyses. (#GH117385)
		-- Fixed an assertion failure caused by invalid default argument substitutions in non-defining
		- friend declarations. (#GH113324)
		-- Fix a crash caused by incorrect argument position in merging deduced template arguments. (#GH113659)
		-- Fixed a parser crash when using pack indexing as a nested name specifier. (#GH119072)
		-- Fixed a null pointer dereference issue when heuristically computing ``sizeof...(pack)`` expressions. (#GH81436)
		-- Fixed an assertion failure caused by mangled names with invalid identifiers. (#GH112205)
		-- Fixed an incorrect lambda scope of generic lambdas that caused Clang to crash when computing potential lambda
		- captures at the end of a full expression. (#GH115931)
		-- Clang no longer rejects deleting a pointer of incomplete enumeration type. (#GH99278)
		-- Fixed recognition of ``std::initializer_list`` when it's surrounded with ``extern "C++"`` and exported
		- out of a module (which is the case e.g. in MSVC's implementation of ``std`` module). (#GH118218)
		-- Fixed a pack expansion issue in checking unexpanded parameter sizes. (#GH17042)
		-- Fixed a bug where captured structured bindings were modifiable inside non-mutable lambda (#GH95081)
		-- Passing incomplete types to ``__is_base_of`` and other builtin type traits for which the corresponding
		- standard type trait mandates a complete type is now a hard (non-sfinae-friendly) error
		- (`LWG3929 <https://wg21.link/LWG3929>`__.) (#GH121278)
		-- Clang now identifies unexpanded parameter packs within the type constraint on a non-type template parameter. (#GH88866)
		-- Fixed an issue while resolving type of expression indexing into a pack of values of non-dependent type (#GH121242)
		-- Fixed a crash when __PRETTY_FUNCTION__ or __FUNCSIG__ (clang-cl) appears in the trailing return type of the lambda (#GH121274)
		-- Fixed a crash caused by the incorrect construction of template arguments for CTAD alias guides when type
		- constraints are applied. (#GH122134)
		-- Fixed canonicalization of pack indexing types - Clang did not always recognized identical pack indexing. (#GH123033)
		-- Fixed a nested lambda substitution issue for constraint evaluation. (#GH123441)
		-- Fixed various false diagnostics related to the use of immediate functions. (#GH123472)
		-- Fix immediate escalation not propagating through inherited constructors. (#GH112677)
		-- Fixed assertions or false compiler diagnostics in the case of C++ modules for
		- lambda functions or inline friend functions defined inside templates (#GH122493).
		-- Clang now rejects declaring an alias template with the same name as its template parameter. (#GH123423)
		-- Correctly determine the implicit constexprness of lambdas in dependent contexts. (#GH97958) (#GH114234)
		+- Clang is now better at keeping track of friend function template instance contexts. (#GH55509)
		Bug Fixes to AST Handling
		^^^^^^^^^^^^^^^^^^^^^^^^^
		-- Fixed a crash that occurred when dividing by zero in complex integer division. (#GH55390).
		-- Fixed a bug in ``ASTContext::getRawCommentForAnyRedecl()`` where the function could
		- sometimes incorrectly return null even if a comment was present. (#GH108145)
		-- Clang now correctly parses the argument of the ``relates``, ``related``, ``relatesalso``,
		- and ``relatedalso`` comment commands.
		-- Clang now uses the location of the begin of the member expression for ``CallExpr``
		- involving deduced ``this``. (#GH116928)
		-- Fixed printout of AST that uses pack indexing expression. (#GH116486)
		-
		Miscellaneous Bug Fixes
		^^^^^^^^^^^^^^^^^^^^^^^
		Miscellaneous Clang Crashes Fixed
		^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
		-- Fixed a crash in C due to incorrect lookup that members in nested anonymous struct/union
		- can be found as ordinary identifiers in struct/union definition. (#GH31295)
		-
		-- Fixed a crash caused by long chains of ``sizeof`` and other similar operators
		- that can be followed by a non-parenthesized expression. (#GH45061)
		-
		-- Fixed an crash when compiling ``#pragma STDC FP_CONTRACT DEFAULT`` with
		- ``-ffp-contract=fast-honor-pragmas``. (#GH104830)
		-
		-- Fixed a crash when function has more than 65536 parameters.
		- Now a diagnostic is emitted. (#GH35741)
		-
		-- Fixed ``-ast-dump`` crashes on codes involving ``concept`` with ``-ast-dump-decl-types``. (#GH94928)
		-
		-- Fixed internal assertion firing when a declaration in the implicit global
		- module is found through ADL. (GH#109879)
		-
		-- Fixed a crash when an unscoped enumeration declared by an opaque-enum-declaration within a class template
		- with a dependent underlying type is subject to integral promotion. (#GH117960)
		-
		OpenACC Specific Changes
		------------------------
		Target Specific Changes
		-----------------------
		-- Clang now implements the Solaris-specific mangling of ``std::tm`` as
		- ``tm``, same for ``std::div_t``, ``std::ldiv_t``, and
		- ``std::lconv``, for Solaris ABI compatibility. (#GH33114)
		-
		AMDGPU Support
		^^^^^^^^^^^^^^
		-- Initial support for gfx950
		-
		-- Added headers ``gpuintrin.h`` and ``amdgpuintrin.h`` that contains common
		- definitions for GPU builtin functions. This header can be included for OpenMP,
		- CUDA, HIP, OpenCL, and C/C++.
		-
		NVPTX Support
		^^^^^^^^^^^^^^
		-- Added headers ``gpuintrin.h`` and ``nvptxintrin.h`` that contains common
		- definitions for GPU builtin functions. This header can be included for OpenMP,
		- CUDA, HIP, OpenCL, and C/C++.
		-
		X86 Support
		^^^^^^^^^^^
		-- The MMX vector intrinsic functions from ``*mmintrin.h`` which
		- operate on `__m64` vectors, such as ``_mm_add_pi8``, have been
		- reimplemented to use the SSE2 instruction-set and XMM registers
		- unconditionally. These intrinsics are therefore *no longer
		- supported* if MMX is enabled without SSE2 -- either from targeting
		- CPUs from the Pentium-MMX through the Pentium 3, or explicitly via
		- passing arguments such as ``-mmmx -mno-sse2``. MMX assembly code
		- remains supported without requiring SSE2, including inside
		- inline-assembly.
		-
		-- The compiler builtins such as ``__builtin_ia32_paddb`` which
		- formerly implemented the above MMX intrinsic functions have been
		- removed. Any uses of these removed functions should migrate to the
		- functions defined by the ``*mmintrin.h`` headers. A mapping can be
		- found in the file ``clang/www/builtins.py``.
		-
		-- Support ISA of ``AVX10.2``.
		- * Supported MINMAX intrinsics of ``*_(mask(z)))_minmax(ne)_p[s|d|h|bh]`` and
		- ``*_(mask(z)))_minmax_s[s|d|h]``.
		-
		-- Supported intrinsics for ``SM4 and AVX10.2``.
		- * Supported SM4 intrinsics of ``_mm512_sm4key4_epi32`` and
		- ``_mm512_sm4rnds4_epi32``.
		-
		-- All intrinsics in adcintrin.h can now be used in constant expressions.
		-
		-- All intrinsics in adxintrin.h can now be used in constant expressions.
		-
		-- All intrinsics in lzcntintrin.h can now be used in constant expressions.
		-
		-- All intrinsics in bmiintrin.h can now be used in constant expressions.
		-
		-- All intrinsics in bmi2intrin.h can now be used in constant expressions.
		-
		-- All intrinsics in tbmintrin.h can now be used in constant expressions.
		-
		-- Supported intrinsics for ``MOVRS AND AVX10.2``.
		- * Supported intrinsics of ``_mm(256|512)_(mask(z))_loadrs_epi(8|16|32|64)``.
		-- Support ISA of ``AMX-FP8``.
		-- Support ISA of ``AMX-TRANSPOSE``.
		-- Support ISA of ``AMX-MOVRS``.
		-- Support ISA of ``AMX-AVX512``.
		-- Support ISA of ``AMX-TF32``.
		-- Support ISA of ``MOVRS``.
		-
		-- Supported ``-march/tune=diamondrapids``
		-
		Arm and AArch64 Support
		^^^^^^^^^^^^^^^^^^^^^^^
		-- Implementation of SVE2.1 and SME2.1 in accordance with the Arm C Language
		- Extensions (ACLE) is now available.
		-
		-- In the ARM Target, the frame pointer (FP) of a leaf function can be retained
		- by using the ``-fno-omit-frame-pointer`` option. If you want to eliminate the FP
		- in leaf functions after enabling ``-fno-omit-frame-pointer``, you can do so by adding
		- the ``-momit-leaf-frame-pointer`` option.
		-
		-- SME keyword attributes which apply to function types are now represented in the
		- mangling of the type. This means that ``void foo(void (*f)() __arm_streaming);``
		- now has a different mangling from ``void foo(void (*f)());``.
		-
		-- The ``__arm_agnostic`` keyword attribute was added to let users describe
		- a function that preserves SME state enabled by PSTATE.ZA without having to share
		- this state with its callers and without making the assumption that this state
		- exists.
		-
		-- Support has been added for the following processors (-mcpu identifiers in parenthesis):
		-
		- For AArch64:
		-
		- * FUJITSU-MONAKA (fujitsu-monaka)
		-
		Android Support
		^^^^^^^^^^^^^^^
		Windows Support
		^^^^^^^^^^^^^^^
		-- clang-cl now supports ``/std:c++23preview`` which enables C++23 features.
		-
		-- Clang no longer allows references inside a union when emulating MSVC 1900+ even if `fms-extensions` is enabled.
		- Starting with VS2015, MSVC 1900, this Microsoft extension is no longer allowed and always results in an error.
		- Clang now follows the MSVC behavior in this scenario.
		- When `-fms-compatibility-version=18.00` or prior is set on the command line this Microsoft extension is still
		- allowed as VS2013 and prior allow it.
		-
		-- Clang now supports the ``#pragma clang section`` directive for COFF targets.
		-
		LoongArch Support
		^^^^^^^^^^^^^^^^^
		-- Types of parameters and return value of ``__builtin_lsx_vorn_v`` and ``__builtin_lasx_xvorn_v``
		- are changed from ``signed char`` to ``unsigned char``. (#GH114514)
		-
		-- ``-mrelax`` and ``-mno-relax`` are supported now on LoongArch that can be used
		- to enable / disable the linker relaxation optimization. (#GH123587)
		-
		-- Fine-grained la64v1.1 options are added including ``-m{no-,}frecipe``, ``-m{no-,}lam-bh``,
		- ``-m{no-,}ld-seq-sa``, ``-m{no-,}div32``, ``-m{no-,}lamcas`` and ``-m{no-,}scq``.
		-
		-- Two options ``-m{no-,}annotate-tablejump`` are added to enable / disable
		- annotating table jump instruction to correlate it with the jump table. (#GH102411)
		-
		-- FreeBSD support is added for LoongArch64 and has been tested by building kernel-toolchain. (#GH119191)
		-
		RISC-V Support
		^^^^^^^^^^^^^^
		-- The option ``-mcmodel=large`` for the large code model is supported.
		-- Bump RVV intrinsic to version 1.0, the spec: https://github.com/riscv-non-isa/rvv-intrinsic-doc/releases/tag/v1.0.0-rc4
		-
		CUDA/HIP Language Changes
		^^^^^^^^^^^^^^^^^^^^^^^^^
		-- Fixed a bug about overriding a constexpr pure-virtual member function with a non-constexpr virtual member function which causes compilation failure when including standard C++ header `format`.
		Bulk data, 333 bytes
		CUDA Support
		^^^^^^^^^^^^
		-- Clang now supports CUDA SDK up to 12.6
		-- Added support for sm_100
		-- Added support for `__grid_constant__` attribute.
		-- CUDA now uses the new offloading driver by default. The new driver supports
		- device-side LTO, interoperability with OpenMP and other languages, and native ``-fgpu-rdc``
		- support with static libraries. The old behavior can be returned using the
		- ``--no-offload-new-driver`` flag. The binary format is no longer compatible
		- with the NVIDIA compiler's RDC-mode support. More information can be found at:
		- https://clang.llvm.org/docs/OffloadingDesign.html
		AIX Support
		^^^^^^^^^^^
		@@ -1209,276 +184,58 @@ NetBSD Support
		WebAssembly Support
		^^^^^^^^^^^^^^^^^^^
		-The default target CPU, "generic", now enables the `-mnontrapping-fptoint`
		-and `-mbulk-memory` flags, which correspond to the [Bulk Memory Operations]
		-and [Non-trapping float-to-int Conversions] language features, which are
		-[widely implemented in engines].
		-
		-A new Lime1 target CPU is added, -mcpu=lime1. This CPU follows the definition of
		-the Lime1 CPU [here], and enables -mmultivalue, -mmutable-globals,
		--mcall-indirect-overlong, -msign-ext, -mbulk-memory-opt, -mnontrapping-fptoint,
		-and -mextended-const.
		-
		-[Bulk Memory Operations]: https://github.com/WebAssembly/bulk-memory-operations/blob/master/proposals/bulk-memory-operations/Overview.md
		-[Non-trapping float-to-int Conversions]: https://github.com/WebAssembly/spec/blob/master/proposals/nontrapping-float-to-int-conversion/Overview.md
		-[widely implemented in engines]: https://webassembly.org/features/
		-[here]: https://github.com/WebAssembly/tool-conventions/blob/main/Lime.md#lime1
		-
		AVR Support
		^^^^^^^^^^^
		-- Reject C/C++ compilation for avr1 devices which have no SRAM.
		-
		DWARF Support in Clang
		----------------------
		Floating Point Support in Clang
		-------------------------------
		-- Add ``__builtin_elementwise_atan2`` builtin for floating point types only.
		-
		Fixed Point Support in Clang
		----------------------------
		AST Matchers
		------------
		-- Fixed an issue with the `hasName` and `hasAnyName` matcher when matching
		- inline namespaces with an enclosing namespace of the same name.
		-
		-- Fixed an ordering issue with the `hasOperands` matcher occurring when setting a
		- binding in the first matcher and using it in the second matcher.
		-
		-- Fixed a crash when traverse lambda expr with invalid captures. (#GH106444)
		-
		-- Fixed ``isInstantiated`` and ``isInTemplateInstantiation`` to also match for variable templates. (#GH110666)
		-
		-- Ensure ``hasName`` matches template specializations across inline namespaces,
		- making `matchesNodeFullSlow` and `matchesNodeFullFast` consistent.
		-
		-- Improved the performance of the ``getExpansionLocOfMacro`` by tracking already processed macros during recursion.
		-
		-- Add ``exportDecl`` matcher to match export declaration.
		-
		-- Ensure ``hasType`` and ``hasDeclaration`` match Objective-C interface declarations.
		-
		-- Ensure ``pointee`` matches Objective-C pointer types.
		-
		-- Add ``dependentScopeDeclRefExpr`` matcher to match expressions that refer to dependent scope declarations.
		-
		-- Add ``dependentNameType`` matcher to match a dependent name type.
		-
		-- Add ``dependentTemplateSpecializationType`` matcher to match a dependent template specialization type.
		-
		-- Add ``hasDependentName`` matcher to match the dependent name of a DependentScopeDeclRefExpr or DependentNameType.
		-
		clang-format
		------------
		-- Adds ``BreakBinaryOperations`` option.
		-- Adds ``TemplateNames`` option.
		-- Adds ``AlignFunctionDeclarations`` option to ``AlignConsecutiveDeclarations``.
		-- Adds ``IndentOnly`` suboption to ``ReflowComments`` to fix the indentation of
		- multi-line comments without touching their contents, renames ``false`` to
		- ``Never``, and ``true`` to ``Always``.
		-- Adds ``RemoveEmptyLinesInUnwrappedLines`` option.
		-- Adds ``KeepFormFeed`` option and set it to ``true`` for ``GNU`` style.
		-- Adds ``AllowShortNamespacesOnASingleLine`` option.
		-- Adds ``VariableTemplates`` option.
		-- Adds support for bash globstar in ``.clang-format-ignore``.
		-- Adds ``WrapNamespaceBodyWithEmptyLines`` option.
		-- Adds the ``IndentExportBlock`` option.
		-
		libclang
		--------
		-- Add ``clang_isBeforeInTranslationUnit``. Given two source locations, it determines
		- whether the first one comes strictly before the second in the source code.
		-- Add ``clang_getTypePrettyPrinted``. It allows controlling the PrintingPolicy used
		- to pretty-print a type.
		-- Added ``clang_visitCXXBaseClasses``, which allows visiting the base classes
		- of a class.
		-- Added ``clang_getOffsetOfBase``, which allows computing the offset of a base
		- class in a class's layout.
		-
		Code Completion
		---------------
		-- Use ``HeuristicResolver`` (upstreamed from clangd) to improve code completion results
		- in dependent code
		-
		Static Analyzer
		---------------
		New features
		^^^^^^^^^^^^
		-- Now CSA models `__builtin_*_overflow` functions. (#GH102602)
		-
		-- MallocChecker now checks for ``ownership_returns(class, idx)`` and ``ownership_takes(class, idx)``
		- attributes with class names different from "malloc". Clang static analyzer now reports an error
		- if class of allocation and deallocation function mismatches.
		- `Documentation <https://clang.llvm.org/docs/analyzer/checkers.html#unix-mismatcheddeallocator-c-c>`__.
		-
		-- Function effects, e.g. the ``nonblocking`` and ``nonallocating`` "performance constraint"
		- attributes, are now verified. For example, for functions declared with the ``nonblocking``
		- attribute, the compiler can generate warnings about the use of any language features, or calls to
		- other functions, which may block.
		-
		-- Introduced ``-warning-suppression-mappings`` flag to control diagnostic
		- suppressions per file. See `documentation <https://clang.llvm.org/docs/WarningSuppressionMappings.html>_` for details.
		-
		Crash and bug fixes
		^^^^^^^^^^^^^^^^^^^
		-- In loops where the loop condition is opaque (i.e. the analyzer cannot
		- determine whether it's true or false), the analyzer will no longer assume
		- execution paths that perform more that two iterations. These unjustified
		- assumptions caused false positive reports (e.g. 100+ out-of-bounds reports in
		- the FFMPEG codebase) in loops where the programmer intended only two or three
		- steps but the analyzer wasn't able to understand that the loop is limited.
		-
		Improvements
		^^^^^^^^^^^^
		-- Improved the handling of the ``ownership_returns`` attribute. Now, Clang reports an
		- error if the attribute is attached to a function that returns a non-pointer value.
		- Fixes (#GH99501)
		-
		Moved checkers
		^^^^^^^^^^^^^^
		-- The checker ``alpha.core.IdenticalExpr`` was deleted because it was
		- duplicated in the clang-tidy checkers ``misc-redundant-expression`` and
		- ``bugprone-branch-clone``.
		-
		-- The checker ``alpha.security.MallocOverflow`` was deleted because it was
		- badly implemented and its aggressive logic produced too many false positives.
		- To detect too large arguments passed to malloc, consider using the checker
		- ``alpha.taint.TaintedAlloc``.
		-
		-- The checkers ``alpha.nondeterministic.PointerSorting`` and
		- ``alpha.nondeterministic.PointerIteration`` were moved to a new bugprone
		- checker named ``bugprone-nondeterministic-pointer-iteration-order``. The
		- original checkers were implemented only using AST matching and make more
		- sense as a single clang-tidy check.
		-
		-- The checker ``alpha.unix.Chroot`` was modernized, improved and moved to
		- ``unix.Chroot``. Testing was done on open source projects that use chroot(),
		- and false issues addressed in the improvements based on real use cases. Open
		- source projects used for testing include nsjail, lxroot, dive and ruri.
		- This checker conforms to SEI Cert C recommendation `POS05-C. Limit access to
		- files by creating a jail
		- <https://wiki.sei.cmu.edu/confluence/display/c/POS05-C.+Limit+access+to+files+by+creating+a+jail>`_.
		- Fixes (#GH34697).
		- (#GH117791) [Documentation](https://clang.llvm.org/docs/analyzer/checkers.html#unix-chroot-c).
		-
		.. _release-notes-sanitizers:
		Sanitizers
		----------
		-- Introduced Realtime Sanitizer, activated by using the -fsanitize=realtime
		- flag. This sanitizer detects unsafe system library calls, such as memory
		- allocations and mutex locks. If any such function is called during invocation
		- of a function marked with the ``[[clang::nonblocking]]`` attribute, an error
		- is printed to the console and the process exits non-zero.
		-
		-- Added the ``-fsanitize-undefined-ignore-overflow-pattern`` flag which can be
		- used to disable specific overflow-dependent code patterns. The supported
		- patterns are: ``add-signed-overflow-test``, ``add-unsigned-overflow-test``,
		- ``negated-unsigned-const``, and ``unsigned-post-decr-while``. The sanitizer
		- instrumentation can be toggled off for all available patterns by specifying
		- ``all``. Conversely, you may disable all exclusions with ``none`` which is
		- the default.
		-
		- .. code-block:: c++
		-
		- /// specified with ``-fsanitize-undefined-ignore-overflow-pattern=add-unsigned-overflow-test``
		- int common_overflow_check_pattern(unsigned base, unsigned offset) {
		- if (base + offset < base) { /* ... */ } // The pattern of `a + b < a`, and other re-orderings, won't be instrumented
		- }
		-
		- /// specified with ``-fsanitize-undefined-ignore-overflow-pattern=add-signed-overflow-test``
		- int common_overflow_check_pattern_signed(signed int base, signed int offset) {
		- if (base + offset < base) { /* ... */ } // The pattern of `a + b < a`, and other re-orderings, won't be instrumented
		- }
		-
		- /// specified with ``-fsanitize-undefined-ignore-overflow-pattern=negated-unsigned-const``
		- void negation_overflow() {
		- unsigned long foo = -1UL; // No longer causes a negation overflow warning
		- unsigned long bar = -2UL; // and so on...
		- }
		-
		- /// specified with ``-fsanitize-undefined-ignore-overflow-pattern=unsigned-post-decr-while``
		- void while_post_decrement() {
		- unsigned char count = 16;
		- while (count--) { /* ... */ } // No longer causes unsigned-integer-overflow sanitizer to trip
		- }
		-
		- Many existing projects have a large amount of these code patterns present.
		- This new flag should allow those projects to enable integer sanitizers with
		- less noise.
		-
		-- ``-fsanitize=signed-integer-overflow``, ``-fsanitize=unsigned-integer-overflow``,
		- ``-fsanitize=implicit-signed-integer-truncation``, ``-fsanitize=implicit-unsigned-integer-truncation``,
		- ``-fsanitize=enum`` now properly support the
		- "type" prefix within `Sanitizer Special Case Lists (SSCL)
		- <https://clang.llvm.org/docs/SanitizerSpecialCaseList.html>`_. See that link
		- for examples.
		-
		-- Introduced an experimental Type Sanitizer, activated by using the
		- ``-fsanitize=type`` flag. This sanitizer detects violations of C/C++ type-based
		- aliasing rules.
		-
		-- Implemented ``-f[no-]sanitize-trap=local-bounds``, and ``-f[no-]sanitize-recover=local-bounds``.
		-
		-- ``-fsanitize-merge`` (default) and ``-fno-sanitize-merge`` have been added for
		- fine-grained, unified control of which UBSan checks can potentially be merged
		- by the compiler (for example,
		- ``-fno-sanitize-merge=bool,enum,array-bounds,local-bounds``).
		-
		-- Changed ``-fsanitize=pointer-overflow`` to no longer report ``NULL + 0`` as
		- undefined behavior in C, in line with
		- `N3322 <https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3322.pdf>`_,
		- and matching the previous behavior for C++.
		- ``NULL + non_zero`` continues to be reported as undefined behavior.
		Python Binding Changes
		----------------------
		-- Fixed an issue that led to crashes when calling ``Type.get_exception_specification_kind``.
		-- Added ``Cursor.pretty_printed``, a binding for ``clang_getCursorPrettyPrinted``,
		- and related functions, which allow changing the formatting of pretty-printed code.
		-- Added ``Cursor.is_anonymous_record_decl``, a binding for
		- ``clang_Cursor_isAnonymousRecordDecl``, which allows checking if a
		- declaration is an anonymous union or anonymous struct.
		-- Added ``Type.pretty_printed`, a binding for ``clang_getTypePrettyPrinted``,
		- which allows changing the formatting of pretty-printed types.
		-- Added ``Cursor.is_virtual_base``, a binding for ``clang_isVirtualBase``,
		- which checks whether a base class is virtual.
		-- Added ``Type.get_bases``, a binding for ``clang_visitCXXBaseClasses``, which
		- allows visiting the base classes of a class.
		-- Added ``Cursor.get_base_offsetof``, a binding for ``clang_getOffsetOfBase``,
		- which allows computing the offset of a base class in a class's layout.
		OpenMP Support
		--------------
		-- Added support for 'omp assume' directive.
		-- Added support for 'omp scope' directive.
		-- Added support for allocator-modifier in 'allocate' clause.
		-- Changed the OpenMP DeviceRTL to use 'generic' IR. The
		- ``LIBOMPTARGET_DEVICE_ARCHITECTURES`` CMake argument is now unused and will
		- always build support for AMDGPU and NVPTX targets.
		-- Added support for combined masked constructs 'omp parallel masked taskloop',
		- 'omp parallel masked taskloop simd','omp masked taskloop' and 'omp masked taskloop simd' directive.
		-- Added support for align-modifier in 'allocate' clause.
		Improvements
		^^^^^^^^^^^^
		-- Improve the handling of mapping array-section for struct containing nested structs with user defined mappers
		-
		-- `num_teams` and `thead_limit` now accept multiple expressions when it is used
		- along in ``target teams ompx_bare`` construct. This allows the target region
		- to be launched with multi-dim grid on GPUs.
		Additional Information
		======================

clang/docs/TypeSanitizer.rst

		@@ -0,0 +1,205 @@
		+=============
		+TypeSanitizer
		+=============
		+
		+.. contents::
		+ :local:
		+
		+Introduction
		+============
		+
		+The TypeSanitizer is a detector for strict type aliasing violations. It consists of a compiler
		+instrumentation module and a run-time library. C/C++ has type-based aliasing rules, and LLVM
		+can exploit these for optimizations given the TBAA metadata Clang emits. In general, a pointer
		+of a given type cannot access an object of a different type, with only a few exceptions.
		+
		+These rules aren't always apparent to users, which leads to code that violates these rules
		+(e.g. for type punning). This can lead to optimization passes introducing bugs unless the
		+code is build with ``-fno-strict-aliasing``, sacrificing performance.
		+
		+TypeSanitizer is built to catch when these strict aliasing rules have been violated, helping
		+users find where such bugs originate in their code despite the code looking valid at first glance.
		+
		+As TypeSanitizer is still experimental, it can currently have a large impact on runtime speed,
		+memory use, and code size. It also has a large compile-time overhead. Work is being done to
		+reduce these impacts.
		+
		+The TypeSanitizer Algorithm
		+===========================
		+For each TBAA type-access descriptor, encoded in LLVM IR using TBAA Metadata, the instrumentation
		+pass generates descriptor tales. Thus there is a unique pointer to each type (and access descriptor).
		+These tables are comdat (except for anonymous-namespace types), so the pointer values are unique
		+across the program.
		+
		+The descriptors refer to other descriptors to form a type aliasing tree, like how LLVM's TBAA data
		+does.
		+
		+The runtime uses 8 bytes of shadow memory, the size of the pointer to the type descriptor, for
		+every byte of accessed data in the program. The first byte of a type will have its shadow memory
		+be set to the pointer to its type descriptor. Aside from that, there are some other values it may be.
		+
		+* 0 is used to represent an unknown type
		+* Negative numbers represent an interior byte: A byte inside a type that is not the first one. As an
		+ example, a value of -2 means you are in the third byte of a type.
		+
		+The Instrumentation first checks for an exact match between the type of the current access and the
		+type for that address in the shadow memory. This can quickly be done by checking pointer values. If
		+it matches, it checks the remaining shadow memory of the type to ensure they are the correct negative
		+numbers. If this fails, it calls the "slow path" check. If the exact match fails, we check to see if
		+the value, and the remainder of the shadow bytes, is 0. If they are, we can set the shadow memory to
		+the correct type descriptor pointer for the first byte, and the correct negative numbers for the rest
		+of the type's shadow.
		+
		+If the type in shadow memory is neither an exact match nor 0, we call the slower runtime check. It
		+uses the full TBAA algorithm, just as the compiler does, to determine when two types are permitted to
		+alias.
		+
		+The instrumentation pass inserts calls to the memset intrinsic to set the memory updated by memset,
		+memcpy, and memmove, as well as allocas/byval (and for lifetime.start/end) to reset the shadow memory
		+to reflect that the type is now unknown. The runtime intercepts memset, memcpy, etc. to perform the
		+same function for the library calls.
		+
		+How to build
		+============
		+
		+Build LLVM/Clang with `CMake <https://llvm.org/docs/CMake.html>`_ and enable
		+the ``compiler-rt`` runtime. An example CMake configuration that will allow
		+for the use/testing of TypeSanitizer:
		+
		+.. code-block:: console
		+
		+ $ cmake -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_PROJECTS="clang" -DLLVM_ENABLE_RUNTIMES="compiler-rt" <path to source>/llvm
		+
		+Usage
		+=====
		+
		+Compile and link your program with ``-fsanitize=type`` flag. The
		+TypeSanitizer run-time library should be linked to the final executable, so
		+make sure to use ``clang`` (not ``ld``) for the final link step. To
		+get a reasonable performance add ``-O1`` or higher.
		+TypeSanitizer by default doesn't print the full stack trace in error messages. Use ``TYSAN_OPTIONS=print_stacktrace=1``
		+to print the full trace. To get nicer stack traces in error messages add ``-fno-omit-frame-pointer`` and
		+``-g``. To get perfect stack traces you may need to disable inlining (just use ``-O1``) and tail call elimination
		+(``-fno-optimize-sibling-calls``).
		+
		+.. code-block:: console
		+
		+ % cat example_AliasViolation.c
		+ int main(int argc, char **argv) {
		+ int x = 100;
		+ float *y = (float*)&x;
		+ *y += 2.0f; // Strict aliasing violation
		+ return 0;
		+ }
		+
		+ # Compile and link
		+ % clang++ -g -fsanitize=type example_AliasViolation.cc
		+
		+The program will print an error message to ``stderr`` each time a strict aliasing violation is detected.
		+The program won't terminate, which will allow you to detect many strict aliasing violations in one
		+run.
		+
		+.. code-block:: console
		+
		+ % ./a.out
		+ ==1375532==ERROR: TypeSanitizer: type-aliasing-violation on address 0x7ffeebf1a72c (pc 0x5b3b1145ff41 bp 0x7ffeebf1a660 sp 0x7ffeebf19e08 tid 1375532)
		+ READ of size 4 at 0x7ffeebf1a72c with type float accesses an existing object of type int
		+ #0 0x5b3b1145ff40 in main example_AliasViolation.c:4:10
		+
		+ ==1375532==ERROR: TypeSanitizer: type-aliasing-violation on address 0x7ffeebf1a72c (pc 0x5b3b1146008a bp 0x7ffeebf1a660 sp 0x7ffeebf19e08 tid 1375532)
		+ WRITE of size 4 at 0x7ffeebf1a72c with type float accesses an existing object of type int
		+ #0 0x5b3b11460089 in main example_AliasViolation.c:4:10
		+
		+Error terminology
		+------------------
		+
		+There are some terms that may appear in TypeSanitizer errors that are derived from
		+`TBAA Metadata <https://llvm.org/docs/LangRef.html#tbaa-metadata>`. This section hopes to provide a
		+brief dictionary of these terms.
		+
		+* ``omnipotent char``: This is a special type which can alias with anything. Its name comes from the C/C++
		+ type ``char``.
		+* ``type p[x]``: This signifies pointers to the type. ``x`` is the number of indirections to reach the final value.
		+ As an example, a pointer to a pointer to an integer would be ``type p2 int``.
		+
		+TypeSanitizer is still experimental. User-facing error messages should be improved in the future to remove
		+references to LLVM IR specific terms.
		+
		+Sanitizer features
		+==================
		+
		+``__has_feature(type_sanitizer)``
		+------------------------------------
		+
		+In some cases one may need to execute different code depending on whether
		+TypeSanitizer is enabled.
		+:ref:`\_\_has\_feature <langext-__has_feature-__has_extension>` can be used for
		+this purpose.
		+
		+.. code-block:: c
		+
		+ #if defined(__has_feature)
		+ # if __has_feature(type_sanitizer)
		+ // code that builds only under TypeSanitizer
		+ # endif
		+ #endif
		+
		+``__attribute__((no_sanitize("type")))``
		+-----------------------------------------------
		+
		+Some code you may not want to be instrumented by TypeSanitizer. One may use the
		+function attribute ``no_sanitize("type")`` to disable instrumenting type aliasing.
		+It is possible, depending on what happens in non-instrumented code, that instrumented code
		+emits false-positives/ false-negatives. This attribute may not be supported by other
		+compilers, so we suggest to use it together with ``__has_feature(type_sanitizer)``.
		+
		+``__attribute__((disable_sanitizer_instrumentation))``
		+--------------------------------------------------------
		+
		+The ``disable_sanitizer_instrumentation`` attribute can be applied to functions
		+to prevent all kinds of instrumentation. As a result, it may introduce false
		+positives and incorrect stack traces. Therefore, it should be used with care,
		+and only if absolutely required; for example for certain code that cannot
		+tolerate any instrumentation and resulting side-effects. This attribute
		+overrides ``no_sanitize("type")``.
		+
		+Ignorelist
		+----------
		+
		+TypeSanitizer supports ``src`` and ``fun`` entity types in
		+:doc:`SanitizerSpecialCaseList`, that can be used to suppress aliasing
		+violation reports in the specified source files or functions. Like
		+with other methods of ignoring instrumentation, this can result in false
		+positives/ false-negatives.
		+
		+Limitations
		+-----------
		+
		+* TypeSanitizer uses more real memory than a native run. It uses 8 bytes of
		+ shadow memory for each byte of user memory.
		+* There are transformation passes which run before TypeSanitizer. If these
		+ passes optimize out an aliasing violation, TypeSanitizer cannot catch it.
		+* Currently, all instrumentation is inlined. This can result in a **15x**
		+ (on average) increase in generated file size, and **3x** to **7x** increase
		+ in compile time. In some documented cases this can cause the compiler to hang.
		+ There are plans to improve this in the future.
		+* Codebases that use unions and struct-initialized variables can see incorrect
		+ results, as TypeSanitizer doesn't yet instrument these reliably.
		+* Since Clang & LLVM's TBAA system is used to generate the checks used by the
		+ instrumentation, TypeSanitizer follows Clang & LLVM's rules for type aliasing.
		+ There may be situations where that disagrees with the standard. However this
		+ does at least mean that TypeSanitizer will catch any aliasing violations that
		+ would cause bugs when compiling with Clang & LLVM.
		+* TypeSanitizer cannot currently be run alongside other sanitizers such as
		+ AddressSanitizer, ThreadSanitizer or UndefinedBehaviourSanitizer.
		+
		+Current Status
		+--------------
		+
		+TypeSanitizer is brand new, and still in development. There are some known
		+issues, especially in areas where Clang's emitted TBAA data isn't extensive
		+enough for TypeSanitizer's runtime.
		+
		+We are actively working on enhancing the tool --- stay tuned. Any help,
		+issues, pull requests, ideas, is more than welcome. You can find the
		+`issue tracker here.<https://github.com/llvm/llvm-project/issues?q=is%3Aissue%20state%3Aopen%20TySan%20label%3Acompiler-rt%3Atysan>`

clang/docs/UsersManual.rst

		@@ -2103,7 +2103,10 @@ are listed below.
		``-fsanitize=undefined``: :doc:`UndefinedBehaviorSanitizer`,
		a fast and compatible undefined behavior checker.
		+ - .. _opt_fsanitize_type:
		+ ``-fsanitize=type``: :doc:`TypeSanitizer`, a detector for strict
		+ aliasing violations.
		- ``-fsanitize=dataflow``: :doc:`DataFlowSanitizer`, a general data
		flow analysis.
		- ``-fsanitize=cfi``: :doc:`control flow integrity <ControlFlowIntegrity>`

clang/docs/index.rst

		@@ -35,6 +35,7 @@ Using Clang as a Compiler
		UndefinedBehaviorSanitizer
		DataFlowSanitizer
		LeakSanitizer
		+ TypeSanitizer
		RealtimeSanitizer
		SanitizerCoverage
		SanitizerStats

clang/include/clang-c/Index.h

		@@ -5905,66 +5905,6 @@ CINDEX_LINKAGE const char *clang_EvalResult_getAsStr(CXEvalResult E);
		* Disposes the created Eval memory.
		*/
		CINDEX_LINKAGE void clang_EvalResult_dispose(CXEvalResult E);
		-/**
		- * @}
		- */
		-
		-/** \defgroup CINDEX_REMAPPING Remapping functions
		- *
		- * @{
		- */
		-
		-/**
		- * A remapping of original source files and their translated files.
		- */
		-typedef void *CXRemapping;
		-
		-/**
		- * Retrieve a remapping.
		- *
		- * \param path the path that contains metadata about remappings.
		- *
		- * \returns the requested remapping. This remapping must be freed
		- * via a call to \c clang_remap_dispose(). Can return NULL if an error occurred.
		- */
		-CINDEX_LINKAGE CXRemapping clang_getRemappings(const char *path);
		-
		-/**
		- * Retrieve a remapping.
		- *
		- * \param filePaths pointer to an array of file paths containing remapping info.
		- *
		- * \param numFiles number of file paths.
		- *
		- * \returns the requested remapping. This remapping must be freed
		- * via a call to \c clang_remap_dispose(). Can return NULL if an error occurred.
		- */
		-CINDEX_LINKAGE
		-CXRemapping clang_getRemappingsFromFileList(const char **filePaths,
		- unsigned numFiles);
		-
		-/**
		- * Determine the number of remappings.
		- */
		-CINDEX_LINKAGE unsigned clang_remap_getNumFiles(CXRemapping);
		-
		-/**
		- * Get the original and the associated filename from the remapping.
		- *
		- * \param original If non-NULL, will be set to the original filename.
		- *
		- * \param transformed If non-NULL, will be set to the filename that the original
		- * is associated with.
		- */
		-CINDEX_LINKAGE void clang_remap_getFilenames(CXRemapping, unsigned index,
		- CXString *original,
		- CXString *transformed);
		-
		-/**
		- * Dispose the remapping.
		- */
		-CINDEX_LINKAGE void clang_remap_dispose(CXRemapping);
		-
		/**
		* @}
		*/

clang/include/clang/ARCMigrate/ARCMT.h→/dev/null

		@@ -1,130 +0,0 @@
		-//===-- ARCMT.h - ARC Migration Rewriter ------------------------*- C++ -*-===//
		-//
		-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
		-// See https://llvm.org/LICENSE.txt for license information.
		-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
		-//
		-//===----------------------------------------------------------------------===//
		-
		-#ifndef LLVM_CLANG_ARCMIGRATE_ARCMT_H
		-#define LLVM_CLANG_ARCMIGRATE_ARCMT_H
		-
		-#include "clang/ARCMigrate/FileRemapper.h"
		-#include "clang/Basic/SourceLocation.h"
		-#include "clang/Frontend/CompilerInvocation.h"
		-
		-namespace clang {
		- class ASTContext;
		- class DiagnosticConsumer;
		- class PCHContainerOperations;
		-
		-namespace arcmt {
		- class MigrationPass;
		-
		-/// Creates an AST with the provided CompilerInvocation but with these
		-/// changes:
		-/// -if a PCH/PTH is set, the original header is used instead
		-/// -Automatic Reference Counting mode is enabled
		-///
		-/// It then checks the AST and produces errors/warning for ARC migration issues
		-/// that the user needs to handle manually.
		-///
		-/// \param emitPremigrationARCErrors if true all ARC errors will get emitted
		-/// even if the migrator can fix them, but the function will still return false
		-/// if all ARC errors can be fixed.
		-///
		-/// \param plistOut if non-empty, it is the file path to store the plist with
		-/// the pre-migration ARC diagnostics.
		-///
		-/// \returns false if no error is produced, true otherwise.
		-bool
		-checkForManualIssues(CompilerInvocation &CI, const FrontendInputFile &Input,
		- std::shared_ptr<PCHContainerOperations> PCHContainerOps,
		- DiagnosticConsumer *DiagClient,
		- bool emitPremigrationARCErrors = false,
		- StringRef plistOut = StringRef());
		-
		-/// Works similar to checkForManualIssues but instead of checking, it
		-/// applies automatic modifications to source files to conform to ARC.
		-///
		-/// \returns false if no error is produced, true otherwise.
		-bool
		-applyTransformations(CompilerInvocation &origCI,
		- const FrontendInputFile &Input,
		- std::shared_ptr<PCHContainerOperations> PCHContainerOps,
		- DiagnosticConsumer *DiagClient);
		-
		-/// Applies automatic modifications and produces temporary files
		-/// and metadata into the \p outputDir path.
		-///
		-/// \param emitPremigrationARCErrors if true all ARC errors will get emitted
		-/// even if the migrator can fix them, but the function will still return false
		-/// if all ARC errors can be fixed.
		-///
		-/// \param plistOut if non-empty, it is the file path to store the plist with
		-/// the pre-migration ARC diagnostics.
		-///
		-/// \returns false if no error is produced, true otherwise.
		-bool migrateWithTemporaryFiles(
		- CompilerInvocation &origCI, const FrontendInputFile &Input,
		- std::shared_ptr<PCHContainerOperations> PCHContainerOps,
		- DiagnosticConsumer *DiagClient, StringRef outputDir,
		- bool emitPremigrationARCErrors, StringRef plistOut);
		-
		-/// Get the set of file remappings from the \p outputDir path that
		-/// migrateWithTemporaryFiles produced.
		-///
		-/// \returns false if no error is produced, true otherwise.
		-bool getFileRemappings(std::vector<std::pair<std::string,std::string> > &remap,
		- StringRef outputDir,
		- DiagnosticConsumer *DiagClient);
		-
		-/// Get the set of file remappings from a list of files with remapping
		-/// info.
		-///
		-/// \returns false if no error is produced, true otherwise.
		-bool getFileRemappingsFromFileList(
		- std::vector<std::pair<std::string,std::string> > &remap,
		- ArrayRef<StringRef> remapFiles,
		- DiagnosticConsumer *DiagClient);
		-
		-typedef void (*TransformFn)(MigrationPass &pass);
		-
		-std::vector<TransformFn> getAllTransformations(LangOptions::GCMode OrigGCMode,
		- bool NoFinalizeRemoval);
		-
		-class MigrationProcess {
		- CompilerInvocation OrigCI;
		- std::shared_ptr<PCHContainerOperations> PCHContainerOps;
		- DiagnosticConsumer *DiagClient;
		- FileRemapper Remapper;
		-
		-public:
		- bool HadARCErrors;
		-
		- MigrationProcess(CompilerInvocation &CI,
		- std::shared_ptr<PCHContainerOperations> PCHContainerOps,
		- DiagnosticConsumer *diagClient,
		- StringRef outputDir = StringRef());
		-
		- class RewriteListener {
		- public:
		- virtual ~RewriteListener();
		-
		- virtual void start(ASTContext &Ctx) { }
		- virtual void finish() { }
		-
		- virtual void insert(SourceLocation loc, StringRef text) { }
		- virtual void remove(CharSourceRange range) { }
		- };
		-
		- bool applyTransform(TransformFn trans, RewriteListener *listener = nullptr);
		-
		- FileRemapper &getRemapper() { return Remapper; }
		-};
		-
		-} // end namespace arcmt
		-
		-} // end namespace clang
		-
		-#endif

clang/include/clang/ARCMigrate/ARCMTActions.h→/dev/null

		@@ -1,76 +0,0 @@
		-//===--- ARCMTActions.h - ARC Migrate Tool Frontend Actions -----*- C++ -*-===//
		-//
		-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
		-// See https://llvm.org/LICENSE.txt for license information.
		-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
		-//
		-//===----------------------------------------------------------------------===//
		-
		-#ifndef LLVM_CLANG_ARCMIGRATE_ARCMTACTIONS_H
		-#define LLVM_CLANG_ARCMIGRATE_ARCMTACTIONS_H
		-
		-#include "clang/ARCMigrate/FileRemapper.h"
		-#include "clang/Frontend/FrontendAction.h"
		-#include <memory>
		-
		-namespace clang {
		-namespace arcmt {
		-
		-class CheckAction : public WrapperFrontendAction {
		-protected:
		- bool BeginInvocation(CompilerInstance &CI) override;
		-
		-public:
		- CheckAction(std::unique_ptr<FrontendAction> WrappedAction);
		-};
		-
		-class ModifyAction : public WrapperFrontendAction {
		-protected:
		- bool BeginInvocation(CompilerInstance &CI) override;
		-
		-public:
		- ModifyAction(std::unique_ptr<FrontendAction> WrappedAction);
		-};
		-
		-class MigrateSourceAction : public ASTFrontendAction {
		- FileRemapper Remapper;
		-protected:
		- bool BeginInvocation(CompilerInstance &CI) override;
		- std::unique_ptr<ASTConsumer> CreateASTConsumer(CompilerInstance &CI,
		- StringRef InFile) override;
		-};
		-
		-class MigrateAction : public WrapperFrontendAction {
		- std::string MigrateDir;
		- std::string PlistOut;
		- bool EmitPremigrationARCErrors;
		-protected:
		- bool BeginInvocation(CompilerInstance &CI) override;
		-
		-public:
		- MigrateAction(std::unique_ptr<FrontendAction> WrappedAction,
		- StringRef migrateDir,
		- StringRef plistOut,
		- bool emitPremigrationARCErrors);
		-};
		-
		-/// Migrates to modern ObjC syntax.
		-class ObjCMigrateAction : public WrapperFrontendAction {
		- std::string MigrateDir;
		- unsigned ObjCMigAction;
		- FileRemapper Remapper;
		- CompilerInstance *CompInst;
		-public:
		- ObjCMigrateAction(std::unique_ptr<FrontendAction> WrappedAction,
		- StringRef migrateDir, unsigned migrateAction);
		-
		-protected:
		- std::unique_ptr<ASTConsumer> CreateASTConsumer(CompilerInstance &CI,
		- StringRef InFile) override;
		- bool BeginInvocation(CompilerInstance &CI) override;
		-};
		-
		-}
		-}
		-
		-#endif

clang/include/clang/ARCMigrate/FileRemapper.h→/dev/null

		@@ -1,84 +0,0 @@
		-//===-- FileRemapper.h - File Remapping Helper ------------------*- C++ -*-===//
		-//
		-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
		-// See https://llvm.org/LICENSE.txt for license information.
		-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
		-//
		-//===----------------------------------------------------------------------===//
		-
		-#ifndef LLVM_CLANG_ARCMIGRATE_FILEREMAPPER_H
		-#define LLVM_CLANG_ARCMIGRATE_FILEREMAPPER_H
		-
		-#include "clang/Basic/FileEntry.h"
		-#include "clang/Basic/LLVM.h"
		-#include "llvm/ADT/DenseMap.h"
		-#include "llvm/ADT/STLExtras.h"
		-#include "llvm/ADT/StringRef.h"
		-#include <memory>
		-#include <variant>
		-
		-namespace llvm {
		- class MemoryBuffer;
		- class MemoryBufferRef;
		-}
		-
		-namespace clang {
		- class FileManager;
		- class DiagnosticsEngine;
		- class PreprocessorOptions;
		-
		-namespace arcmt {
		-
		-class FileRemapper {
		- // FIXME: Reuse the same FileManager for multiple ASTContexts.
		- std::unique_ptr<FileManager> FileMgr;
		-
		- using Target = std::variant<FileEntryRef, llvm::MemoryBuffer *>;
		- using MappingsTy = llvm::DenseMap<FileEntryRef, Target>;
		- MappingsTy FromToMappings;
		-
		- llvm::DenseMap<const FileEntry *, FileEntryRef> ToFromMappings;
		-
		-public:
		- FileRemapper();
		- ~FileRemapper();
		-
		- bool initFromDisk(StringRef outputDir, DiagnosticsEngine &Diag,
		- bool ignoreIfFilesChanged);
		- bool initFromFile(StringRef filePath, DiagnosticsEngine &Diag,
		- bool ignoreIfFilesChanged);
		- bool flushToDisk(StringRef outputDir, DiagnosticsEngine &Diag);
		- bool flushToFile(StringRef outputPath, DiagnosticsEngine &Diag);
		-
		- bool overwriteOriginal(DiagnosticsEngine &Diag,
		- StringRef outputDir = StringRef());
		-
		- void remap(StringRef filePath, std::unique_ptr<llvm::MemoryBuffer> memBuf);
		-
		- void applyMappings(PreprocessorOptions &PPOpts) const;
		-
		- /// Iterate through all the mappings.
		- void forEachMapping(
		- llvm::function_ref<void(StringRef, StringRef)> CaptureFile,
		- llvm::function_ref<void(StringRef, const llvm::MemoryBufferRef &)>
		- CaptureBuffer) const;
		-
		- void clear(StringRef outputDir = StringRef());
		-
		-private:
		- void remap(FileEntryRef file, std::unique_ptr<llvm::MemoryBuffer> memBuf);
		- void remap(FileEntryRef file, FileEntryRef newfile);
		-
		- OptionalFileEntryRef getOriginalFile(StringRef filePath);
		- void resetTarget(Target &targ);
		-
		- bool report(const Twine &err, DiagnosticsEngine &Diag);
		-
		- std::string getRemapInfoFile(StringRef outputDir);
		-};
		-
		-} // end namespace arcmt
		-
		-} // end namespace clang
		-
		-#endif

clang/include/clang/AST/ASTLambda.h

		@@ -17,6 +17,7 @@
		#include "clang/AST/DeclCXX.h"
		#include "clang/AST/DeclTemplate.h"
		+#include "llvm/Support/Casting.h"
		namespace clang {
		inline StringRef getLambdaStaticInvokerName() {
		@@ -35,6 +36,12 @@ inline bool isLambdaCallOperator(const DeclContext *DC) {
		return isLambdaCallOperator(cast<CXXMethodDecl>(DC));
		}
		+inline bool isLambdaMethod(const DeclContext *DC) {
		+ if (const auto *MD = dyn_cast_if_present<CXXMethodDecl>(DC))
		+ return MD->getParent()->isLambda();
		+ return false;
		+}
		+
		inline bool isLambdaCallWithExplicitObjectParameter(const DeclContext *DC) {
		return isLambdaCallOperator(DC) &&
		cast<CXXMethodDecl>(DC)->isExplicitObjectMemberFunction();

clang/include/clang/AST/Decl.h

		@@ -698,6 +698,10 @@ public:
		return const_cast<ValueDecl *>(this)->getPotentiallyDecomposedVarDecl();
		}
		+ /// Determine whether this value is actually a function parameter pack,
		+ /// init-capture pack, or structured binding pack
		+ bool isParameterPack() const;
		+
		// Implement isa/cast/dyncast/etc.
		static bool classof(const Decl *D) { return classofKind(D->getKind()); }
		static bool classofKind(Kind K) { return K >= firstValue && K <= lastValue; }
		@@ -1527,10 +1531,6 @@ public:
		NonParmVarDeclBits.IsInitCapture = IC;
		}
		- /// Determine whether this variable is actually a function parameter pack or
		- /// init-capture pack.
		- bool isParameterPack() const;
		-
		/// Whether this local extern variable declaration's previous declaration
		/// was declared in the same block scope. Only correct in C++.
		bool isPreviousDeclInSameBlockScope() const {
		@@ -2298,6 +2298,13 @@ public:
		FunctionDeclBits.IsLateTemplateParsed = ILT;
		}
		+ bool isInstantiatedFromMemberTemplate() const {
		+ return FunctionDeclBits.IsInstantiatedFromMemberTemplate;
		+ }
		+ void setInstantiatedFromMemberTemplate(bool Val = true) {
		+ FunctionDeclBits.IsInstantiatedFromMemberTemplate = Val;
		+ }
		+
		/// Whether this function is "trivial" in some specialized C++ senses.
		/// Can only be true for default constructors, copy constructors,
		/// copy assignment operators, and destructors. Not meaningful until
		@@ -5139,6 +5146,12 @@ static constexpr StringRef getOpenMPVariantManglingSeparatorStr() {
		bool IsArmStreamingFunction(const FunctionDecl *FD,
		bool IncludeLocallyStreaming);
		+/// Returns whether the given FunctionDecl has Arm ZA state.
		+bool hasArmZAState(const FunctionDecl *FD);
		+
		+/// Returns whether the given FunctionDecl has Arm ZT0 state.
		+bool hasArmZT0State(const FunctionDecl *FD);
		+
		} // namespace clang
		#endif // LLVM_CLANG_AST_DECL_H

clang/include/clang/AST/DeclBase.h

		@@ -1777,6 +1777,8 @@ protected:
		uint64_t HasImplicitReturnZero : 1;
		LLVM_PREFERRED_TYPE(bool)
		uint64_t IsLateTemplateParsed : 1;
		+ LLVM_PREFERRED_TYPE(bool)
		+ uint64_t IsInstantiatedFromMemberTemplate : 1;
		/// Kind of contexpr specifier as defined by ConstexprSpecKind.
		LLVM_PREFERRED_TYPE(ConstexprSpecKind)
		@@ -1827,7 +1829,7 @@ protected:
		};
		/// Number of inherited and non-inherited bits in FunctionDeclBitfields.
		- enum { NumFunctionDeclBits = NumDeclContextBits + 31 };
		+ enum { NumFunctionDeclBits = NumDeclContextBits + 32 };
		/// Stores the bits used by CXXConstructorDecl. If modified
		/// NumCXXConstructorDeclBits and the accessor
		@@ -1838,12 +1840,12 @@ protected:
		LLVM_PREFERRED_TYPE(FunctionDeclBitfields)
		uint64_t : NumFunctionDeclBits;
		- /// 20 bits to fit in the remaining available space.
		+ /// 19 bits to fit in the remaining available space.
		/// Note that this makes CXXConstructorDeclBitfields take
		/// exactly 64 bits and thus the width of NumCtorInitializers
		/// will need to be shrunk if some bit is added to NumDeclContextBitfields,
		/// NumFunctionDeclBitfields or CXXConstructorDeclBitfields.
		- uint64_t NumCtorInitializers : 17;
		+ uint64_t NumCtorInitializers : 16;
		LLVM_PREFERRED_TYPE(bool)
		uint64_t IsInheritingConstructor : 1;
		@@ -1857,7 +1859,7 @@ protected:
		};
		/// Number of inherited and non-inherited bits in CXXConstructorDeclBitfields.
		- enum { NumCXXConstructorDeclBits = NumFunctionDeclBits + 20 };
		+ enum { NumCXXConstructorDeclBits = NumFunctionDeclBits + 19 };
		/// Stores the bits used by ObjCMethodDecl.
		/// If modified NumObjCMethodDeclBits and the accessor

clang/include/clang/AST/DeclCXX.h

		@@ -1967,17 +1967,29 @@ public:
		class CXXDeductionGuideDecl : public FunctionDecl {
		void anchor() override;
		+public:
		+ // Represents the relationship between this deduction guide and the
		+ // deduction guide that it was generated from (or lack thereof).
		+ // See the SourceDeductionGuide member for more details.
		+ enum class SourceDeductionGuideKind : uint8_t {
		+ None,
		+ Alias,
		+ };
		+
		private:
		CXXDeductionGuideDecl(ASTContext &C, DeclContext *DC, SourceLocation StartLoc,
		ExplicitSpecifier ES,
		const DeclarationNameInfo &NameInfo, QualType T,
		TypeSourceInfo *TInfo, SourceLocation EndLocation,
		CXXConstructorDecl *Ctor, DeductionCandidate Kind,
		- Expr *TrailingRequiresClause)
		+ Expr *TrailingRequiresClause,
		+ const CXXDeductionGuideDecl *GeneratedFrom,
		+ SourceDeductionGuideKind SourceKind)
		: FunctionDecl(CXXDeductionGuide, C, DC, StartLoc, NameInfo, T, TInfo,
		SC_None, false, false, ConstexprSpecKind::Unspecified,
		TrailingRequiresClause),
		- Ctor(Ctor), ExplicitSpec(ES) {
		+ Ctor(Ctor), ExplicitSpec(ES),
		+ SourceDeductionGuide(GeneratedFrom, SourceKind) {
		if (EndLocation.isValid())
		setRangeEnd(EndLocation);
		setDeductionCandidateKind(Kind);
		@@ -1985,6 +1997,12 @@ private:
		CXXConstructorDecl *Ctor;
		ExplicitSpecifier ExplicitSpec;
		+ // The deduction guide, if any, that this deduction guide was generated from,
		+ // in the case of alias template deduction. The SourceDeductionGuideKind
		+ // member indicates which of these sources applies, or is None otherwise.
		+ llvm::PointerIntPair<const CXXDeductionGuideDecl *, 2,
		+ SourceDeductionGuideKind>
		+ SourceDeductionGuide;
		void setExplicitSpecifier(ExplicitSpecifier ES) { ExplicitSpec = ES; }
		public:
		@@ -1997,7 +2015,9 @@ public:
		TypeSourceInfo *TInfo, SourceLocation EndLocation,
		CXXConstructorDecl *Ctor = nullptr,
		DeductionCandidate Kind = DeductionCandidate::Normal,
		- Expr *TrailingRequiresClause = nullptr);
		+ Expr *TrailingRequiresClause = nullptr,
		+ const CXXDeductionGuideDecl *SourceDG = nullptr,
		+ SourceDeductionGuideKind SK = SourceDeductionGuideKind::None);
		static CXXDeductionGuideDecl *CreateDeserialized(ASTContext &C,
		GlobalDeclID ID);
		@@ -2017,6 +2037,25 @@ public:
		/// this is an implicit deduction guide.
		CXXConstructorDecl *getCorrespondingConstructor() const { return Ctor; }
		+ /// Get the deduction guide from which this deduction guide was generated,
		+ /// if it was generated as part of alias template deduction or from an
		+ /// inherited constructor.
		+ const CXXDeductionGuideDecl *getSourceDeductionGuide() const {
		+ return SourceDeductionGuide.getPointer();
		+ }
		+
		+ void setSourceDeductionGuide(CXXDeductionGuideDecl *DG) {
		+ SourceDeductionGuide.setPointer(DG);
		+ }
		+
		+ SourceDeductionGuideKind getSourceDeductionGuideKind() const {
		+ return SourceDeductionGuide.getInt();
		+ }
		+
		+ void setSourceDeductionGuideKind(SourceDeductionGuideKind SK) {
		+ SourceDeductionGuide.setInt(SK);
		+ }
		+
		void setDeductionCandidateKind(DeductionCandidate K) {
		FunctionDeclBits.DeductionCandidateKind = static_cast<unsigned char>(K);
		}
		@@ -4136,8 +4175,9 @@ class BindingDecl : public ValueDecl {
		/// binding).
		Expr *Binding = nullptr;
		- BindingDecl(DeclContext *DC, SourceLocation IdLoc, IdentifierInfo *Id)
		- : ValueDecl(Decl::Binding, DC, IdLoc, Id, QualType()) {}
		+ BindingDecl(DeclContext *DC, SourceLocation IdLoc, IdentifierInfo *Id,
		+ QualType T)
		+ : ValueDecl(Decl::Binding, DC, IdLoc, Id, T) {}
		void anchor() override;
		@@ -4145,7 +4185,8 @@ public:
		friend class ASTDeclReader;
		static BindingDecl *Create(ASTContext &C, DeclContext *DC,
		- SourceLocation IdLoc, IdentifierInfo *Id);
		+ SourceLocation IdLoc, IdentifierInfo *Id,
		+ QualType T);
		static BindingDecl *CreateDeserialized(ASTContext &C, GlobalDeclID ID);
		/// Get the expression to which this declaration is bound. This may be null
		@@ -4153,14 +4194,13 @@ public:
		/// decomposition declaration, and when the initializer is type-dependent.
		Expr *getBinding() const { return Binding; }
		+ // Get the array of Exprs when the binding represents a pack.
		+ llvm::ArrayRef<Expr *> getBindingPackExprs() const;
		+
		/// Get the decomposition declaration that this binding represents a
		/// decomposition of.
		ValueDecl *getDecomposedDecl() const { return Decomp; }
		- /// Get the variable (if any) that holds the value of evaluating the binding.
		- /// Only present for user-defined bindings for tuple-like types.
		- VarDecl *getHoldingVar() const;
		-
		/// Set the binding for this BindingDecl, along with its declared type (which
		/// should be a possibly-cv-qualified form of the type of the binding, or a
		/// reference to such a type).
		@@ -4172,6 +4212,10 @@ public:
		/// Set the decomposed variable for this BindingDecl.
		void setDecomposedDecl(ValueDecl *Decomposed) { Decomp = Decomposed; }
		+ /// Get the variable (if any) that holds the value of evaluating the binding.
		+ /// Only present for user-defined bindings for tuple-like types.
		+ VarDecl *getHoldingVar() const;
		+
		static bool classof(const Decl *D) { return classofKind(D->getKind()); }
		static bool classofKind(Kind K) { return K == Decl::Binding; }
		};
		@@ -4199,8 +4243,16 @@ class DecompositionDecl final
		NumBindings(Bindings.size()) {
		std::uninitialized_copy(Bindings.begin(), Bindings.end(),
		getTrailingObjects<BindingDecl *>());
		- for (auto *B : Bindings)
		+ for (auto *B : Bindings) {
		B->setDecomposedDecl(this);
		+ if (B->isParameterPack() && B->getBinding()) {
		+ for (Expr *E : B->getBindingPackExprs()) {
		+ auto *DRE = cast<DeclRefExpr>(E);
		+ auto *NestedB = cast<BindingDecl>(DRE->getDecl());
		+ NestedB->setDecomposedDecl(this);
		+ }
		+ }
		+ }
		}
		void anchor() override;
		@@ -4218,8 +4270,33 @@ public:
		static DecompositionDecl *CreateDeserialized(ASTContext &C, GlobalDeclID ID,
		unsigned NumBindings);
		- ArrayRef<BindingDecl *> bindings() const {
		- return llvm::ArrayRef(getTrailingObjects<BindingDecl *>(), NumBindings);
		+ // Provide the range of bindings which may have a nested pack.
		+ llvm::ArrayRef<BindingDecl *> bindings() const {
		+ return {getTrailingObjects<BindingDecl *>(), NumBindings};
		+ }
		+
		+ // Provide a flattened range to visit each binding.
		+ auto flat_bindings() const {
		+ llvm::ArrayRef<BindingDecl *> Bindings = bindings();
		+ llvm::ArrayRef<Expr *> PackExprs;
		+
		+ // Split the bindings into subranges split by the pack.
		+ auto S1 = Bindings.take_until(
		+ [](BindingDecl *BD) { return BD->isParameterPack(); });
		+
		+ Bindings = Bindings.drop_front(S1.size());
		+ if (!Bindings.empty()) {
		+ PackExprs = Bindings.front()->getBindingPackExprs();
		+ Bindings = Bindings.drop_front();
		+ }
		+
		+ auto S2 = llvm::map_range(PackExprs, [](Expr *E) {
		+ auto *DRE = cast<DeclRefExpr>(E);
		+ return cast<BindingDecl>(DRE->getDecl());
		+ });
		+
		+ return llvm::concat<BindingDecl *>(std::move(S1), std::move(S2),
		+ std::move(Bindings));
		}
		void printName(raw_ostream &OS, const PrintingPolicy &Policy) const override;

clang/include/clang/AST/DeclTemplate.h

		@@ -1011,6 +1011,15 @@ public:
		return getTemplatedDecl()->isThisDeclarationADefinition();
		}
		+ bool isCompatibleWithDefinition() const {
		+ return getTemplatedDecl()->isInstantiatedFromMemberTemplate() ||
		+ isThisDeclarationADefinition();
		+ }
		+ void setInstantiatedFromMemberTemplate(FunctionTemplateDecl *D) {
		+ getTemplatedDecl()->setInstantiatedFromMemberTemplate();
		+ RedeclarableTemplateDecl::setInstantiatedFromMemberTemplate(D);
		+ }
		+
		/// Return the specialization with the provided arguments if it exists,
		/// otherwise return the insertion point.
		FunctionDecl *findSpecialization(ArrayRef<TemplateArgument> Args,
		@@ -2018,7 +2027,8 @@ public:
		/// Set the template argument list as written in the sources.
		void
		setTemplateArgsAsWritten(const ASTTemplateArgumentListInfo *ArgsWritten) {
		- if (auto *Info = ExplicitInfo.dyn_cast<ExplicitInstantiationInfo *>())
		+ if (auto *Info =
		+ dyn_cast_if_present<ExplicitInstantiationInfo *>(ExplicitInfo))
		Info->TemplateArgsAsWritten = ArgsWritten;
		else
		ExplicitInfo = ArgsWritten;
		@@ -2032,7 +2042,8 @@ public:
		/// Gets the location of the extern keyword, if present.
		SourceLocation getExternKeywordLoc() const {
		- if (auto *Info = ExplicitInfo.dyn_cast<ExplicitInstantiationInfo *>())
		+ if (auto *Info =
		+ dyn_cast_if_present<ExplicitInstantiationInfo *>(ExplicitInfo))
		return Info->ExternKeywordLoc;
		return SourceLocation();
		}
		@@ -2780,7 +2791,8 @@ public:
		/// Retrieve the template argument list as written in the sources,
		/// if any.
		const ASTTemplateArgumentListInfo *getTemplateArgsAsWritten() const {
		- if (auto *Info = ExplicitInfo.dyn_cast<ExplicitInstantiationInfo *>())
		+ if (auto *Info =
		+ dyn_cast_if_present<ExplicitInstantiationInfo *>(ExplicitInfo))
		return Info->TemplateArgsAsWritten;
		return cast<const ASTTemplateArgumentListInfo *>(ExplicitInfo);
		}
		@@ -2803,7 +2815,8 @@ public:
		/// Gets the location of the extern keyword, if present.
		SourceLocation getExternKeywordLoc() const {
		- if (auto *Info = ExplicitInfo.dyn_cast<ExplicitInstantiationInfo *>())
		+ if (auto *Info =
		+ dyn_cast_if_present<ExplicitInstantiationInfo *>(ExplicitInfo))
		return Info->ExternKeywordLoc;
		return SourceLocation();
		}
		@@ -2813,7 +2826,8 @@ public:
		/// Gets the location of the template keyword, if present.
		SourceLocation getTemplateKeywordLoc() const {
		- if (auto *Info = ExplicitInfo.dyn_cast<ExplicitInstantiationInfo *>())
		+ if (auto *Info =
		+ dyn_cast_if_present<ExplicitInstantiationInfo *>(ExplicitInfo))
		return Info->TemplateKeywordLoc;
		return SourceLocation();
		}

clang/include/clang/AST/DynamicRecursiveASTVisitor.h

		@@ -52,7 +52,11 @@ class ASTContext;
		/// WalkUpFromX or post-order traversal).
		///
		/// \see RecursiveASTVisitor.
		-class DynamicRecursiveASTVisitor {
		+template <bool IsConst> class DynamicRecursiveASTVisitorBase {
		+protected:
		+ template <typename ASTNode>
		+ using MaybeConst = std::conditional_t<IsConst, const ASTNode, ASTNode>;
		+
		public:
		/// Whether this visitor should recurse into template instantiations.
		bool ShouldVisitTemplateInstantiations = false;
		@@ -68,28 +72,29 @@ public:
		bool ShouldVisitLambdaBody = true;
		protected:
		- DynamicRecursiveASTVisitor() = default;
		- DynamicRecursiveASTVisitor(DynamicRecursiveASTVisitor &&) = default;
		- DynamicRecursiveASTVisitor(const DynamicRecursiveASTVisitor &) = default;
		- DynamicRecursiveASTVisitor &
		- operator=(DynamicRecursiveASTVisitor &&) = default;
		- DynamicRecursiveASTVisitor &
		- operator=(const DynamicRecursiveASTVisitor &) = default;
		+ DynamicRecursiveASTVisitorBase() = default;
		+ DynamicRecursiveASTVisitorBase(DynamicRecursiveASTVisitorBase &&) = default;
		+ DynamicRecursiveASTVisitorBase(const DynamicRecursiveASTVisitorBase &) =
		+ default;
		+ DynamicRecursiveASTVisitorBase &
		+ operator=(DynamicRecursiveASTVisitorBase &&) = default;
		+ DynamicRecursiveASTVisitorBase &
		+ operator=(const DynamicRecursiveASTVisitorBase &) = default;
		public:
		virtual void anchor();
		- virtual ~DynamicRecursiveASTVisitor() = default;
		+ virtual ~DynamicRecursiveASTVisitorBase() = default;
		/// Recursively visits an entire AST, starting from the TranslationUnitDecl.
		/// \returns false if visitation was terminated early.
		- virtual bool TraverseAST(ASTContext &AST);
		+ virtual bool TraverseAST(MaybeConst<ASTContext> &AST);
		/// Recursively visit an attribute, by dispatching to
		/// Traverse*Attr() based on the argument's dynamic type.
		///
		/// \returns false if the visitation was terminated early, true
		/// otherwise (including when the argument is a Null type location).
		- virtual bool TraverseAttr(Attr *At);
		+ virtual bool TraverseAttr(MaybeConst<Attr> *At);
		/// Recursively visit a constructor initializer. This
		/// automatically dispatches to another visitor for the initializer
		@@ -97,7 +102,8 @@ public:
		/// be overridden for clients that need access to the name.
		///
		/// \returns false if the visitation was terminated early, true otherwise.
		- virtual bool TraverseConstructorInitializer(CXXCtorInitializer *Init);
		+ virtual bool
		+ TraverseConstructorInitializer(MaybeConst<CXXCtorInitializer> *Init);
		/// Recursively visit a base specifier. This can be overridden by a
		/// subclass.
		@@ -110,7 +116,7 @@ public:
		///
		/// \returns false if the visitation was terminated early, true
		/// otherwise (including when the argument is NULL).
		- virtual bool TraverseDecl(Decl *D);
		+ virtual bool TraverseDecl(MaybeConst<Decl> *D);
		/// Recursively visit a name with its location information.
		///
		@@ -121,13 +127,15 @@ public:
		/// will be used to initialize the capture.
		///
		/// \returns false if the visitation was terminated early, true otherwise.
		- virtual bool TraverseLambdaCapture(LambdaExpr *LE, const LambdaCapture *C,
		- Expr *Init);
		+ virtual bool TraverseLambdaCapture(MaybeConst<LambdaExpr> *LE,
		+ const LambdaCapture *C,
		+ MaybeConst<Expr> *Init);
		/// Recursively visit a C++ nested-name-specifier.
		///
		/// \returns false if the visitation was terminated early, true otherwise.
		- virtual bool TraverseNestedNameSpecifier(NestedNameSpecifier *NNS);
		+ virtual bool
		+ TraverseNestedNameSpecifier(MaybeConst<NestedNameSpecifier> *NNS);
		/// Recursively visit a C++ nested-name-specifier with location
		/// information.
		@@ -140,7 +148,7 @@ public:
		///
		/// \returns false if the visitation was terminated early, true
		/// otherwise (including when the argument is nullptr).
		- virtual bool TraverseStmt(Stmt *S);
		+ virtual bool TraverseStmt(MaybeConst<Stmt> *S);
		/// Recursively visit a template argument and dispatch to the
		/// appropriate method for the argument type.
		@@ -190,41 +198,51 @@ public:
		/// Traverse a concept (requirement).
		virtual bool TraverseTypeConstraint(const TypeConstraint *C);
		- virtual bool TraverseConceptRequirement(concepts::Requirement *R);
		- virtual bool TraverseConceptTypeRequirement(concepts::TypeRequirement *R);
		- virtual bool TraverseConceptExprRequirement(concepts::ExprRequirement *R);
		- virtual bool TraverseConceptNestedRequirement(concepts::NestedRequirement *R);
		- virtual bool TraverseConceptReference(ConceptReference *CR);
		- virtual bool VisitConceptReference(ConceptReference *CR) { return true; }
		+ virtual bool TraverseConceptRequirement(MaybeConst<concepts::Requirement> *R);
		+
		+ virtual bool
		+ TraverseConceptTypeRequirement(MaybeConst<concepts::TypeRequirement> *R);
		+
		+ virtual bool
		+ TraverseConceptExprRequirement(MaybeConst<concepts::ExprRequirement> *R);
		+
		+ virtual bool
		+ TraverseConceptNestedRequirement(MaybeConst<concepts::NestedRequirement> *R);
		+
		+ virtual bool TraverseConceptReference(MaybeConst<ConceptReference> *CR);
		+ virtual bool VisitConceptReference(MaybeConst<ConceptReference> *CR) {
		+ return true;
		+ }
		/// Visit a node.
		- virtual bool VisitAttr(Attr *A) { return true; }
		- virtual bool VisitDecl(Decl *D) { return true; }
		- virtual bool VisitStmt(Stmt *S) { return true; }
		- virtual bool VisitType(Type *T) { return true; }
		+ virtual bool VisitAttr(MaybeConst<Attr> *A) { return true; }
		+ virtual bool VisitDecl(MaybeConst<Decl> *D) { return true; }
		+ virtual bool VisitStmt(MaybeConst<Stmt> *S) { return true; }
		+ virtual bool VisitType(MaybeConst<Type> *T) { return true; }
		virtual bool VisitTypeLoc(TypeLoc TL) { return true; }
		/// Walk up from a node.
		- bool WalkUpFromDecl(Decl *D) { return VisitDecl(D); }
		- bool WalkUpFromStmt(Stmt *S) { return VisitStmt(S); }
		- bool WalkUpFromType(Type *T) { return VisitType(T); }
		+ bool WalkUpFromDecl(MaybeConst<Decl> *D) { return VisitDecl(D); }
		+ bool WalkUpFromStmt(MaybeConst<Stmt> *S) { return VisitStmt(S); }
		+ bool WalkUpFromType(MaybeConst<Type> *T) { return VisitType(T); }
		bool WalkUpFromTypeLoc(TypeLoc TL) { return VisitTypeLoc(TL); }
		/// Invoked before visiting a statement or expression via data recursion.
		///
		/// \returns false to skip visiting the node, true otherwise.
		- virtual bool dataTraverseStmtPre(Stmt *S) { return true; }
		+ virtual bool dataTraverseStmtPre(MaybeConst<Stmt> *S) { return true; }
		/// Invoked after visiting a statement or expression via data recursion.
		/// This is not invoked if the previously invoked \c dataTraverseStmtPre
		/// returned false.
		///
		/// \returns false if the visitation was terminated early, true otherwise.
		- virtual bool dataTraverseStmtPost(Stmt *S) { return true; }
		- virtual bool dataTraverseNode(Stmt *S);
		+ virtual bool dataTraverseStmtPost(MaybeConst<Stmt> *S) { return true; }
		+ virtual bool dataTraverseNode(MaybeConst<Stmt> *S);
		#define DEF_TRAVERSE_TMPL_INST(kind) \
		- virtual bool TraverseTemplateInstantiations(kind##TemplateDecl *D);
		+ virtual bool TraverseTemplateInstantiations( \
		+ MaybeConst<kind##TemplateDecl> *D);
		DEF_TRAVERSE_TMPL_INST(Class)
		DEF_TRAVERSE_TMPL_INST(Var)
		DEF_TRAVERSE_TMPL_INST(Function)
		@@ -232,32 +250,34 @@ public:
		// Decls.
		#define ABSTRACT_DECL(DECL)
		-#define DECL(CLASS, BASE) virtual bool Traverse##CLASS##Decl(CLASS##Decl *D);
		+#define DECL(CLASS, BASE) \
		+ virtual bool Traverse##CLASS##Decl(MaybeConst<CLASS##Decl> *D);
		#include "clang/AST/DeclNodes.inc"
		#define DECL(CLASS, BASE) \
		- bool WalkUpFrom##CLASS##Decl(CLASS##Decl *D); \
		- virtual bool Visit##CLASS##Decl(CLASS##Decl *D) { return true; }
		+ bool WalkUpFrom##CLASS##Decl(MaybeConst<CLASS##Decl> *D); \
		+ virtual bool Visit##CLASS##Decl(MaybeConst<CLASS##Decl> *D) { return true; }
		#include "clang/AST/DeclNodes.inc"
		// Stmts.
		#define ABSTRACT_STMT(STMT)
		-#define STMT(CLASS, PARENT) virtual bool Traverse##CLASS(CLASS *S);
		+#define STMT(CLASS, PARENT) virtual bool Traverse##CLASS(MaybeConst<CLASS> *S);
		#include "clang/AST/StmtNodes.inc"
		#define STMT(CLASS, PARENT) \
		- bool WalkUpFrom##CLASS(CLASS *S); \
		- virtual bool Visit##CLASS(CLASS *S) { return true; }
		+ bool WalkUpFrom##CLASS(MaybeConst<CLASS> *S); \
		+ virtual bool Visit##CLASS(MaybeConst<CLASS> *S) { return true; }
		#include "clang/AST/StmtNodes.inc"
		// Types.
		#define ABSTRACT_TYPE(CLASS, BASE)
		-#define TYPE(CLASS, BASE) virtual bool Traverse##CLASS##Type(CLASS##Type *T);
		+#define TYPE(CLASS, BASE) \
		+ virtual bool Traverse##CLASS##Type(MaybeConst<CLASS##Type> *T);
		#include "clang/AST/TypeNodes.inc"
		#define TYPE(CLASS, BASE) \
		- bool WalkUpFrom##CLASS##Type(CLASS##Type *T); \
		- virtual bool Visit##CLASS##Type(CLASS##Type *T) { return true; }
		+ bool WalkUpFrom##CLASS##Type(MaybeConst<CLASS##Type> *T); \
		+ virtual bool Visit##CLASS##Type(MaybeConst<CLASS##Type> *T) { return true; }
		#include "clang/AST/TypeNodes.inc"
		// TypeLocs.
		@@ -271,6 +291,14 @@ public:
		virtual bool Visit##CLASS##TypeLoc(CLASS##TypeLoc TL) { return true; }
		#include "clang/AST/TypeLocNodes.def"
		};
		+
		+extern template class DynamicRecursiveASTVisitorBase<false>;
		+extern template class DynamicRecursiveASTVisitorBase<true>;
		+
		+using DynamicRecursiveASTVisitor =
		+ DynamicRecursiveASTVisitorBase</*Const=*/false>;
		+using ConstDynamicRecursiveASTVisitor =
		+ DynamicRecursiveASTVisitorBase</*Const=*/true>;
		} // namespace clang
		#endif // LLVM_CLANG_AST_DYNAMIC_RECURSIVE_AST_VISITOR_H

clang/include/clang/AST/ExprCXX.h

		@@ -2847,8 +2847,8 @@ public:
		///
		/// Example:
		/// \code
		-/// __array_rank(int[10][20]) == 2
		-/// __array_extent(int, 1) == 20
		+/// __array_rank(int[10][20]) == 2
		+/// __array_extent(int[10][20], 1) == 20
		/// \endcode
		class ArrayTypeTraitExpr : public Expr {
		/// The trait. An ArrayTypeTrait enum in MSVC compat unsigned.
		@@ -4326,8 +4326,6 @@ public:
		/// Retrieve the parameter pack.
		NamedDecl *getPack() const { return Pack; }
		- void setPack(NamedDecl *NewPack) { Pack = NewPack; }
		-
		/// Retrieve the length of the parameter pack.
		///
		/// This routine may only be invoked when the expression is not
		@@ -5321,6 +5319,59 @@ public:
		}
		};
		+// Represents an unexpanded pack where the list of expressions are
		+// known. These are used when structured bindings introduce a pack.
		+class ResolvedUnexpandedPackExpr final
		+ : public Expr,
		+ private llvm::TrailingObjects<ResolvedUnexpandedPackExpr, Expr *> {
		+ friend class ASTStmtReader;
		+ friend class ASTStmtWriter;
		+ friend TrailingObjects;
		+
		+ SourceLocation BeginLoc;
		+ unsigned NumExprs;
		+
		+ ResolvedUnexpandedPackExpr(SourceLocation BL, QualType QT, unsigned NumExprs);
		+
		+public:
		+ static ResolvedUnexpandedPackExpr *CreateDeserialized(ASTContext &C,
		+ unsigned NumExprs);
		+ static ResolvedUnexpandedPackExpr *
		+ Create(ASTContext &C, SourceLocation BeginLoc, QualType T, unsigned NumExprs);
		+ static ResolvedUnexpandedPackExpr *Create(ASTContext &C,
		+ SourceLocation BeginLoc, QualType T,
		+ llvm::ArrayRef<Expr *> Exprs);
		+
		+ unsigned getNumExprs() const { return NumExprs; }
		+
		+ llvm::MutableArrayRef<Expr *> getExprs() {
		+ return {getTrailingObjects<Expr *>(), NumExprs};
		+ }
		+
		+ llvm::ArrayRef<Expr *> getExprs() const {
		+ return {getTrailingObjects<Expr *>(), NumExprs};
		+ }
		+
		+ Expr *getExpansion(unsigned Idx) { return getExprs()[Idx]; }
		+ Expr *getExpansion(unsigned Idx) const { return getExprs()[Idx]; }
		+
		+ // Iterators
		+ child_range children() {
		+ return child_range((Stmt **)getTrailingObjects<Expr *>(),
		+ (Stmt **)getTrailingObjects<Expr *>() + getNumExprs());
		+ }
		+
		+ SourceLocation getBeginLoc() const LLVM_READONLY { return BeginLoc; }
		+ SourceLocation getEndLoc() const LLVM_READONLY { return BeginLoc; }
		+
		+ // Returns the resolved pack of a decl or nullptr
		+ static ResolvedUnexpandedPackExpr *getFromDecl(Decl *);
		+
		+ static bool classof(const Stmt *T) {
		+ return T->getStmtClass() == ResolvedUnexpandedPackExprClass;
		+ }
		+};
		+
		} // namespace clang
		#endif // LLVM_CLANG_AST_EXPRCXX_H

clang/include/clang/AST/RecursiveASTVisitor.h

		@@ -2950,6 +2950,7 @@ DEF_TRAVERSE_STMT(FunctionParmPackExpr, {})
		DEF_TRAVERSE_STMT(CXXFoldExpr, {})
		DEF_TRAVERSE_STMT(AtomicExpr, {})
		DEF_TRAVERSE_STMT(CXXParenListInitExpr, {})
		+DEF_TRAVERSE_STMT(ResolvedUnexpandedPackExpr, {})
		DEF_TRAVERSE_STMT(MaterializeTemporaryExpr, {
		if (S->getLifetimeExtendedTemporaryDecl()) {

clang/include/clang/AST/Type.h

		@@ -2518,6 +2518,7 @@ public:
		bool isFloat32Type() const;
		bool isDoubleType() const;
		bool isBFloat16Type() const;
		+ bool isMFloat8Type() const;
		bool isFloat128Type() const;
		bool isIbm128Type() const;
		bool isRealType() const; // C99 6.2.5p17 (real floating + integer)
		@@ -8537,6 +8538,10 @@ inline bool Type::isBFloat16Type() const {
		return isSpecificBuiltinType(BuiltinType::BFloat16);
		}
		+inline bool Type::isMFloat8Type() const {
		+ return isSpecificBuiltinType(BuiltinType::MFloat8);
		+}
		+
		inline bool Type::isFloat128Type() const {
		return isSpecificBuiltinType(BuiltinType::Float128);
		}

clang/include/clang/Basic/AArch64SVEACLETypes.def

		@@ -57,6 +57,11 @@
		// - IsBF true for vector of brain float elements.
		//===----------------------------------------------------------------------===//
		+#ifndef SVE_SCALAR_TYPE
		+#define SVE_SCALAR_TYPE(Name, MangledName, Id, SingletonId, Bits) \
		+ SVE_TYPE(Name, Id, SingletonId)
		+#endif
		+
		#ifndef SVE_VECTOR_TYPE
		#define SVE_VECTOR_TYPE(Name, MangledName, Id, SingletonId) \
		SVE_TYPE(Name, Id, SingletonId)
		@@ -72,6 +77,11 @@
		SVE_VECTOR_TYPE_DETAILS(Name, MangledName, Id, SingletonId, NumEls, ElBits, NF, false, false, true)
		#endif
		+#ifndef SVE_VECTOR_TYPE_MFLOAT
		+#define SVE_VECTOR_TYPE_MFLOAT(Name, MangledName, Id, SingletonId, NumEls, ElBits, NF) \
		+ SVE_VECTOR_TYPE_DETAILS(Name, MangledName, Id, SingletonId, NumEls, ElBits, NF, false, false, false)
		+#endif
		+
		#ifndef SVE_VECTOR_TYPE_FLOAT
		#define SVE_VECTOR_TYPE_FLOAT(Name, MangledName, Id, SingletonId, NumEls, ElBits, NF) \
		SVE_VECTOR_TYPE_DETAILS(Name, MangledName, Id, SingletonId, NumEls, ElBits, NF, false, true, false)
		@@ -97,16 +107,6 @@
		SVE_TYPE(Name, Id, SingletonId)
		#endif
		-#ifndef AARCH64_VECTOR_TYPE
		-#define AARCH64_VECTOR_TYPE(Name, MangledName, Id, SingletonId) \
		- SVE_TYPE(Name, Id, SingletonId)
		-#endif
		-
		-#ifndef AARCH64_VECTOR_TYPE_MFLOAT
		-#define AARCH64_VECTOR_TYPE_MFLOAT(Name, MangledName, Id, SingletonId, NumEls, ElBits, NF) \
		- AARCH64_VECTOR_TYPE(Name, MangledName, Id, SingletonId)
		-#endif
		-
		//===- Vector point types -----------------------------------------------===//
		SVE_VECTOR_TYPE_INT("__SVInt8_t", "__SVInt8_t", SveInt8, SveInt8Ty, 16, 8, 1, true)
		@@ -125,8 +125,7 @@ SVE_VECTOR_TYPE_FLOAT("__SVFloat64_t", "__SVFloat64_t", SveFloat64, SveFloat64Ty
		SVE_VECTOR_TYPE_BFLOAT("__SVBfloat16_t", "__SVBfloat16_t", SveBFloat16, SveBFloat16Ty, 8, 16, 1)
		-// This is a 8 bits opaque type.
		-SVE_VECTOR_TYPE_INT("__SVMfloat8_t", "__SVMfloat8_t", SveMFloat8, SveMFloat8Ty, 16, 8, 1, false)
		+SVE_VECTOR_TYPE_MFLOAT("__SVMfloat8_t", "__SVMfloat8_t", SveMFloat8, SveMFloat8Ty, 16, 8, 1)
		//
		// x2
		@@ -148,7 +147,7 @@ SVE_VECTOR_TYPE_FLOAT("__clang_svfloat64x2_t", "svfloat64x2_t", SveFloat64x2, Sv
		SVE_VECTOR_TYPE_BFLOAT("__clang_svbfloat16x2_t", "svbfloat16x2_t", SveBFloat16x2, SveBFloat16x2Ty, 8, 16, 2)
		-SVE_VECTOR_TYPE_INT("__clang_svmfloat8x2_t", "svmfloat8x2_t", SveMFloat8x2, SveMFloat8x2Ty, 16, 8, 2, false)
		+SVE_VECTOR_TYPE_MFLOAT("__clang_svmfloat8x2_t", "svmfloat8x2_t", SveMFloat8x2, SveMFloat8x2Ty, 16, 8, 2)
		//
		// x3
		@@ -170,7 +169,7 @@ SVE_VECTOR_TYPE_FLOAT("__clang_svfloat64x3_t", "svfloat64x3_t", SveFloat64x3, Sv
		SVE_VECTOR_TYPE_BFLOAT("__clang_svbfloat16x3_t", "svbfloat16x3_t", SveBFloat16x3, SveBFloat16x3Ty, 8, 16, 3)
		-SVE_VECTOR_TYPE_INT("__clang_svmfloat8x3_t", "svmfloat8x3_t", SveMFloat8x3, SveMFloat8x3Ty, 16, 8, 3, false)
		+SVE_VECTOR_TYPE_MFLOAT("__clang_svmfloat8x3_t", "svmfloat8x3_t", SveMFloat8x3, SveMFloat8x3Ty, 16, 8, 3)
		//
		// x4
		@@ -192,7 +191,7 @@ SVE_VECTOR_TYPE_FLOAT("__clang_svfloat64x4_t", "svfloat64x4_t", SveFloat64x4, Sv
		SVE_VECTOR_TYPE_BFLOAT("__clang_svbfloat16x4_t", "svbfloat16x4_t", SveBFloat16x4, SveBFloat16x4Ty, 8, 16, 4)
		-SVE_VECTOR_TYPE_INT("__clang_svmfloat8x4_t", "svmfloat8x4_t", SveMFloat8x4, SveMFloat8x4Ty, 16, 8, 4, false)
		+SVE_VECTOR_TYPE_MFLOAT("__clang_svmfloat8x4_t", "svmfloat8x4_t", SveMFloat8x4, SveMFloat8x4Ty, 16, 8, 4)
		SVE_PREDICATE_TYPE_ALL("__SVBool_t", "__SVBool_t", SveBool, SveBoolTy, 16, 1)
		SVE_PREDICATE_TYPE_ALL("__clang_svboolx2_t", "svboolx2_t", SveBoolx2, SveBoolx2Ty, 16, 2)
		@@ -200,17 +199,15 @@ SVE_PREDICATE_TYPE_ALL("__clang_svboolx4_t", "svboolx4_t", SveBoolx4, SveBoolx4T
		SVE_OPAQUE_TYPE("__SVCount_t", "__SVCount_t", SveCount, SveCountTy)
		-AARCH64_VECTOR_TYPE_MFLOAT("__mfp8", "__mfp8", MFloat8, MFloat8Ty, 1, 8, 1)
		-AARCH64_VECTOR_TYPE_MFLOAT("__MFloat8x8_t", "__MFloat8x8_t", MFloat8x8, MFloat8x8Ty, 8, 8, 1)
		-AARCH64_VECTOR_TYPE_MFLOAT("__MFloat8x16_t", "__MFloat8x16_t", MFloat8x16, MFloat8x16Ty, 16, 8, 1)
		+SVE_SCALAR_TYPE("__mfp8", "__mfp8", MFloat8, MFloat8Ty, 8)
		#undef SVE_VECTOR_TYPE
		+#undef SVE_VECTOR_TYPE_MFLOAT
		#undef SVE_VECTOR_TYPE_BFLOAT
		#undef SVE_VECTOR_TYPE_FLOAT
		#undef SVE_VECTOR_TYPE_INT
		#undef SVE_PREDICATE_TYPE
		#undef SVE_PREDICATE_TYPE_ALL
		#undef SVE_OPAQUE_TYPE
		-#undef AARCH64_VECTOR_TYPE_MFLOAT
		-#undef AARCH64_VECTOR_TYPE
		+#undef SVE_SCALAR_TYPE
		#undef SVE_TYPE

clang/include/clang/Basic/Attr.td

		@@ -3458,18 +3458,16 @@ def DiagnoseIf : InheritableAttr {
		let Spellings = [GNU<"diagnose_if">];
		let Subjects = SubjectList<[Function, ObjCMethod, ObjCProperty]>;
		let Args = [ExprArgument<"Cond">, StringArgument<"Message">,
		- EnumArgument<"DiagnosticType", "DiagnosticType",
		+ EnumArgument<"DefaultSeverity",
		+ "DefaultSeverity",
		/*is_string=*/true,
		- ["error", "warning"],
		- ["DT_Error", "DT_Warning"]>,
		+ ["error", "warning"],
		+ ["DS_error", "DS_warning"]>,
		+ StringArgument<"WarningGroup", /*optional*/ 1>,
		BoolArgument<"ArgDependent", 0, /*fake*/ 1>,
		DeclArgument<Named, "Parent", 0, /*fake*/ 1>];
		let InheritEvenIfAlreadyPresent = 1;
		let LateParsed = LateAttrParseStandard;
		- let AdditionalMembers = [{
		- bool isError() const { return diagnosticType == DT_Error; }
		- bool isWarning() const { return diagnosticType == DT_Warning; }
		- }];
		let TemplateDependent = 1;
		let Documentation = [DiagnoseIfDocs];
		}

clang/include/clang/Basic/Builtins.td

		@@ -4795,6 +4795,12 @@ def HLSLWaveActiveCountBits : LangBuiltin<"HLSL_LANG"> {
		let Prototype = "unsigned int(bool)";
		}
		+def HLSLWaveActiveMax : LangBuiltin<"HLSL_LANG"> {
		+ let Spellings = ["__builtin_hlsl_wave_active_max"];
		+ let Attributes = [NoThrow, Const];
		+ let Prototype = "void (...)";
		+}
		+
		def HLSLWaveActiveSum : LangBuiltin<"HLSL_LANG"> {
		let Spellings = ["__builtin_hlsl_wave_active_sum"];
		let Attributes = [NoThrow, Const];

clang/include/clang/Basic/BuiltinsAMDGPU.def

		@@ -504,6 +504,8 @@ TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4i16, "V4sV4s*1", "nc", "gf
		TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4f16, "V4hV4h*1", "nc", "gfx12-insts,wavefrontsize64")
		TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4bf16, "V4yV4y*1", "nc", "gfx12-insts,wavefrontsize64")
		+TARGET_BUILTIN(__builtin_amdgcn_ds_bpermute_fi_b32, "iii", "nc", "gfx12-insts")
		+
		//===----------------------------------------------------------------------===//
		// WMMA builtins.
		// Postfix w32 indicates the builtin requires wavefront size of 32.

clang/include/clang/Basic/BuiltinsHexagon.def→/dev/null

		@@ -1,173 +0,0 @@
		-//===-- BuiltinsHexagon.def - Hexagon Builtin function database --*- C++ -*-==//
		-//
		-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
		-// See https://llvm.org/LICENSE.txt for license information.
		-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
		-//
		-//===----------------------------------------------------------------------===//
		-//
		-// This file defines the Hexagon-specific builtin function database. Users of
		-// this file must define the BUILTIN macro to make use of this information.
		-//
		-//===----------------------------------------------------------------------===//
		-
		-// The format of this database matches clang/Basic/Builtins.def.
		-
		-#if defined(BUILTIN) && !defined(TARGET_BUILTIN)
		-# define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
		-#endif
		-
		-#pragma push_macro("V79")
		-#define V79 "v79"
		-#pragma push_macro("V75")
		-#define V75 "v75|" V79
		-#pragma push_macro("V73")
		-#define V73 "v73|" V75
		-#pragma push_macro("V71")
		-#define V71 "v71|" V73
		-#pragma push_macro("V69")
		-#define V69 "v69|" V71
		-#pragma push_macro("V68")
		-#define V68 "v68|" V69
		-#pragma push_macro("V67")
		-#define V67 "v67|" V68
		-#pragma push_macro("V66")
		-#define V66 "v66|" V67
		-#pragma push_macro("V65")
		-#define V65 "v65|" V66
		-#pragma push_macro("V62")
		-#define V62 "v62|" V65
		-#pragma push_macro("V60")
		-#define V60 "v60|" V62
		-#pragma push_macro("V55")
		-#define V55 "v55|" V60
		-#pragma push_macro("V5")
		-#define V5 "v5|" V55
		-
		-#pragma push_macro("HVXV79")
		-#define HVXV79 "hvxv79"
		-#pragma push_macro("HVXV75")
		-#define HVXV75 "hvxv75|" HVXV79
		-#pragma push_macro("HVXV73")
		-#define HVXV73 "hvxv73|" HVXV75
		-#pragma push_macro("HVXV71")
		-#define HVXV71 "hvxv71|" HVXV73
		-#pragma push_macro("HVXV69")
		-#define HVXV69 "hvxv69|" HVXV71
		-#pragma push_macro("HVXV68")
		-#define HVXV68 "hvxv68|" HVXV69
		-#pragma push_macro("HVXV67")
		-#define HVXV67 "hvxv67|" HVXV68
		-#pragma push_macro("HVXV66")
		-#define HVXV66 "hvxv66|" HVXV67
		-#pragma push_macro("HVXV65")
		-#define HVXV65 "hvxv65|" HVXV66
		-#pragma push_macro("HVXV62")
		-#define HVXV62 "hvxv62|" HVXV65
		-#pragma push_macro("HVXV60")
		-#define HVXV60 "hvxv60|" HVXV62
		-
		-
		-// The builtins below are not autogenerated from iset.py.
		-// Make sure you do not overwrite these.
		-TARGET_BUILTIN(__builtin_SI_to_SXTHI_asrh, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_brev_ldd, "v*LLi*CLLi*iC", "", V5)
		-TARGET_BUILTIN(__builtin_brev_ldw, "v*i*Ci*iC", "", V5)
		-TARGET_BUILTIN(__builtin_brev_ldh, "v*s*Cs*iC", "", V5)
		-TARGET_BUILTIN(__builtin_brev_lduh, "v*Us*CUs*iC", "", V5)
		-TARGET_BUILTIN(__builtin_brev_ldb, "v*Sc*CSc*iC", "", V5)
		-TARGET_BUILTIN(__builtin_brev_ldub, "v*Uc*CUc*iC", "", V5)
		-TARGET_BUILTIN(__builtin_circ_ldd, "LLi*LLi*LLi*iIi", "", V5)
		-TARGET_BUILTIN(__builtin_circ_ldw, "i*i*i*iIi", "", V5)
		-TARGET_BUILTIN(__builtin_circ_ldh, "s*s*s*iIi", "", V5)
		-TARGET_BUILTIN(__builtin_circ_lduh, "Us*Us*Us*iIi", "", V5)
		-TARGET_BUILTIN(__builtin_circ_ldb, "c*c*c*iIi", "", V5)
		-TARGET_BUILTIN(__builtin_circ_ldub, "Uc*Uc*Uc*iIi", "", V5)
		-TARGET_BUILTIN(__builtin_brev_std, "LLi*CLLi*LLiiC", "", V5)
		-TARGET_BUILTIN(__builtin_brev_stw, "i*Ci*iiC", "", V5)
		-TARGET_BUILTIN(__builtin_brev_sth, "s*Cs*iiC", "", V5)
		-TARGET_BUILTIN(__builtin_brev_sthhi, "s*Cs*iiC", "", V5)
		-TARGET_BUILTIN(__builtin_brev_stb, "c*Cc*iiC", "", V5)
		-TARGET_BUILTIN(__builtin_circ_std, "LLi*LLi*LLiiIi", "", V5)
		-TARGET_BUILTIN(__builtin_circ_stw, "i*i*iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_circ_sth, "s*s*iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_circ_sthhi, "s*s*iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_circ_stb, "c*c*iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrub_pci, "iv*IiivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrb_pci, "iv*IiivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_L2_loadruh_pci, "iv*IiivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrh_pci, "iv*IiivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_L2_loadri_pci, "iv*IiivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrd_pci, "LLiv*IiivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrub_pcr, "iv*ivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrb_pcr, "iv*ivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_L2_loadruh_pcr, "iv*ivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrh_pcr, "iv*ivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_L2_loadri_pcr, "iv*ivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrd_pcr, "LLiv*ivC*", "", V5)
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_storerb_pci, "vv*IiiivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_storerh_pci, "vv*IiiivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_storerf_pci, "vv*IiiivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_storeri_pci, "vv*IiiivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_storerd_pci, "vv*IiiLLivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_storerb_pcr, "vv*iivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_storerh_pcr, "vv*iivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_storerf_pcr, "vv*iivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_storeri_pcr, "vv*iivC*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_storerd_pcr, "vv*iLLivC*", "", V5)
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_prefetch,"vv*","", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A6_vminub_RdP,"LLiLLiLLi","", V62)
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstoreq,"vV64bv*V16i","", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorenq,"vV64bv*V16i","", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorentq,"vV64bv*V16i","", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorentnq,"vV64bv*V16i","", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstoreq_128B,"vV128bv*V32i","", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorenq_128B,"vV128bv*V32i","", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorentq_128B,"vV128bv*V32i","", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorentnq_128B,"vV128bv*V32i","", HVXV60)
		-
		-
		-// These are only valid on v65
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybub_rtt,"V32iV16iLLi","", "hvxv65")
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybub_rtt_128B,"V64iV32iLLi","", "hvxv65")
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybub_rtt_acc,"V32iV32iV16iLLi","", "hvxv65")
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybub_rtt_acc_128B,"V64iV64iV32iLLi","", "hvxv65")
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt,"V32iV16iLLi","", "hvxv65")
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_128B,"V64iV32iLLi","", "hvxv65")
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc,"V32iV32iV16iLLi","", "hvxv65")
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "hvxv65")
		-
		-#include "clang/Basic/BuiltinsHexagonDep.def"
		-
		-#pragma pop_macro("HVXV60")
		-#pragma pop_macro("HVXV62")
		-#pragma pop_macro("HVXV65")
		-#pragma pop_macro("HVXV66")
		-#pragma pop_macro("HVXV67")
		-#pragma pop_macro("HVXV68")
		-#pragma pop_macro("HVXV69")
		-#pragma pop_macro("HVXV71")
		-#pragma pop_macro("HVXV73")
		-#pragma pop_macro("HVXV75")
		-#pragma pop_macro("HVXV79")
		-
		-#pragma pop_macro("V5")
		-#pragma pop_macro("V55")
		-#pragma pop_macro("V60")
		-#pragma pop_macro("V62")
		-#pragma pop_macro("V65")
		-#pragma pop_macro("V66")
		-#pragma pop_macro("V67")
		-#pragma pop_macro("V68")
		-#pragma pop_macro("V69")
		-#pragma pop_macro("V71")
		-#pragma pop_macro("V73")
		-#pragma pop_macro("V75")
		-#pragma pop_macro("V79")
		-
		-#undef BUILTIN
		-#undef TARGET_BUILTIN
		-

clang/include/clang/Basic/BuiltinsHexagon.td

		@@ -0,0 +1,2143 @@
		+//===--- BuiltinsHexagon.td - Hexagon Builtin function defs -----*- C++ -*-===//
		+//
		+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
		+// See https://llvm.org/LICENSE.txt for license information.
		+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
		+//
		+//===----------------------------------------------------------------------===//
		+//
		+// This file defines the Hexagon-specific builtin function database.
		+//
		+//===----------------------------------------------------------------------===//
		+
		+include "clang/Basic/BuiltinsBase.td"
		+
		+class VFeatures {
		+ string Features;
		+}
		+
		+class V<string version, VFeatures newer> : VFeatures {
		+ let Features = !strconcat("v", version, "|", newer.Features);
		+}
		+
		+let Features = "v79" in def V79 : VFeatures;
		+
		+def V75 : V<"75", V79>;
		+def V73 : V<"73", V75>;
		+def V71 : V<"71", V73>;
		+def V69 : V<"69", V71>;
		+def V68 : V<"68", V69>;
		+def V67 : V<"67", V68>;
		+def V66 : V<"66", V67>;
		+def V65 : V<"65", V66>;
		+def V62 : V<"62", V65>;
		+def V60 : V<"60", V62>;
		+def V55 : V<"55", V60>;
		+def V5 : V<"5", V55>;
		+
		+class HVXVFeatures {
		+ string Features;
		+}
		+
		+class HVXV<string version, HVXVFeatures newer> : HVXVFeatures {
		+ let Features = !strconcat("hvxv", version, "|", newer.Features);
		+}
		+
		+let Features = "hvxv79" in def HVXV79 : HVXVFeatures;
		+
		+def HVXV75 : HVXV<"75", HVXV79>;
		+def HVXV73 : HVXV<"73", HVXV75>;
		+def HVXV71 : HVXV<"71", HVXV73>;
		+def HVXV69 : HVXV<"69", HVXV71>;
		+def HVXV68 : HVXV<"68", HVXV69>;
		+def HVXV67 : HVXV<"67", HVXV68>;
		+def HVXV66 : HVXV<"66", HVXV67>;
		+def HVXV65 : HVXV<"65", HVXV66>;
		+def HVXV62 : HVXV<"62", HVXV65>;
		+def HVXV60 : HVXV<"60", HVXV62>;
		+
		+class HexagonBuiltin<string prototype> : TargetBuiltin {
		+ let Spellings = ["__builtin_HEXAGON_" # NAME];
		+ let Prototype = prototype;
		+ let Features = V5.Features;
		+}
		+
		+class HexagonBuiltinNoPrefix<string prototype> : TargetBuiltin {
		+ let Spellings = [NAME];
		+ let Prototype = prototype;
		+ let Features = V5.Features;
		+}
		+
		+// The builtins below are not autogenerated from iset.py.
		+// Make sure you do not overwrite these.
		+def __builtin_SI_to_SXTHI_asrh : HexagonBuiltinNoPrefix<"int(int)">;
		+def __builtin_brev_ldd : HexagonBuiltinNoPrefix<"void *(long long int * const, long long int *, int const)">;
		+def __builtin_brev_ldw : HexagonBuiltinNoPrefix<"void *(int * const, int *, int const)">;
		+def __builtin_brev_ldh : HexagonBuiltinNoPrefix<"void *(short * const, short *, int const)">;
		+def __builtin_brev_lduh : HexagonBuiltinNoPrefix<"void *(unsigned short * const, unsigned short *, int const)">;
		+def __builtin_brev_ldb : HexagonBuiltinNoPrefix<"void *(signed char * const, signed char *, int const)">;
		+def __builtin_brev_ldub : HexagonBuiltinNoPrefix<"void *(unsigned char * const, unsigned char *, int const)">;
		+def __builtin_circ_ldd : HexagonBuiltinNoPrefix<"long long int *(long long int *, long long int *, int, _Constant int)">;
		+def __builtin_circ_ldw : HexagonBuiltinNoPrefix<"int *(int *, int *, int, _Constant int)">;
		+def __builtin_circ_ldh : HexagonBuiltinNoPrefix<"short *(short *, short *, int, _Constant int)">;
		+def __builtin_circ_lduh : HexagonBuiltinNoPrefix<"unsigned short *(unsigned short *, unsigned short *, int, _Constant int)">;
		+def __builtin_circ_ldb : HexagonBuiltinNoPrefix<"char *(char *, char *, int, _Constant int)">;
		+def __builtin_circ_ldub : HexagonBuiltinNoPrefix<"unsigned char *(unsigned char *, unsigned char *, int, _Constant int)">;
		+def __builtin_brev_std : HexagonBuiltinNoPrefix<"long long int * const(long long int *, long long int, int const)">;
		+def __builtin_brev_stw : HexagonBuiltinNoPrefix<"int * const(int *, int, int const)">;
		+def __builtin_brev_sth : HexagonBuiltinNoPrefix<"short * const(short *, int, int const)">;
		+def __builtin_brev_sthhi : HexagonBuiltinNoPrefix<"short * const(short *, int, int const)">;
		+def __builtin_brev_stb : HexagonBuiltinNoPrefix<"char * const(char *, int, int const)">;
		+def __builtin_circ_std : HexagonBuiltinNoPrefix<"long long int *(long long int *, long long int, int, _Constant int)">;
		+def __builtin_circ_stw : HexagonBuiltinNoPrefix<"int *(int *, int, int, _Constant int)">;
		+def __builtin_circ_sth : HexagonBuiltinNoPrefix<"short *(short *, int, int, _Constant int)">;
		+def __builtin_circ_sthhi : HexagonBuiltinNoPrefix<"short *(short *, int, int, _Constant int)">;
		+def __builtin_circ_stb : HexagonBuiltinNoPrefix<"char *(char *, int, int, _Constant int)">;
		+def L2_loadrub_pci : HexagonBuiltin<"int(void *, _Constant int, int, void const *)">;
		+def L2_loadrb_pci : HexagonBuiltin<"int(void *, _Constant int, int, void const *)">;
		+def L2_loadruh_pci : HexagonBuiltin<"int(void *, _Constant int, int, void const *)">;
		+def L2_loadrh_pci : HexagonBuiltin<"int(void *, _Constant int, int, void const *)">;
		+def L2_loadri_pci : HexagonBuiltin<"int(void *, _Constant int, int, void const *)">;
		+def L2_loadrd_pci : HexagonBuiltin<"long long int(void *, _Constant int, int, void const *)">;
		+def L2_loadrub_pcr : HexagonBuiltin<"int(void *, int, void const *)">;
		+def L2_loadrb_pcr : HexagonBuiltin<"int(void *, int, void const *)">;
		+def L2_loadruh_pcr : HexagonBuiltin<"int(void *, int, void const *)">;
		+def L2_loadrh_pcr : HexagonBuiltin<"int(void *, int, void const *)">;
		+def L2_loadri_pcr : HexagonBuiltin<"int(void *, int, void const *)">;
		+def L2_loadrd_pcr : HexagonBuiltin<"long long int(void *, int, void const *)">;
		+
		+def S2_storerb_pci : HexagonBuiltin<"void(void *, _Constant int, int, int, void const *)">;
		+def S2_storerh_pci : HexagonBuiltin<"void(void *, _Constant int, int, int, void const *)">;
		+def S2_storerf_pci : HexagonBuiltin<"void(void *, _Constant int, int, int, void const *)">;
		+def S2_storeri_pci : HexagonBuiltin<"void(void *, _Constant int, int, int, void const *)">;
		+def S2_storerd_pci : HexagonBuiltin<"void(void *, _Constant int, int, long long int, void const *)">;
		+def S2_storerb_pcr : HexagonBuiltin<"void(void *, int, int, void const *)">;
		+def S2_storerh_pcr : HexagonBuiltin<"void(void *, int, int, void const *)">;
		+def S2_storerf_pcr : HexagonBuiltin<"void(void *, int, int, void const *)">;
		+def S2_storeri_pcr : HexagonBuiltin<"void(void *, int, int, void const *)">;
		+def S2_storerd_pcr : HexagonBuiltin<"void(void *, int, long long int, void const *)">;
		+
		+def prefetch : HexagonBuiltin<"void(void *)">;
		+let Features = V62.Features in {
		+ def A6_vminub_RdP : HexagonBuiltin<"long long int(long long int, long long int)">;
		+}
		+
		+let Features = HVXV60.Features in {
		+ def V6_vmaskedstoreq : HexagonBuiltin<"void(_Vector<64, bool>, void *, _Vector<16, int>)">;
		+ def V6_vmaskedstorenq : HexagonBuiltin<"void(_Vector<64, bool>, void *, _Vector<16, int>)">;
		+ def V6_vmaskedstorentq : HexagonBuiltin<"void(_Vector<64, bool>, void *, _Vector<16, int>)">;
		+ def V6_vmaskedstorentnq : HexagonBuiltin<"void(_Vector<64, bool>, void *, _Vector<16, int>)">;
		+ def V6_vmaskedstoreq_128B : HexagonBuiltin<"void(_Vector<128, bool>, void *, _Vector<32, int>)">;
		+ def V6_vmaskedstorenq_128B : HexagonBuiltin<"void(_Vector<128, bool>, void *, _Vector<32, int>)">;
		+ def V6_vmaskedstorentq_128B : HexagonBuiltin<"void(_Vector<128, bool>, void *, _Vector<32, int>)">;
		+ def V6_vmaskedstorentnq_128B : HexagonBuiltin<"void(_Vector<128, bool>, void *, _Vector<32, int>)">;
		+}
		+
		+
		+// These are only valid on v65
		+let Features = "hvxv65" in {
		+ def V6_vrmpybub_rtt : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, long long int)">;
		+ def V6_vrmpybub_rtt_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, long long int)">;
		+ def V6_vrmpybub_rtt_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, long long int)">;
		+ def V6_vrmpybub_rtt_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, long long int)">;
		+ def V6_vrmpyub_rtt : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, long long int)">;
		+ def V6_vrmpyub_rtt_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, long long int)">;
		+ def V6_vrmpyub_rtt_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, long long int)">;
		+ def V6_vrmpyub_rtt_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, long long int)">;
		+}
		+
		+// V5 Scalar Instructions.
		+
		+def A2_abs : HexagonBuiltin<"int(int)">;
		+def A2_absp : HexagonBuiltin<"long long int(long long int)">;
		+def A2_abssat : HexagonBuiltin<"int(int)">;
		+def A2_add : HexagonBuiltin<"int(int, int)">;
		+def A2_addh_h16_hh : HexagonBuiltin<"int(int, int)">;
		+def A2_addh_h16_hl : HexagonBuiltin<"int(int, int)">;
		+def A2_addh_h16_lh : HexagonBuiltin<"int(int, int)">;
		+def A2_addh_h16_ll : HexagonBuiltin<"int(int, int)">;
		+def A2_addh_h16_sat_hh : HexagonBuiltin<"int(int, int)">;
		+def A2_addh_h16_sat_hl : HexagonBuiltin<"int(int, int)">;
		+def A2_addh_h16_sat_lh : HexagonBuiltin<"int(int, int)">;
		+def A2_addh_h16_sat_ll : HexagonBuiltin<"int(int, int)">;
		+def A2_addh_l16_hl : HexagonBuiltin<"int(int, int)">;
		+def A2_addh_l16_ll : HexagonBuiltin<"int(int, int)">;
		+def A2_addh_l16_sat_hl : HexagonBuiltin<"int(int, int)">;
		+def A2_addh_l16_sat_ll : HexagonBuiltin<"int(int, int)">;
		+def A2_addi : HexagonBuiltin<"int(int, _Constant int)">;
		+def A2_addp : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_addpsat : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_addsat : HexagonBuiltin<"int(int, int)">;
		+def A2_addsp : HexagonBuiltin<"long long int(int, long long int)">;
		+def A2_and : HexagonBuiltin<"int(int, int)">;
		+def A2_andir : HexagonBuiltin<"int(int, _Constant int)">;
		+def A2_andp : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_aslh : HexagonBuiltin<"int(int)">;
		+def A2_asrh : HexagonBuiltin<"int(int)">;
		+def A2_combine_hh : HexagonBuiltin<"int(int, int)">;
		+def A2_combine_hl : HexagonBuiltin<"int(int, int)">;
		+def A2_combine_lh : HexagonBuiltin<"int(int, int)">;
		+def A2_combine_ll : HexagonBuiltin<"int(int, int)">;
		+def A2_combineii : HexagonBuiltin<"long long int(_Constant int, _Constant int)">;
		+def A2_combinew : HexagonBuiltin<"long long int(int, int)">;
		+def A2_max : HexagonBuiltin<"int(int, int)">;
		+def A2_maxp : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_maxu : HexagonBuiltin<"unsigned int(int, int)">;
		+def A2_maxup : HexagonBuiltin<"unsigned long long int(long long int, long long int)">;
		+def A2_min : HexagonBuiltin<"int(int, int)">;
		+def A2_minp : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_minu : HexagonBuiltin<"unsigned int(int, int)">;
		+def A2_minup : HexagonBuiltin<"unsigned long long int(long long int, long long int)">;
		+def A2_neg : HexagonBuiltin<"int(int)">;
		+def A2_negp : HexagonBuiltin<"long long int(long long int)">;
		+def A2_negsat : HexagonBuiltin<"int(int)">;
		+def A2_not : HexagonBuiltin<"int(int)">;
		+def A2_notp : HexagonBuiltin<"long long int(long long int)">;
		+def A2_or : HexagonBuiltin<"int(int, int)">;
		+def A2_orir : HexagonBuiltin<"int(int, _Constant int)">;
		+def A2_orp : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_roundsat : HexagonBuiltin<"int(long long int)">;
		+def A2_sat : HexagonBuiltin<"int(long long int)">;
		+def A2_satb : HexagonBuiltin<"int(int)">;
		+def A2_sath : HexagonBuiltin<"int(int)">;
		+def A2_satub : HexagonBuiltin<"int(int)">;
		+def A2_satuh : HexagonBuiltin<"int(int)">;
		+def A2_sub : HexagonBuiltin<"int(int, int)">;
		+def A2_subh_h16_hh : HexagonBuiltin<"int(int, int)">;
		+def A2_subh_h16_hl : HexagonBuiltin<"int(int, int)">;
		+def A2_subh_h16_lh : HexagonBuiltin<"int(int, int)">;
		+def A2_subh_h16_ll : HexagonBuiltin<"int(int, int)">;
		+def A2_subh_h16_sat_hh : HexagonBuiltin<"int(int, int)">;
		+def A2_subh_h16_sat_hl : HexagonBuiltin<"int(int, int)">;
		+def A2_subh_h16_sat_lh : HexagonBuiltin<"int(int, int)">;
		+def A2_subh_h16_sat_ll : HexagonBuiltin<"int(int, int)">;
		+def A2_subh_l16_hl : HexagonBuiltin<"int(int, int)">;
		+def A2_subh_l16_ll : HexagonBuiltin<"int(int, int)">;
		+def A2_subh_l16_sat_hl : HexagonBuiltin<"int(int, int)">;
		+def A2_subh_l16_sat_ll : HexagonBuiltin<"int(int, int)">;
		+def A2_subp : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_subri : HexagonBuiltin<"int(_Constant int, int)">;
		+def A2_subsat : HexagonBuiltin<"int(int, int)">;
		+def A2_svaddh : HexagonBuiltin<"int(int, int)">;
		+def A2_svaddhs : HexagonBuiltin<"int(int, int)">;
		+def A2_svadduhs : HexagonBuiltin<"int(int, int)">;
		+def A2_svavgh : HexagonBuiltin<"int(int, int)">;
		+def A2_svavghs : HexagonBuiltin<"int(int, int)">;
		+def A2_svnavgh : HexagonBuiltin<"int(int, int)">;
		+def A2_svsubh : HexagonBuiltin<"int(int, int)">;
		+def A2_svsubhs : HexagonBuiltin<"int(int, int)">;
		+def A2_svsubuhs : HexagonBuiltin<"int(int, int)">;
		+def A2_swiz : HexagonBuiltin<"int(int)">;
		+def A2_sxtb : HexagonBuiltin<"int(int)">;
		+def A2_sxth : HexagonBuiltin<"int(int)">;
		+def A2_sxtw : HexagonBuiltin<"long long int(int)">;
		+def A2_tfr : HexagonBuiltin<"int(int)">;
		+def A2_tfrih : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def A2_tfril : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def A2_tfrp : HexagonBuiltin<"long long int(long long int)">;
		+def A2_tfrpi : HexagonBuiltin<"long long int(_Constant int)">;
		+def A2_tfrsi : HexagonBuiltin<"int(_Constant int)">;
		+def A2_vabsh : HexagonBuiltin<"long long int(long long int)">;
		+def A2_vabshsat : HexagonBuiltin<"long long int(long long int)">;
		+def A2_vabsw : HexagonBuiltin<"long long int(long long int)">;
		+def A2_vabswsat : HexagonBuiltin<"long long int(long long int)">;
		+def A2_vaddb_map : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vaddh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vaddhs : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vaddub : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vaddubs : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vadduhs : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vaddw : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vaddws : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vavgh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vavghcr : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vavghr : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vavgub : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vavgubr : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vavguh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vavguhr : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vavguw : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vavguwr : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vavgw : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vavgwcr : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vavgwr : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vcmpbeq : HexagonBuiltin<"int(long long int, long long int)">;
		+def A2_vcmpbgtu : HexagonBuiltin<"int(long long int, long long int)">;
		+def A2_vcmpheq : HexagonBuiltin<"int(long long int, long long int)">;
		+def A2_vcmphgt : HexagonBuiltin<"int(long long int, long long int)">;
		+def A2_vcmphgtu : HexagonBuiltin<"int(long long int, long long int)">;
		+def A2_vcmpweq : HexagonBuiltin<"int(long long int, long long int)">;
		+def A2_vcmpwgt : HexagonBuiltin<"int(long long int, long long int)">;
		+def A2_vcmpwgtu : HexagonBuiltin<"int(long long int, long long int)">;
		+def A2_vconj : HexagonBuiltin<"long long int(long long int)">;
		+def A2_vmaxb : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vmaxh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vmaxub : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vmaxuh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vmaxuw : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vmaxw : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vminb : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vminh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vminub : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vminuh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vminuw : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vminw : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vnavgh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vnavghcr : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vnavghr : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vnavgw : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vnavgwcr : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vnavgwr : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vraddub : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vraddub_acc : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def A2_vrsadub : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vrsadub_acc : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def A2_vsubb_map : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vsubh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vsubhs : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vsubub : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vsububs : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vsubuhs : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vsubw : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_vsubws : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_xor : HexagonBuiltin<"int(int, int)">;
		+def A2_xorp : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A2_zxtb : HexagonBuiltin<"int(int)">;
		+def A2_zxth : HexagonBuiltin<"int(int)">;
		+def A4_andn : HexagonBuiltin<"int(int, int)">;
		+def A4_andnp : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A4_bitsplit : HexagonBuiltin<"long long int(int, int)">;
		+def A4_bitspliti : HexagonBuiltin<"long long int(int, unsigned _Constant int)">;
		+def A4_boundscheck : HexagonBuiltin<"int(int, long long int)">;
		+def A4_cmpbeq : HexagonBuiltin<"int(int, int)">;
		+def A4_cmpbeqi : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def A4_cmpbgt : HexagonBuiltin<"int(int, int)">;
		+def A4_cmpbgti : HexagonBuiltin<"int(int, _Constant int)">;
		+def A4_cmpbgtu : HexagonBuiltin<"int(int, int)">;
		+def A4_cmpbgtui : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def A4_cmpheq : HexagonBuiltin<"int(int, int)">;
		+def A4_cmpheqi : HexagonBuiltin<"int(int, _Constant int)">;
		+def A4_cmphgt : HexagonBuiltin<"int(int, int)">;
		+def A4_cmphgti : HexagonBuiltin<"int(int, _Constant int)">;
		+def A4_cmphgtu : HexagonBuiltin<"int(int, int)">;
		+def A4_cmphgtui : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def A4_combineir : HexagonBuiltin<"long long int(_Constant int, int)">;
		+def A4_combineri : HexagonBuiltin<"long long int(int, _Constant int)">;
		+def A4_cround_ri : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def A4_cround_rr : HexagonBuiltin<"int(int, int)">;
		+def A4_modwrapu : HexagonBuiltin<"int(int, int)">;
		+def A4_orn : HexagonBuiltin<"int(int, int)">;
		+def A4_ornp : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def A4_rcmpeq : HexagonBuiltin<"int(int, int)">;
		+def A4_rcmpeqi : HexagonBuiltin<"int(int, _Constant int)">;
		+def A4_rcmpneq : HexagonBuiltin<"int(int, int)">;
		+def A4_rcmpneqi : HexagonBuiltin<"int(int, _Constant int)">;
		+def A4_round_ri : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def A4_round_ri_sat : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def A4_round_rr : HexagonBuiltin<"int(int, int)">;
		+def A4_round_rr_sat : HexagonBuiltin<"int(int, int)">;
		+def A4_tlbmatch : HexagonBuiltin<"int(long long int, int)">;
		+def A4_vcmpbeq_any : HexagonBuiltin<"int(long long int, long long int)">;
		+def A4_vcmpbeqi : HexagonBuiltin<"int(long long int, unsigned _Constant int)">;
		+def A4_vcmpbgt : HexagonBuiltin<"int(long long int, long long int)">;
		+def A4_vcmpbgti : HexagonBuiltin<"int(long long int, _Constant int)">;
		+def A4_vcmpbgtui : HexagonBuiltin<"int(long long int, unsigned _Constant int)">;
		+def A4_vcmpheqi : HexagonBuiltin<"int(long long int, _Constant int)">;
		+def A4_vcmphgti : HexagonBuiltin<"int(long long int, _Constant int)">;
		+def A4_vcmphgtui : HexagonBuiltin<"int(long long int, unsigned _Constant int)">;
		+def A4_vcmpweqi : HexagonBuiltin<"int(long long int, _Constant int)">;
		+def A4_vcmpwgti : HexagonBuiltin<"int(long long int, _Constant int)">;
		+def A4_vcmpwgtui : HexagonBuiltin<"int(long long int, unsigned _Constant int)">;
		+def A4_vrmaxh : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def A4_vrmaxuh : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def A4_vrmaxuw : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def A4_vrmaxw : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def A4_vrminh : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def A4_vrminuh : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def A4_vrminuw : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def A4_vrminw : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def A5_vaddhubs : HexagonBuiltin<"int(long long int, long long int)">;
		+def C2_all8 : HexagonBuiltin<"int(int)">;
		+def C2_and : HexagonBuiltin<"int(int, int)">;
		+def C2_andn : HexagonBuiltin<"int(int, int)">;
		+def C2_any8 : HexagonBuiltin<"int(int)">;
		+def C2_bitsclr : HexagonBuiltin<"int(int, int)">;
		+def C2_bitsclri : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def C2_bitsset : HexagonBuiltin<"int(int, int)">;
		+def C2_cmpeq : HexagonBuiltin<"int(int, int)">;
		+def C2_cmpeqi : HexagonBuiltin<"int(int, _Constant int)">;
		+def C2_cmpeqp : HexagonBuiltin<"int(long long int, long long int)">;
		+def C2_cmpgei : HexagonBuiltin<"int(int, _Constant int)">;
		+def C2_cmpgeui : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def C2_cmpgt : HexagonBuiltin<"int(int, int)">;
		+def C2_cmpgti : HexagonBuiltin<"int(int, _Constant int)">;
		+def C2_cmpgtp : HexagonBuiltin<"int(long long int, long long int)">;
		+def C2_cmpgtu : HexagonBuiltin<"int(int, int)">;
		+def C2_cmpgtui : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def C2_cmpgtup : HexagonBuiltin<"int(long long int, long long int)">;
		+def C2_cmplt : HexagonBuiltin<"int(int, int)">;
		+def C2_cmpltu : HexagonBuiltin<"int(int, int)">;
		+def C2_mask : HexagonBuiltin<"long long int(int)">;
		+def C2_mux : HexagonBuiltin<"int(int, int, int)">;
		+def C2_muxii : HexagonBuiltin<"int(int, _Constant int, _Constant int)">;
		+def C2_muxir : HexagonBuiltin<"int(int, int, _Constant int)">;
		+def C2_muxri : HexagonBuiltin<"int(int, _Constant int, int)">;
		+def C2_not : HexagonBuiltin<"int(int)">;
		+def C2_or : HexagonBuiltin<"int(int, int)">;
		+def C2_orn : HexagonBuiltin<"int(int, int)">;
		+def C2_pxfer_map : HexagonBuiltin<"int(int)">;
		+def C2_tfrpr : HexagonBuiltin<"int(int)">;
		+def C2_tfrrp : HexagonBuiltin<"int(int)">;
		+def C2_vitpack : HexagonBuiltin<"int(int, int)">;
		+def C2_vmux : HexagonBuiltin<"long long int(int, long long int, long long int)">;
		+def C2_xor : HexagonBuiltin<"int(int, int)">;
		+def C4_and_and : HexagonBuiltin<"int(int, int, int)">;
		+def C4_and_andn : HexagonBuiltin<"int(int, int, int)">;
		+def C4_and_or : HexagonBuiltin<"int(int, int, int)">;
		+def C4_and_orn : HexagonBuiltin<"int(int, int, int)">;
		+def C4_cmplte : HexagonBuiltin<"int(int, int)">;
		+def C4_cmpltei : HexagonBuiltin<"int(int, _Constant int)">;
		+def C4_cmplteu : HexagonBuiltin<"int(int, int)">;
		+def C4_cmplteui : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def C4_cmpneq : HexagonBuiltin<"int(int, int)">;
		+def C4_cmpneqi : HexagonBuiltin<"int(int, _Constant int)">;
		+def C4_fastcorner9 : HexagonBuiltin<"int(int, int)">;
		+def C4_fastcorner9_not : HexagonBuiltin<"int(int, int)">;
		+def C4_nbitsclr : HexagonBuiltin<"int(int, int)">;
		+def C4_nbitsclri : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def C4_nbitsset : HexagonBuiltin<"int(int, int)">;
		+def C4_or_and : HexagonBuiltin<"int(int, int, int)">;
		+def C4_or_andn : HexagonBuiltin<"int(int, int, int)">;
		+def C4_or_or : HexagonBuiltin<"int(int, int, int)">;
		+def C4_or_orn : HexagonBuiltin<"int(int, int, int)">;
		+def F2_conv_d2df : HexagonBuiltin<"double(long long int)">;
		+def F2_conv_d2sf : HexagonBuiltin<"float(long long int)">;
		+def F2_conv_df2d : HexagonBuiltin<"long long int(double)">;
		+def F2_conv_df2d_chop : HexagonBuiltin<"long long int(double)">;
		+def F2_conv_df2sf : HexagonBuiltin<"float(double)">;
		+def F2_conv_df2ud : HexagonBuiltin<"long long int(double)">;
		+def F2_conv_df2ud_chop : HexagonBuiltin<"long long int(double)">;
		+def F2_conv_df2uw : HexagonBuiltin<"int(double)">;
		+def F2_conv_df2uw_chop : HexagonBuiltin<"int(double)">;
		+def F2_conv_df2w : HexagonBuiltin<"int(double)">;
		+def F2_conv_df2w_chop : HexagonBuiltin<"int(double)">;
		+def F2_conv_sf2d : HexagonBuiltin<"long long int(float)">;
		+def F2_conv_sf2d_chop : HexagonBuiltin<"long long int(float)">;
		+def F2_conv_sf2df : HexagonBuiltin<"double(float)">;
		+def F2_conv_sf2ud : HexagonBuiltin<"long long int(float)">;
		+def F2_conv_sf2ud_chop : HexagonBuiltin<"long long int(float)">;
		+def F2_conv_sf2uw : HexagonBuiltin<"int(float)">;
		+def F2_conv_sf2uw_chop : HexagonBuiltin<"int(float)">;
		+def F2_conv_sf2w : HexagonBuiltin<"int(float)">;
		+def F2_conv_sf2w_chop : HexagonBuiltin<"int(float)">;
		+def F2_conv_ud2df : HexagonBuiltin<"double(long long int)">;
		+def F2_conv_ud2sf : HexagonBuiltin<"float(long long int)">;
		+def F2_conv_uw2df : HexagonBuiltin<"double(int)">;
		+def F2_conv_uw2sf : HexagonBuiltin<"float(int)">;
		+def F2_conv_w2df : HexagonBuiltin<"double(int)">;
		+def F2_conv_w2sf : HexagonBuiltin<"float(int)">;
		+def F2_dfclass : HexagonBuiltin<"int(double, unsigned _Constant int)">;
		+def F2_dfcmpeq : HexagonBuiltin<"int(double, double)">;
		+def F2_dfcmpge : HexagonBuiltin<"int(double, double)">;
		+def F2_dfcmpgt : HexagonBuiltin<"int(double, double)">;
		+def F2_dfcmpuo : HexagonBuiltin<"int(double, double)">;
		+def F2_dfimm_n : HexagonBuiltin<"double(unsigned _Constant int)">;
		+def F2_dfimm_p : HexagonBuiltin<"double(unsigned _Constant int)">;
		+def F2_sfadd : HexagonBuiltin<"float(float, float)">;
		+def F2_sfclass : HexagonBuiltin<"int(float, unsigned _Constant int)">;
		+def F2_sfcmpeq : HexagonBuiltin<"int(float, float)">;
		+def F2_sfcmpge : HexagonBuiltin<"int(float, float)">;
		+def F2_sfcmpgt : HexagonBuiltin<"int(float, float)">;
		+def F2_sfcmpuo : HexagonBuiltin<"int(float, float)">;
		+def F2_sffixupd : HexagonBuiltin<"float(float, float)">;
		+def F2_sffixupn : HexagonBuiltin<"float(float, float)">;
		+def F2_sffixupr : HexagonBuiltin<"float(float)">;
		+def F2_sffma : HexagonBuiltin<"float(float, float, float)">;
		+def F2_sffma_lib : HexagonBuiltin<"float(float, float, float)">;
		+def F2_sffma_sc : HexagonBuiltin<"float(float, float, float, int)">;
		+def F2_sffms : HexagonBuiltin<"float(float, float, float)">;
		+def F2_sffms_lib : HexagonBuiltin<"float(float, float, float)">;
		+def F2_sfimm_n : HexagonBuiltin<"float(unsigned _Constant int)">;
		+def F2_sfimm_p : HexagonBuiltin<"float(unsigned _Constant int)">;
		+def F2_sfmax : HexagonBuiltin<"float(float, float)">;
		+def F2_sfmin : HexagonBuiltin<"float(float, float)">;
		+def F2_sfmpy : HexagonBuiltin<"float(float, float)">;
		+def F2_sfsub : HexagonBuiltin<"float(float, float)">;
		+def M2_acci : HexagonBuiltin<"int(int, int, int)">;
		+def M2_accii : HexagonBuiltin<"int(int, int, _Constant int)">;
		+def M2_cmaci_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_cmacr_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_cmacs_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_cmacs_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_cmacsc_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_cmacsc_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_cmpyi_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_cmpyr_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_cmpyrs_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_cmpyrs_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_cmpyrsc_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_cmpyrsc_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_cmpys_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_cmpys_s1 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_cmpysc_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_cmpysc_s1 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_cnacs_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_cnacs_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_cnacsc_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_cnacsc_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_dpmpyss_acc_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_dpmpyss_nac_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_dpmpyss_rnd_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_dpmpyss_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_dpmpyuu_acc_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_dpmpyuu_nac_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_dpmpyuu_s0 : HexagonBuiltin<"unsigned long long int(int, int)">;
		+def M2_hmmpyh_rs1 : HexagonBuiltin<"int(int, int)">;
		+def M2_hmmpyh_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_hmmpyl_rs1 : HexagonBuiltin<"int(int, int)">;
		+def M2_hmmpyl_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_maci : HexagonBuiltin<"int(int, int, int)">;
		+def M2_macsin : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def M2_macsip : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def M2_mmachs_rs0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmachs_rs1 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmachs_s0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmachs_s1 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmacls_rs0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmacls_rs1 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmacls_s0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmacls_s1 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmacuhs_rs0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmacuhs_rs1 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmacuhs_s0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmacuhs_s1 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmaculs_rs0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmaculs_rs1 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmaculs_s0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmaculs_s1 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_mmpyh_rs0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyh_rs1 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyh_s0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyh_s1 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyl_rs0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyl_rs1 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyl_s0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyl_s1 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyuh_rs0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyuh_rs1 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyuh_s0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyuh_s1 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyul_rs0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyul_rs1 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyul_s0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mmpyul_s1 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_mpy_acc_hh_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_hh_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_hl_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_hl_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_lh_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_lh_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_ll_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_ll_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_sat_hh_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_sat_hh_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_sat_hl_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_sat_hl_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_sat_lh_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_sat_lh_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_sat_ll_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_acc_sat_ll_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_hh_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_hh_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_hl_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_hl_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_lh_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_lh_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_ll_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_ll_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_nac_hh_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_hh_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_hl_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_hl_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_lh_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_lh_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_ll_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_ll_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_sat_hh_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_sat_hh_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_sat_hl_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_sat_hl_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_sat_lh_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_sat_lh_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_sat_ll_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_nac_sat_ll_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpy_rnd_hh_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_rnd_hh_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_rnd_hl_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_rnd_hl_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_rnd_lh_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_rnd_lh_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_rnd_ll_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_rnd_ll_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_hh_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_hh_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_hl_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_hl_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_lh_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_lh_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_ll_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_ll_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_rnd_hh_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_rnd_hh_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_rnd_hl_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_rnd_hl_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_rnd_lh_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_rnd_lh_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_rnd_ll_s0 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_sat_rnd_ll_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_up : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_up_s1 : HexagonBuiltin<"int(int, int)">;
		+def M2_mpy_up_s1_sat : HexagonBuiltin<"int(int, int)">;
		+def M2_mpyd_acc_hh_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_acc_hh_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_acc_hl_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_acc_hl_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_acc_lh_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_acc_lh_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_acc_ll_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_acc_ll_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_hh_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_hh_s1 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_hl_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_hl_s1 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_lh_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_lh_s1 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_ll_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_ll_s1 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_nac_hh_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_nac_hh_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_nac_hl_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_nac_hl_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_nac_lh_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_nac_lh_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_nac_ll_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_nac_ll_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyd_rnd_hh_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_rnd_hh_s1 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_rnd_hl_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_rnd_hl_s1 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_rnd_lh_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_rnd_lh_s1 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_rnd_ll_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyd_rnd_ll_s1 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_mpyi : HexagonBuiltin<"int(int, int)">;
		+def M2_mpysmi : HexagonBuiltin<"int(int, _Constant int)">;
		+def M2_mpysu_up : HexagonBuiltin<"int(int, int)">;
		+def M2_mpyu_acc_hh_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_acc_hh_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_acc_hl_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_acc_hl_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_acc_lh_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_acc_lh_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_acc_ll_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_acc_ll_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_hh_s0 : HexagonBuiltin<"unsigned int(int, int)">;
		+def M2_mpyu_hh_s1 : HexagonBuiltin<"unsigned int(int, int)">;
		+def M2_mpyu_hl_s0 : HexagonBuiltin<"unsigned int(int, int)">;
		+def M2_mpyu_hl_s1 : HexagonBuiltin<"unsigned int(int, int)">;
		+def M2_mpyu_lh_s0 : HexagonBuiltin<"unsigned int(int, int)">;
		+def M2_mpyu_lh_s1 : HexagonBuiltin<"unsigned int(int, int)">;
		+def M2_mpyu_ll_s0 : HexagonBuiltin<"unsigned int(int, int)">;
		+def M2_mpyu_ll_s1 : HexagonBuiltin<"unsigned int(int, int)">;
		+def M2_mpyu_nac_hh_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_nac_hh_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_nac_hl_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_nac_hl_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_nac_lh_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_nac_lh_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_nac_ll_s0 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_nac_ll_s1 : HexagonBuiltin<"int(int, int, int)">;
		+def M2_mpyu_up : HexagonBuiltin<"unsigned int(int, int)">;
		+def M2_mpyud_acc_hh_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_acc_hh_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_acc_hl_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_acc_hl_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_acc_lh_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_acc_lh_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_acc_ll_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_acc_ll_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_hh_s0 : HexagonBuiltin<"unsigned long long int(int, int)">;
		+def M2_mpyud_hh_s1 : HexagonBuiltin<"unsigned long long int(int, int)">;
		+def M2_mpyud_hl_s0 : HexagonBuiltin<"unsigned long long int(int, int)">;
		+def M2_mpyud_hl_s1 : HexagonBuiltin<"unsigned long long int(int, int)">;
		+def M2_mpyud_lh_s0 : HexagonBuiltin<"unsigned long long int(int, int)">;
		+def M2_mpyud_lh_s1 : HexagonBuiltin<"unsigned long long int(int, int)">;
		+def M2_mpyud_ll_s0 : HexagonBuiltin<"unsigned long long int(int, int)">;
		+def M2_mpyud_ll_s1 : HexagonBuiltin<"unsigned long long int(int, int)">;
		+def M2_mpyud_nac_hh_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_nac_hh_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_nac_hl_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_nac_hl_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_nac_lh_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_nac_lh_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_nac_ll_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyud_nac_ll_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_mpyui : HexagonBuiltin<"int(int, int)">;
		+def M2_nacci : HexagonBuiltin<"int(int, int, int)">;
		+def M2_naccii : HexagonBuiltin<"int(int, int, _Constant int)">;
		+def M2_subacc : HexagonBuiltin<"int(int, int, int)">;
		+def M2_vabsdiffh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_vabsdiffw : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_vcmac_s0_sat_i : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_vcmac_s0_sat_r : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_vcmpy_s0_sat_i : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_vcmpy_s0_sat_r : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_vcmpy_s1_sat_i : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_vcmpy_s1_sat_r : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_vdmacs_s0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_vdmacs_s1 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_vdmpyrs_s0 : HexagonBuiltin<"int(long long int, long long int)">;
		+def M2_vdmpyrs_s1 : HexagonBuiltin<"int(long long int, long long int)">;
		+def M2_vdmpys_s0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_vdmpys_s1 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_vmac2 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_vmac2es : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_vmac2es_s0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_vmac2es_s1 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_vmac2s_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_vmac2s_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_vmac2su_s0 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_vmac2su_s1 : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M2_vmpy2es_s0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_vmpy2es_s1 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_vmpy2s_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_vmpy2s_s0pack : HexagonBuiltin<"int(int, int)">;
		+def M2_vmpy2s_s1 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_vmpy2s_s1pack : HexagonBuiltin<"int(int, int)">;
		+def M2_vmpy2su_s0 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_vmpy2su_s1 : HexagonBuiltin<"long long int(int, int)">;
		+def M2_vraddh : HexagonBuiltin<"int(long long int, long long int)">;
		+def M2_vradduh : HexagonBuiltin<"int(long long int, long long int)">;
		+def M2_vrcmaci_s0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_vrcmaci_s0c : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_vrcmacr_s0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_vrcmacr_s0c : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_vrcmpyi_s0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_vrcmpyi_s0c : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_vrcmpyr_s0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_vrcmpyr_s0c : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_vrcmpys_acc_s1 : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def M2_vrcmpys_s1 : HexagonBuiltin<"long long int(long long int, int)">;
		+def M2_vrcmpys_s1rp : HexagonBuiltin<"int(long long int, int)">;
		+def M2_vrmac_s0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M2_vrmpy_s0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M2_xor_xacc : HexagonBuiltin<"int(int, int, int)">;
		+def M4_and_and : HexagonBuiltin<"int(int, int, int)">;
		+def M4_and_andn : HexagonBuiltin<"int(int, int, int)">;
		+def M4_and_or : HexagonBuiltin<"int(int, int, int)">;
		+def M4_and_xor : HexagonBuiltin<"int(int, int, int)">;
		+def M4_cmpyi_wh : HexagonBuiltin<"int(long long int, int)">;
		+def M4_cmpyi_whc : HexagonBuiltin<"int(long long int, int)">;
		+def M4_cmpyr_wh : HexagonBuiltin<"int(long long int, int)">;
		+def M4_cmpyr_whc : HexagonBuiltin<"int(long long int, int)">;
		+def M4_mac_up_s1_sat : HexagonBuiltin<"int(int, int, int)">;
		+def M4_mpyri_addi : HexagonBuiltin<"int(unsigned _Constant int, int, unsigned _Constant int)">;
		+def M4_mpyri_addr : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def M4_mpyri_addr_u2 : HexagonBuiltin<"int(int, unsigned _Constant int, int)">;
		+def M4_mpyrr_addi : HexagonBuiltin<"int(unsigned _Constant int, int, int)">;
		+def M4_mpyrr_addr : HexagonBuiltin<"int(int, int, int)">;
		+def M4_nac_up_s1_sat : HexagonBuiltin<"int(int, int, int)">;
		+def M4_or_and : HexagonBuiltin<"int(int, int, int)">;
		+def M4_or_andn : HexagonBuiltin<"int(int, int, int)">;
		+def M4_or_or : HexagonBuiltin<"int(int, int, int)">;
		+def M4_or_xor : HexagonBuiltin<"int(int, int, int)">;
		+def M4_pmpyw : HexagonBuiltin<"long long int(int, int)">;
		+def M4_pmpyw_acc : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M4_vpmpyh : HexagonBuiltin<"long long int(int, int)">;
		+def M4_vpmpyh_acc : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M4_vrmpyeh_acc_s0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M4_vrmpyeh_acc_s1 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M4_vrmpyeh_s0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M4_vrmpyeh_s1 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M4_vrmpyoh_acc_s0 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M4_vrmpyoh_acc_s1 : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M4_vrmpyoh_s0 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M4_vrmpyoh_s1 : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M4_xor_and : HexagonBuiltin<"int(int, int, int)">;
		+def M4_xor_andn : HexagonBuiltin<"int(int, int, int)">;
		+def M4_xor_or : HexagonBuiltin<"int(int, int, int)">;
		+def M4_xor_xacc : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M5_vdmacbsu : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M5_vdmpybsu : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M5_vmacbsu : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M5_vmacbuu : HexagonBuiltin<"long long int(long long int, int, int)">;
		+def M5_vmpybsu : HexagonBuiltin<"long long int(int, int)">;
		+def M5_vmpybuu : HexagonBuiltin<"long long int(int, int)">;
		+def M5_vrmacbsu : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M5_vrmacbuu : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def M5_vrmpybsu : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def M5_vrmpybuu : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S2_addasl_rrri : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_asl_i_p : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+def S2_asl_i_p_acc : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_asl_i_p_and : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_asl_i_p_nac : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_asl_i_p_or : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_asl_i_p_xacc : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_asl_i_r : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def S2_asl_i_r_acc : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_asl_i_r_and : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_asl_i_r_nac : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_asl_i_r_or : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_asl_i_r_sat : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def S2_asl_i_r_xacc : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_asl_i_vh : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+def S2_asl_i_vw : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+def S2_asl_r_p : HexagonBuiltin<"long long int(long long int, int)">;
		+def S2_asl_r_p_acc : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_asl_r_p_and : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_asl_r_p_nac : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_asl_r_p_or : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_asl_r_p_xor : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_asl_r_r : HexagonBuiltin<"int(int, int)">;
		+def S2_asl_r_r_acc : HexagonBuiltin<"int(int, int, int)">;
		+def S2_asl_r_r_and : HexagonBuiltin<"int(int, int, int)">;
		+def S2_asl_r_r_nac : HexagonBuiltin<"int(int, int, int)">;
		+def S2_asl_r_r_or : HexagonBuiltin<"int(int, int, int)">;
		+def S2_asl_r_r_sat : HexagonBuiltin<"int(int, int)">;
		+def S2_asl_r_vh : HexagonBuiltin<"long long int(long long int, int)">;
		+def S2_asl_r_vw : HexagonBuiltin<"long long int(long long int, int)">;
		+def S2_asr_i_p : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+def S2_asr_i_p_acc : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_asr_i_p_and : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_asr_i_p_nac : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_asr_i_p_or : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_asr_i_p_rnd : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+def S2_asr_i_p_rnd_goodsyntax : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+def S2_asr_i_r : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def S2_asr_i_r_acc : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_asr_i_r_and : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_asr_i_r_nac : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_asr_i_r_or : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_asr_i_r_rnd : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def S2_asr_i_r_rnd_goodsyntax : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def S2_asr_i_svw_trun : HexagonBuiltin<"int(long long int, unsigned _Constant int)">;
		+def S2_asr_i_vh : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+def S2_asr_i_vw : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+def S2_asr_r_p : HexagonBuiltin<"long long int(long long int, int)">;
		+def S2_asr_r_p_acc : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_asr_r_p_and : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_asr_r_p_nac : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_asr_r_p_or : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_asr_r_p_xor : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_asr_r_r : HexagonBuiltin<"int(int, int)">;
		+def S2_asr_r_r_acc : HexagonBuiltin<"int(int, int, int)">;
		+def S2_asr_r_r_and : HexagonBuiltin<"int(int, int, int)">;
		+def S2_asr_r_r_nac : HexagonBuiltin<"int(int, int, int)">;
		+def S2_asr_r_r_or : HexagonBuiltin<"int(int, int, int)">;
		+def S2_asr_r_r_sat : HexagonBuiltin<"int(int, int)">;
		+def S2_asr_r_svw_trun : HexagonBuiltin<"int(long long int, int)">;
		+def S2_asr_r_vh : HexagonBuiltin<"long long int(long long int, int)">;
		+def S2_asr_r_vw : HexagonBuiltin<"long long int(long long int, int)">;
		+def S2_brev : HexagonBuiltin<"int(int)">;
		+def S2_brevp : HexagonBuiltin<"long long int(long long int)">;
		+def S2_cl0 : HexagonBuiltin<"int(int)">;
		+def S2_cl0p : HexagonBuiltin<"int(long long int)">;
		+def S2_cl1 : HexagonBuiltin<"int(int)">;
		+def S2_cl1p : HexagonBuiltin<"int(long long int)">;
		+def S2_clb : HexagonBuiltin<"int(int)">;
		+def S2_clbnorm : HexagonBuiltin<"int(int)">;
		+def S2_clbp : HexagonBuiltin<"int(long long int)">;
		+def S2_clrbit_i : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def S2_clrbit_r : HexagonBuiltin<"int(int, int)">;
		+def S2_ct0 : HexagonBuiltin<"int(int)">;
		+def S2_ct0p : HexagonBuiltin<"int(long long int)">;
		+def S2_ct1 : HexagonBuiltin<"int(int)">;
		+def S2_ct1p : HexagonBuiltin<"int(long long int)">;
		+def S2_deinterleave : HexagonBuiltin<"long long int(long long int)">;
		+def S2_extractu : HexagonBuiltin<"int(int, unsigned _Constant int, unsigned _Constant int)">;
		+def S2_extractu_rp : HexagonBuiltin<"int(int, long long int)">;
		+def S2_extractup : HexagonBuiltin<"long long int(long long int, unsigned _Constant int, unsigned _Constant int)">;
		+def S2_extractup_rp : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S2_insert : HexagonBuiltin<"int(int, int, unsigned _Constant int, unsigned _Constant int)">;
		+def S2_insert_rp : HexagonBuiltin<"int(int, int, long long int)">;
		+def S2_insertp : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int, unsigned _Constant int)">;
		+def S2_insertp_rp : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+def S2_interleave : HexagonBuiltin<"long long int(long long int)">;
		+def S2_lfsp : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S2_lsl_r_p : HexagonBuiltin<"long long int(long long int, int)">;
		+def S2_lsl_r_p_acc : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_lsl_r_p_and : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_lsl_r_p_nac : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_lsl_r_p_or : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_lsl_r_p_xor : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_lsl_r_r : HexagonBuiltin<"int(int, int)">;
		+def S2_lsl_r_r_acc : HexagonBuiltin<"int(int, int, int)">;
		+def S2_lsl_r_r_and : HexagonBuiltin<"int(int, int, int)">;
		+def S2_lsl_r_r_nac : HexagonBuiltin<"int(int, int, int)">;
		+def S2_lsl_r_r_or : HexagonBuiltin<"int(int, int, int)">;
		+def S2_lsl_r_vh : HexagonBuiltin<"long long int(long long int, int)">;
		+def S2_lsl_r_vw : HexagonBuiltin<"long long int(long long int, int)">;
		+def S2_lsr_i_p : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+def S2_lsr_i_p_acc : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_lsr_i_p_and : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_lsr_i_p_nac : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_lsr_i_p_or : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_lsr_i_p_xacc : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_lsr_i_r : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def S2_lsr_i_r_acc : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_lsr_i_r_and : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_lsr_i_r_nac : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_lsr_i_r_or : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_lsr_i_r_xacc : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+def S2_lsr_i_vh : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+def S2_lsr_i_vw : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+def S2_lsr_r_p : HexagonBuiltin<"long long int(long long int, int)">;
		+def S2_lsr_r_p_acc : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_lsr_r_p_and : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_lsr_r_p_nac : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_lsr_r_p_or : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_lsr_r_p_xor : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_lsr_r_r : HexagonBuiltin<"int(int, int)">;
		+def S2_lsr_r_r_acc : HexagonBuiltin<"int(int, int, int)">;
		+def S2_lsr_r_r_and : HexagonBuiltin<"int(int, int, int)">;
		+def S2_lsr_r_r_nac : HexagonBuiltin<"int(int, int, int)">;
		+def S2_lsr_r_r_or : HexagonBuiltin<"int(int, int, int)">;
		+def S2_lsr_r_vh : HexagonBuiltin<"long long int(long long int, int)">;
		+def S2_lsr_r_vw : HexagonBuiltin<"long long int(long long int, int)">;
		+def S2_packhl : HexagonBuiltin<"long long int(int, int)">;
		+def S2_parityp : HexagonBuiltin<"int(long long int, long long int)">;
		+def S2_setbit_i : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def S2_setbit_r : HexagonBuiltin<"int(int, int)">;
		+def S2_shuffeb : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S2_shuffeh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S2_shuffob : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S2_shuffoh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S2_svsathb : HexagonBuiltin<"int(int)">;
		+def S2_svsathub : HexagonBuiltin<"int(int)">;
		+def S2_tableidxb_goodsyntax : HexagonBuiltin<"int(int, int, unsigned _Constant int, unsigned _Constant int)">;
		+def S2_tableidxd_goodsyntax : HexagonBuiltin<"int(int, int, unsigned _Constant int, unsigned _Constant int)">;
		+def S2_tableidxh_goodsyntax : HexagonBuiltin<"int(int, int, unsigned _Constant int, unsigned _Constant int)">;
		+def S2_tableidxw_goodsyntax : HexagonBuiltin<"int(int, int, unsigned _Constant int, unsigned _Constant int)">;
		+def S2_togglebit_i : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def S2_togglebit_r : HexagonBuiltin<"int(int, int)">;
		+def S2_tstbit_i : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def S2_tstbit_r : HexagonBuiltin<"int(int, int)">;
		+def S2_valignib : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_valignrb : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_vcnegh : HexagonBuiltin<"long long int(long long int, int)">;
		+def S2_vcrotate : HexagonBuiltin<"long long int(long long int, int)">;
		+def S2_vrcnegh : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_vrndpackwh : HexagonBuiltin<"int(long long int)">;
		+def S2_vrndpackwhs : HexagonBuiltin<"int(long long int)">;
		+def S2_vsathb : HexagonBuiltin<"int(long long int)">;
		+def S2_vsathb_nopack : HexagonBuiltin<"long long int(long long int)">;
		+def S2_vsathub : HexagonBuiltin<"int(long long int)">;
		+def S2_vsathub_nopack : HexagonBuiltin<"long long int(long long int)">;
		+def S2_vsatwh : HexagonBuiltin<"int(long long int)">;
		+def S2_vsatwh_nopack : HexagonBuiltin<"long long int(long long int)">;
		+def S2_vsatwuh : HexagonBuiltin<"int(long long int)">;
		+def S2_vsatwuh_nopack : HexagonBuiltin<"long long int(long long int)">;
		+def S2_vsplatrb : HexagonBuiltin<"int(int)">;
		+def S2_vsplatrh : HexagonBuiltin<"long long int(int)">;
		+def S2_vspliceib : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+def S2_vsplicerb : HexagonBuiltin<"long long int(long long int, long long int, int)">;
		+def S2_vsxtbh : HexagonBuiltin<"long long int(int)">;
		+def S2_vsxthw : HexagonBuiltin<"long long int(int)">;
		+def S2_vtrunehb : HexagonBuiltin<"int(long long int)">;
		+def S2_vtrunewh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S2_vtrunohb : HexagonBuiltin<"int(long long int)">;
		+def S2_vtrunowh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S2_vzxtbh : HexagonBuiltin<"long long int(int)">;
		+def S2_vzxthw : HexagonBuiltin<"long long int(int)">;
		+def S4_addaddi : HexagonBuiltin<"int(int, int, _Constant int)">;
		+def S4_addi_asl_ri : HexagonBuiltin<"int(unsigned _Constant int, int, unsigned _Constant int)">;
		+def S4_addi_lsr_ri : HexagonBuiltin<"int(unsigned _Constant int, int, unsigned _Constant int)">;
		+def S4_andi_asl_ri : HexagonBuiltin<"int(unsigned _Constant int, int, unsigned _Constant int)">;
		+def S4_andi_lsr_ri : HexagonBuiltin<"int(unsigned _Constant int, int, unsigned _Constant int)">;
		+def S4_clbaddi : HexagonBuiltin<"int(int, _Constant int)">;
		+def S4_clbpaddi : HexagonBuiltin<"int(long long int, _Constant int)">;
		+def S4_clbpnorm : HexagonBuiltin<"int(long long int)">;
		+def S4_extract : HexagonBuiltin<"int(int, unsigned _Constant int, unsigned _Constant int)">;
		+def S4_extract_rp : HexagonBuiltin<"int(int, long long int)">;
		+def S4_extractp : HexagonBuiltin<"long long int(long long int, unsigned _Constant int, unsigned _Constant int)">;
		+def S4_extractp_rp : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S4_lsli : HexagonBuiltin<"int(_Constant int, int)">;
		+def S4_ntstbit_i : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+def S4_ntstbit_r : HexagonBuiltin<"int(int, int)">;
		+def S4_or_andi : HexagonBuiltin<"int(int, int, _Constant int)">;
		+def S4_or_andix : HexagonBuiltin<"int(int, int, _Constant int)">;
		+def S4_or_ori : HexagonBuiltin<"int(int, int, _Constant int)">;
		+def S4_ori_asl_ri : HexagonBuiltin<"int(unsigned _Constant int, int, unsigned _Constant int)">;
		+def S4_ori_lsr_ri : HexagonBuiltin<"int(unsigned _Constant int, int, unsigned _Constant int)">;
		+def S4_parity : HexagonBuiltin<"int(int, int)">;
		+def S4_subaddi : HexagonBuiltin<"int(int, _Constant int, int)">;
		+def S4_subi_asl_ri : HexagonBuiltin<"int(unsigned _Constant int, int, unsigned _Constant int)">;
		+def S4_subi_lsr_ri : HexagonBuiltin<"int(unsigned _Constant int, int, unsigned _Constant int)">;
		+def S4_vrcrotate : HexagonBuiltin<"long long int(long long int, int, unsigned _Constant int)">;
		+def S4_vrcrotate_acc : HexagonBuiltin<"long long int(long long int, long long int, int, unsigned _Constant int)">;
		+def S4_vxaddsubh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S4_vxaddsubhr : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S4_vxaddsubw : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S4_vxsubaddh : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S4_vxsubaddhr : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S4_vxsubaddw : HexagonBuiltin<"long long int(long long int, long long int)">;
		+def S5_asrhub_rnd_sat_goodsyntax : HexagonBuiltin<"int(long long int, unsigned _Constant int)">;
		+def S5_asrhub_sat : HexagonBuiltin<"int(long long int, unsigned _Constant int)">;
		+def S5_popcountp : HexagonBuiltin<"int(long long int)">;
		+def S5_vasrhrnd_goodsyntax : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+def Y2_dccleana : HexagonBuiltin<"void(void *)">;
		+def Y2_dccleaninva : HexagonBuiltin<"void(void *)">;
		+def Y2_dcfetch : HexagonBuiltin<"void(void *)">;
		+def Y2_dcinva : HexagonBuiltin<"void(void *)">;
		+def Y2_dczeroa : HexagonBuiltin<"void(void *)">;
		+def Y4_l2fetch : HexagonBuiltin<"void(void *, int)">;
		+def Y5_l2fetch : HexagonBuiltin<"void(void *, long long int)">;
		+
		+// V60 Scalar Instructions.
		+
		+let Features = V60.Features in {
		+ def S6_rol_i_p : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+ def S6_rol_i_p_acc : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+ def S6_rol_i_p_and : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+ def S6_rol_i_p_nac : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+ def S6_rol_i_p_or : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+ def S6_rol_i_p_xacc : HexagonBuiltin<"long long int(long long int, long long int, unsigned _Constant int)">;
		+ def S6_rol_i_r : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+ def S6_rol_i_r_acc : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+ def S6_rol_i_r_and : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+ def S6_rol_i_r_nac : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+ def S6_rol_i_r_or : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+ def S6_rol_i_r_xacc : HexagonBuiltin<"int(int, int, unsigned _Constant int)">;
		+}
		+
		+// V62 Scalar Instructions.
		+
		+let Features = V62.Features in {
		+ def M6_vabsdiffb : HexagonBuiltin<"long long int(long long int, long long int)">;
		+ def M6_vabsdiffub : HexagonBuiltin<"long long int(long long int, long long int)">;
		+ def S6_vsplatrbp : HexagonBuiltin<"long long int(int)">;
		+ def S6_vtrunehb_ppp : HexagonBuiltin<"long long int(long long int, long long int)">;
		+ def S6_vtrunohb_ppp : HexagonBuiltin<"long long int(long long int, long long int)">;
		+}
		+
		+// V65 Scalar Instructions.
		+
		+let Features = V65.Features in {
		+ def A6_vcmpbeq_notany : HexagonBuiltin<"int(long long int, long long int)">;
		+}
		+
		+// V66 Scalar Instructions.
		+
		+let Features = V66.Features in {
		+ def F2_dfadd : HexagonBuiltin<"double(double, double)">;
		+ def F2_dfsub : HexagonBuiltin<"double(double, double)">;
		+ def M2_mnaci : HexagonBuiltin<"int(int, int, int)">;
		+ def S2_mask : HexagonBuiltin<"int(unsigned _Constant int, unsigned _Constant int)">;
		+}
		+
		+// V67 Scalar Instructions.
		+
		+let Features = "audio" in {
		+ def A7_clip : HexagonBuiltin<"int(int, unsigned _Constant int)">;
		+ def A7_croundd_ri : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+ def A7_croundd_rr : HexagonBuiltin<"long long int(long long int, int)">;
		+ def A7_vclip : HexagonBuiltin<"long long int(long long int, unsigned _Constant int)">;
		+}
		+let Features = V67.Features in {
		+ def F2_dfmax : HexagonBuiltin<"double(double, double)">;
		+ def F2_dfmin : HexagonBuiltin<"double(double, double)">;
		+ def F2_dfmpyfix : HexagonBuiltin<"double(double, double)">;
		+ def F2_dfmpyhh : HexagonBuiltin<"double(double, double, double)">;
		+ def F2_dfmpylh : HexagonBuiltin<"double(double, double, double)">;
		+ def F2_dfmpyll : HexagonBuiltin<"double(double, double)">;
		+}
		+let Features = "audio" in {
		+ def M7_dcmpyiw : HexagonBuiltin<"long long int(long long int, long long int)">;
		+ def M7_dcmpyiw_acc : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+ def M7_dcmpyiwc : HexagonBuiltin<"long long int(long long int, long long int)">;
		+ def M7_dcmpyiwc_acc : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+ def M7_dcmpyrw : HexagonBuiltin<"long long int(long long int, long long int)">;
		+ def M7_dcmpyrw_acc : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+ def M7_dcmpyrwc : HexagonBuiltin<"long long int(long long int, long long int)">;
		+ def M7_dcmpyrwc_acc : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+}
		+let Features = V67.Features in {
		+ def M7_vdmpy : HexagonBuiltin<"long long int(long long int, long long int)">;
		+ def M7_vdmpy_acc : HexagonBuiltin<"long long int(long long int, long long int, long long int)">;
		+}
		+let Features = "audio" in {
		+ def M7_wcmpyiw : HexagonBuiltin<"int(long long int, long long int)">;
		+ def M7_wcmpyiw_rnd : HexagonBuiltin<"int(long long int, long long int)">;
		+ def M7_wcmpyiwc : HexagonBuiltin<"int(long long int, long long int)">;
		+ def M7_wcmpyiwc_rnd : HexagonBuiltin<"int(long long int, long long int)">;
		+ def M7_wcmpyrw : HexagonBuiltin<"int(long long int, long long int)">;
		+ def M7_wcmpyrw_rnd : HexagonBuiltin<"int(long long int, long long int)">;
		+ def M7_wcmpyrwc : HexagonBuiltin<"int(long long int, long long int)">;
		+ def M7_wcmpyrwc_rnd : HexagonBuiltin<"int(long long int, long long int)">;
		+}
		+
		+// V68 Scalar Instructions.
		+
		+let Features = V68.Features in {
		+ def Y6_dmlink : HexagonBuiltin<"void(void *, void *)">;
		+ def Y6_dmpause : HexagonBuiltin<"int()">;
		+ def Y6_dmpoll : HexagonBuiltin<"int()">;
		+ def Y6_dmresume : HexagonBuiltin<"void(void *)">;
		+ def Y6_dmstart : HexagonBuiltin<"void(void *)">;
		+ def Y6_dmwait : HexagonBuiltin<"int()">;
		+}
		+
		+// V60 HVX Instructions.
		+
		+let Features = HVXV60.Features in {
		+ def V6_extractw : HexagonBuiltin<"int(_Vector<16, int>, int)">;
		+ def V6_extractw_128B : HexagonBuiltin<"int(_Vector<32, int>, int)">;
		+ def V6_hi : HexagonBuiltin<"_Vector<16, int>(_Vector<32, int>)">;
		+ def V6_hi_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<64, int>)">;
		+ def V6_lo : HexagonBuiltin<"_Vector<16, int>(_Vector<32, int>)">;
		+ def V6_lo_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<64, int>)">;
		+ def V6_lvsplatw : HexagonBuiltin<"_Vector<16, int>(int)">;
		+ def V6_lvsplatw_128B : HexagonBuiltin<"_Vector<32, int>(int)">;
		+ def V6_pred_and : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<64, bool>)">;
		+ def V6_pred_and_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<128, bool>)">;
		+ def V6_pred_and_n : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<64, bool>)">;
		+ def V6_pred_and_n_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<128, bool>)">;
		+ def V6_pred_not : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>)">;
		+ def V6_pred_not_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>)">;
		+ def V6_pred_or : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<64, bool>)">;
		+ def V6_pred_or_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<128, bool>)">;
		+ def V6_pred_or_n : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<64, bool>)">;
		+ def V6_pred_or_n_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<128, bool>)">;
		+ def V6_pred_scalar2 : HexagonBuiltin<"_Vector<64, bool>(int)">;
		+ def V6_pred_scalar2_128B : HexagonBuiltin<"_Vector<128, bool>(int)">;
		+ def V6_pred_xor : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<64, bool>)">;
		+ def V6_pred_xor_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<128, bool>)">;
		+ def V6_vS32b_nqpred_ai : HexagonBuiltin<"void(_Vector<64, bool>, void *, _Vector<16, int>)">;
		+ def V6_vS32b_nqpred_ai_128B : HexagonBuiltin<"void(_Vector<128, bool>, void *, _Vector<32, int>)">;
		+ def V6_vS32b_nt_nqpred_ai : HexagonBuiltin<"void(_Vector<64, bool>, void *, _Vector<16, int>)">;
		+ def V6_vS32b_nt_nqpred_ai_128B : HexagonBuiltin<"void(_Vector<128, bool>, void *, _Vector<32, int>)">;
		+ def V6_vS32b_nt_qpred_ai : HexagonBuiltin<"void(_Vector<64, bool>, void *, _Vector<16, int>)">;
		+ def V6_vS32b_nt_qpred_ai_128B : HexagonBuiltin<"void(_Vector<128, bool>, void *, _Vector<32, int>)">;
		+ def V6_vS32b_qpred_ai : HexagonBuiltin<"void(_Vector<64, bool>, void *, _Vector<16, int>)">;
		+ def V6_vS32b_qpred_ai_128B : HexagonBuiltin<"void(_Vector<128, bool>, void *, _Vector<32, int>)">;
		+ def V6_vabsdiffh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vabsdiffh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vabsdiffub : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vabsdiffub_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vabsdiffuh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vabsdiffuh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vabsdiffw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vabsdiffw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vabsh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vabsh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vabsh_sat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vabsh_sat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vabsw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vabsw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vabsw_sat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vabsw_sat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vaddb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddb_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddb_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vaddbnq : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddbnq_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddbq : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddbq_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddh_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddh_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vaddhnq : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddhnq_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddhq : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddhq_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddhsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddhsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddhsat_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddhsat_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vaddhw : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddhw_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddubh : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddubh_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddubsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddubsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddubsat_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddubsat_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vadduhsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadduhsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vadduhsat_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vadduhsat_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vadduhw : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadduhw_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddw_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddw_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vaddwnq : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddwnq_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddwq : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddwq_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddwsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddwsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddwsat_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddwsat_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_valignb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_valignb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_valignbi : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, unsigned _Constant int)">;
		+ def V6_valignbi_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, unsigned _Constant int)">;
		+ def V6_vand : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vand_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vandqrt : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, int)">;
		+ def V6_vandqrt_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, int)">;
		+ def V6_vandqrt_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<64, bool>, int)">;
		+ def V6_vandqrt_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<128, bool>, int)">;
		+ def V6_vandvrt : HexagonBuiltin<"_Vector<64, bool>(_Vector<16, int>, int)">;
		+ def V6_vandvrt_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<32, int>, int)">;
		+ def V6_vandvrt_acc : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, int)">;
		+ def V6_vandvrt_acc_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, int)">;
		+ def V6_vaslh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vaslh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vaslhv : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaslhv_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaslw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vaslw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vaslw_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vaslw_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vaslwv : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaslwv_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vasrh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vasrh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vasrhbrndsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasrhbrndsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vasrhubrndsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasrhubrndsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vasrhubsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasrhubsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vasrhv : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vasrhv_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vasrw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vasrw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vasrw_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasrw_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vasrwh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasrwh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vasrwhrndsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasrwhrndsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vasrwhsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasrwhsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vasrwuhsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasrwuhsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vasrwv : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vasrwv_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vassign : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vassign_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vassignp : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vassignp_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>)">;
		+ def V6_vavgh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vavgh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vavghrnd : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vavghrnd_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vavgub : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vavgub_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vavgubrnd : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vavgubrnd_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vavguh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vavguh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vavguhrnd : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vavguhrnd_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vavgw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vavgw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vavgwrnd : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vavgwrnd_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vcl0h : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vcl0h_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vcl0w : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vcl0w_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vcombine : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vcombine_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vd0 : HexagonBuiltin<"_Vector<16, int>()">;
		+ def V6_vd0_128B : HexagonBuiltin<"_Vector<32, int>()">;
		+ def V6_vdealb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vdealb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vdealb4w : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vdealb4w_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vdealh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vdealh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vdealvdd : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vdealvdd_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vdelta : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vdelta_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vdmpybus : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vdmpybus_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vdmpybus_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vdmpybus_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vdmpybus_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vdmpybus_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, int)">;
		+ def V6_vdmpybus_dv_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vdmpybus_dv_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, int)">;
		+ def V6_vdmpyhb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vdmpyhb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vdmpyhb_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vdmpyhb_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vdmpyhb_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vdmpyhb_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, int)">;
		+ def V6_vdmpyhb_dv_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vdmpyhb_dv_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, int)">;
		+ def V6_vdmpyhisat : HexagonBuiltin<"_Vector<16, int>(_Vector<32, int>, int)">;
		+ def V6_vdmpyhisat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<64, int>, int)">;
		+ def V6_vdmpyhisat_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<32, int>, int)">;
		+ def V6_vdmpyhisat_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<64, int>, int)">;
		+ def V6_vdmpyhsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vdmpyhsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vdmpyhsat_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vdmpyhsat_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vdmpyhsuisat : HexagonBuiltin<"_Vector<16, int>(_Vector<32, int>, int)">;
		+ def V6_vdmpyhsuisat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<64, int>, int)">;
		+ def V6_vdmpyhsuisat_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<32, int>, int)">;
		+ def V6_vdmpyhsuisat_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<64, int>, int)">;
		+ def V6_vdmpyhsusat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vdmpyhsusat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vdmpyhsusat_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vdmpyhsusat_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vdmpyhvsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vdmpyhvsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vdmpyhvsat_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vdmpyhvsat_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vdsaduh : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vdsaduh_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, int)">;
		+ def V6_vdsaduh_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vdsaduh_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, int)">;
		+ def V6_veqb : HexagonBuiltin<"_Vector<64, bool>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_veqb_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_veqb_and : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_veqb_and_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_veqb_or : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_veqb_or_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_veqb_xor : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_veqb_xor_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_veqh : HexagonBuiltin<"_Vector<64, bool>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_veqh_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_veqh_and : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_veqh_and_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_veqh_or : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_veqh_or_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_veqh_xor : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_veqh_xor_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_veqw : HexagonBuiltin<"_Vector<64, bool>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_veqw_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_veqw_and : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_veqw_and_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_veqw_or : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_veqw_or_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_veqw_xor : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_veqw_xor_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtb : HexagonBuiltin<"_Vector<64, bool>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtb_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtb_and : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtb_and_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtb_or : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtb_or_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtb_xor : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtb_xor_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgth : HexagonBuiltin<"_Vector<64, bool>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgth_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgth_and : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgth_and_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgth_or : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgth_or_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgth_xor : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgth_xor_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtub : HexagonBuiltin<"_Vector<64, bool>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtub_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtub_and : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtub_and_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtub_or : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtub_or_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtub_xor : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtub_xor_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtuh : HexagonBuiltin<"_Vector<64, bool>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtuh_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtuh_and : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtuh_and_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtuh_or : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtuh_or_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtuh_xor : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtuh_xor_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtuw : HexagonBuiltin<"_Vector<64, bool>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtuw_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtuw_and : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtuw_and_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtuw_or : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtuw_or_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtuw_xor : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtuw_xor_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtw : HexagonBuiltin<"_Vector<64, bool>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtw_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtw_and : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtw_and_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtw_or : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtw_or_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtw_xor : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtw_xor_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vinsertwr : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vinsertwr_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vlalignb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vlalignb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vlalignbi : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, unsigned _Constant int)">;
		+ def V6_vlalignbi_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, unsigned _Constant int)">;
		+ def V6_vlsrh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vlsrh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vlsrhv : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vlsrhv_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vlsrw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vlsrw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vlsrwv : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vlsrwv_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vlutvvb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vlutvvb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vlutvvb_oracc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vlutvvb_oracc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vlutvwh : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vlutvwh_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vlutvwh_oracc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vlutvwh_oracc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vmaxh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmaxh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmaxub : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmaxub_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmaxuh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmaxuh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmaxw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmaxw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vminh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vminh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vminub : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vminub_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vminuh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vminuh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vminw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vminw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpabus : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vmpabus_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, int)">;
		+ def V6_vmpabus_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vmpabus_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, int)">;
		+ def V6_vmpabusv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpabusv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vmpabuuv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpabuuv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vmpahb : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vmpahb_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, int)">;
		+ def V6_vmpahb_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vmpahb_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, int)">;
		+ def V6_vmpybus : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, int)">;
		+ def V6_vmpybus_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, int)">;
		+ def V6_vmpybus_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, int)">;
		+ def V6_vmpybus_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, int)">;
		+ def V6_vmpybusv : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpybusv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpybusv_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpybusv_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpybv : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpybv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpybv_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpybv_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyewuh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyewuh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyh : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, int)">;
		+ def V6_vmpyh_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, int)">;
		+ def V6_vmpyhsat_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, int)">;
		+ def V6_vmpyhsat_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, int)">;
		+ def V6_vmpyhsrs : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vmpyhsrs_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vmpyhss : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vmpyhss_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vmpyhus : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyhus_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyhus_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyhus_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyhv : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyhv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyhv_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyhv_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyhvsrs : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyhvsrs_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyieoh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyieoh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyiewh_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyiewh_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyiewuh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyiewuh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyiewuh_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyiewuh_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyih : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyih_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyih_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyih_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyihb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vmpyihb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vmpyihb_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vmpyihb_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vmpyiowh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyiowh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyiwb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vmpyiwb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vmpyiwb_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vmpyiwb_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vmpyiwh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vmpyiwh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vmpyiwh_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vmpyiwh_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vmpyowh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyowh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyowh_rnd : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyowh_rnd_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyowh_rnd_sacc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyowh_rnd_sacc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyowh_sacc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyowh_sacc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyub : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, int)">;
		+ def V6_vmpyub_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, int)">;
		+ def V6_vmpyub_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, int)">;
		+ def V6_vmpyub_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, int)">;
		+ def V6_vmpyubv : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyubv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyubv_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyubv_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyuh : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, int)">;
		+ def V6_vmpyuh_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, int)">;
		+ def V6_vmpyuh_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, int)">;
		+ def V6_vmpyuh_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, int)">;
		+ def V6_vmpyuhv : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyuhv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyuhv_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyuhv_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmux : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmux_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vnavgh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vnavgh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vnavgub : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vnavgub_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vnavgw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vnavgw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vnormamth : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vnormamth_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vnormamtw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vnormamtw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vnot : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vnot_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vor : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vor_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vpackeb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vpackeb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vpackeh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vpackeh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vpackhb_sat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vpackhb_sat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vpackhub_sat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vpackhub_sat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vpackob : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vpackob_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vpackoh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vpackoh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vpackwh_sat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vpackwh_sat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vpackwuh_sat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vpackwuh_sat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vpopcounth : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vpopcounth_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vrdelta : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vrdelta_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vrmpybus : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vrmpybus_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vrmpybus_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vrmpybus_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vrmpybusi : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int, unsigned _Constant int)">;
		+ def V6_vrmpybusi_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, int, unsigned _Constant int)">;
		+ def V6_vrmpybusi_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int, unsigned _Constant int)">;
		+ def V6_vrmpybusi_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, int, unsigned _Constant int)">;
		+ def V6_vrmpybusv : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vrmpybusv_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vrmpybusv_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vrmpybusv_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vrmpybv : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vrmpybv_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vrmpybv_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vrmpybv_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vrmpyub : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vrmpyub_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vrmpyub_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vrmpyub_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vrmpyubi : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int, unsigned _Constant int)">;
		+ def V6_vrmpyubi_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, int, unsigned _Constant int)">;
		+ def V6_vrmpyubi_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int, unsigned _Constant int)">;
		+ def V6_vrmpyubi_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, int, unsigned _Constant int)">;
		+ def V6_vrmpyubv : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vrmpyubv_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vrmpyubv_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vrmpyubv_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vror : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vror_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vroundhb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vroundhb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vroundhub : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vroundhub_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vroundwh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vroundwh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vroundwuh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vroundwuh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vrsadubi : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int, unsigned _Constant int)">;
		+ def V6_vrsadubi_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, int, unsigned _Constant int)">;
		+ def V6_vrsadubi_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int, unsigned _Constant int)">;
		+ def V6_vrsadubi_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, int, unsigned _Constant int)">;
		+ def V6_vsathub : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsathub_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsatwh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsatwh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsb : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>)">;
		+ def V6_vsb_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>)">;
		+ def V6_vsh : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>)">;
		+ def V6_vsh_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>)">;
		+ def V6_vshufeh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vshufeh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vshuffb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vshuffb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vshuffeb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vshuffeb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vshuffh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vshuffh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vshuffob : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vshuffob_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vshuffvdd : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vshuffvdd_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vshufoeb : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vshufoeb_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vshufoeh : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vshufoeh_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vshufoh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vshufoh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubb_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubb_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vsubbnq : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubbnq_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubbq : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubbq_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubh_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubh_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vsubhnq : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubhnq_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubhq : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubhq_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubhsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubhsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubhsat_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubhsat_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vsubhw : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubhw_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsububh : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsububh_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsububsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsububsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsububsat_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsububsat_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vsubuhsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubuhsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubuhsat_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubuhsat_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vsubuhw : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubuhw_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubw_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubw_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vsubwnq : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubwnq_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubwq : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubwq_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubwsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubwsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubwsat_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubwsat_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vswap : HexagonBuiltin<"_Vector<32, int>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vswap_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vtmpyb : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vtmpyb_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, int)">;
		+ def V6_vtmpyb_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vtmpyb_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, int)">;
		+ def V6_vtmpybus : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vtmpybus_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, int)">;
		+ def V6_vtmpybus_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vtmpybus_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, int)">;
		+ def V6_vtmpyhb : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vtmpyhb_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, int)">;
		+ def V6_vtmpyhb_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vtmpyhb_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, int)">;
		+ def V6_vunpackb : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>)">;
		+ def V6_vunpackb_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>)">;
		+ def V6_vunpackh : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>)">;
		+ def V6_vunpackh_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>)">;
		+ def V6_vunpackob : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>)">;
		+ def V6_vunpackob_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>)">;
		+ def V6_vunpackoh : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>)">;
		+ def V6_vunpackoh_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>)">;
		+ def V6_vunpackub : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>)">;
		+ def V6_vunpackub_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>)">;
		+ def V6_vunpackuh : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>)">;
		+ def V6_vunpackuh_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>)">;
		+ def V6_vxor : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vxor_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vzb : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>)">;
		+ def V6_vzb_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>)">;
		+ def V6_vzh : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>)">;
		+ def V6_vzh_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>)">;
		+}
		+
		+// V62 HVX Instructions.
		+
		+let Features = HVXV62.Features in {
		+ def V6_lvsplatb : HexagonBuiltin<"_Vector<16, int>(int)">;
		+ def V6_lvsplatb_128B : HexagonBuiltin<"_Vector<32, int>(int)">;
		+ def V6_lvsplath : HexagonBuiltin<"_Vector<16, int>(int)">;
		+ def V6_lvsplath_128B : HexagonBuiltin<"_Vector<32, int>(int)">;
		+ def V6_pred_scalar2v2 : HexagonBuiltin<"_Vector<64, bool>(int)">;
		+ def V6_pred_scalar2v2_128B : HexagonBuiltin<"_Vector<128, bool>(int)">;
		+ def V6_shuffeqh : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<64, bool>)">;
		+ def V6_shuffeqh_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<128, bool>)">;
		+ def V6_shuffeqw : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<64, bool>)">;
		+ def V6_shuffeqw_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<128, bool>)">;
		+ def V6_vaddbsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddbsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddbsat_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddbsat_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vaddcarry : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, void *)">;
		+ def V6_vaddcarry_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, void *)">;
		+ def V6_vaddclbh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddclbh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddclbw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddclbw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddhw_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddhw_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddubh_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddubh_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vaddububb_sat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vaddububb_sat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vadduhw_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadduhw_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vadduwsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadduwsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vadduwsat_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vadduwsat_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vandnqrt : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, int)">;
		+ def V6_vandnqrt_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, int)">;
		+ def V6_vandnqrt_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<64, bool>, int)">;
		+ def V6_vandnqrt_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<128, bool>, int)">;
		+ def V6_vandvnqv : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>)">;
		+ def V6_vandvnqv_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>)">;
		+ def V6_vandvqv : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>, _Vector<16, int>)">;
		+ def V6_vandvqv_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>, _Vector<32, int>)">;
		+ def V6_vasrhbsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasrhbsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vasruwuhrndsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasruwuhrndsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vasrwuhrndsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasrwuhrndsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vlsrb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vlsrb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vlutvvb_nm : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vlutvvb_nm_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vlutvvb_oracci : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>, unsigned _Constant int)">;
		+ def V6_vlutvvb_oracci_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>, unsigned _Constant int)">;
		+ def V6_vlutvvbi : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, unsigned _Constant int)">;
		+ def V6_vlutvvbi_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, unsigned _Constant int)">;
		+ def V6_vlutvwh_nm : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vlutvwh_nm_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vlutvwh_oracci : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>, unsigned _Constant int)">;
		+ def V6_vlutvwh_oracci_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>, unsigned _Constant int)">;
		+ def V6_vlutvwhi : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>, unsigned _Constant int)">;
		+ def V6_vlutvwhi_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>, unsigned _Constant int)">;
		+ def V6_vmaxb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmaxb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vminb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vminb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpauhb : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vmpauhb_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, int)">;
		+ def V6_vmpauhb_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vmpauhb_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, int)">;
		+ def V6_vmpyewuh_64 : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyewuh_64_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpyiwub : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vmpyiwub_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vmpyiwub_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vmpyiwub_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vmpyowh_64_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyowh_64_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vrounduhub : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vrounduhub_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vrounduwuh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vrounduwuh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsatuwuh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsatuwuh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubbsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubbsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubbsat_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubbsat_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+ def V6_vsubcarry : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, void *)">;
		+ def V6_vsubcarry_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, void *)">;
		+ def V6_vsubububb_sat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubububb_sat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubuwsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsubuwsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubuwsat_dv : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubuwsat_dv_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>)">;
		+}
		+
		+// V65 HVX Instructions.
		+
		+let Features = HVXV65.Features in {
		+ def V6_vabsb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vabsb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vabsb_sat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vabsb_sat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vaslh_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vaslh_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vasrh_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasrh_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vasruhubrndsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasruhubrndsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vasruhubsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasruhubsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vasruwuhsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vasruwuhsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vavgb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vavgb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vavgbrnd : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vavgbrnd_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vavguw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vavguw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vavguwrnd : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vavguwrnd_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vdd0 : HexagonBuiltin<"_Vector<32, int>()">;
		+ def V6_vdd0_128B : HexagonBuiltin<"_Vector<64, int>()">;
		+ def V6_vgathermh : HexagonBuiltin<"void(void *, int, int, _Vector<16, int>)">;
		+ def V6_vgathermh_128B : HexagonBuiltin<"void(void *, int, int, _Vector<32, int>)">;
		+ def V6_vgathermhq : HexagonBuiltin<"void(void *, _Vector<64, bool>, int, int, _Vector<16, int>)">;
		+ def V6_vgathermhq_128B : HexagonBuiltin<"void(void *, _Vector<128, bool>, int, int, _Vector<32, int>)">;
		+ def V6_vgathermhw : HexagonBuiltin<"void(void *, int, int, _Vector<32, int>)">;
		+ def V6_vgathermhw_128B : HexagonBuiltin<"void(void *, int, int, _Vector<64, int>)">;
		+ def V6_vgathermhwq : HexagonBuiltin<"void(void *, _Vector<64, bool>, int, int, _Vector<32, int>)">;
		+ def V6_vgathermhwq_128B : HexagonBuiltin<"void(void *, _Vector<128, bool>, int, int, _Vector<64, int>)">;
		+ def V6_vgathermw : HexagonBuiltin<"void(void *, int, int, _Vector<16, int>)">;
		+ def V6_vgathermw_128B : HexagonBuiltin<"void(void *, int, int, _Vector<32, int>)">;
		+ def V6_vgathermwq : HexagonBuiltin<"void(void *, _Vector<64, bool>, int, int, _Vector<16, int>)">;
		+ def V6_vgathermwq_128B : HexagonBuiltin<"void(void *, _Vector<128, bool>, int, int, _Vector<32, int>)">;
		+ def V6_vlut4 : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, long long int)">;
		+ def V6_vlut4_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, long long int)">;
		+ def V6_vmpabuu : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vmpabuu_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, int)">;
		+ def V6_vmpabuu_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vmpabuu_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, int)">;
		+ def V6_vmpahhsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, long long int)">;
		+ def V6_vmpahhsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, long long int)">;
		+ def V6_vmpauhuhsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, long long int)">;
		+ def V6_vmpauhuhsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, long long int)">;
		+ def V6_vmpsuhuhsat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, long long int)">;
		+ def V6_vmpsuhuhsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, long long int)">;
		+ def V6_vmpyh_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, int)">;
		+ def V6_vmpyh_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, int)">;
		+ def V6_vmpyuhe : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vmpyuhe_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vmpyuhe_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_vmpyuhe_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_vnavgb : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vnavgb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vprefixqb : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>)">;
		+ def V6_vprefixqb_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>)">;
		+ def V6_vprefixqh : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>)">;
		+ def V6_vprefixqh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>)">;
		+ def V6_vprefixqw : HexagonBuiltin<"_Vector<16, int>(_Vector<64, bool>)">;
		+ def V6_vprefixqw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<128, bool>)">;
		+ def V6_vscattermh : HexagonBuiltin<"void(int, int, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vscattermh_128B : HexagonBuiltin<"void(int, int, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vscattermh_add : HexagonBuiltin<"void(int, int, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vscattermh_add_128B : HexagonBuiltin<"void(int, int, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vscattermhq : HexagonBuiltin<"void(_Vector<64, bool>, int, int, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vscattermhq_128B : HexagonBuiltin<"void(_Vector<128, bool>, int, int, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vscattermhw : HexagonBuiltin<"void(int, int, _Vector<32, int>, _Vector<16, int>)">;
		+ def V6_vscattermhw_128B : HexagonBuiltin<"void(int, int, _Vector<64, int>, _Vector<32, int>)">;
		+ def V6_vscattermhw_add : HexagonBuiltin<"void(int, int, _Vector<32, int>, _Vector<16, int>)">;
		+ def V6_vscattermhw_add_128B : HexagonBuiltin<"void(int, int, _Vector<64, int>, _Vector<32, int>)">;
		+ def V6_vscattermhwq : HexagonBuiltin<"void(_Vector<64, bool>, int, int, _Vector<32, int>, _Vector<16, int>)">;
		+ def V6_vscattermhwq_128B : HexagonBuiltin<"void(_Vector<128, bool>, int, int, _Vector<64, int>, _Vector<32, int>)">;
		+ def V6_vscattermw : HexagonBuiltin<"void(int, int, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vscattermw_128B : HexagonBuiltin<"void(int, int, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vscattermw_add : HexagonBuiltin<"void(int, int, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vscattermw_add_128B : HexagonBuiltin<"void(int, int, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vscattermwq : HexagonBuiltin<"void(_Vector<64, bool>, int, int, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vscattermwq_128B : HexagonBuiltin<"void(_Vector<128, bool>, int, int, _Vector<32, int>, _Vector<32, int>)">;
		+}
		+
		+// V66 HVX Instructions.
		+
		+let Features = HVXV66.Features in {
		+ def V6_vaddcarryo : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, void *)">;
		+ def V6_vaddcarryo_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, void *)">;
		+ def V6_vaddcarrysat : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<64, bool>)">;
		+ def V6_vaddcarrysat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<128, bool>)">;
		+ def V6_vasr_into : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vasr_into_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vrotr : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vrotr_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsatdw : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsatdw_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsubcarryo : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, void *)">;
		+ def V6_vsubcarryo_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, void *)">;
		+}
		+
		+// V68 HVX Instructions.
		+
		+let Features = HVXV68.Features in {
		+ def V6_v6mpyhubs10 : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, unsigned _Constant int)">;
		+ def V6_v6mpyhubs10_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, unsigned _Constant int)">;
		+ def V6_v6mpyhubs10_vxx : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>, unsigned _Constant int)">;
		+ def V6_v6mpyhubs10_vxx_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, _Vector<64, int>, unsigned _Constant int)">;
		+ def V6_v6mpyvubs10 : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, unsigned _Constant int)">;
		+ def V6_v6mpyvubs10_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, unsigned _Constant int)">;
		+ def V6_v6mpyvubs10_vxx : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>, unsigned _Constant int)">;
		+ def V6_v6mpyvubs10_vxx_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<64, int>, _Vector<64, int>, unsigned _Constant int)">;
		+ def V6_vabs_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vabs_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vabs_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vabs_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vadd_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadd_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vadd_hf_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadd_hf_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vadd_qf16 : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadd_qf16_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vadd_qf16_mix : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadd_qf16_mix_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vadd_qf32 : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadd_qf32_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vadd_qf32_mix : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadd_qf32_mix_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vadd_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadd_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vadd_sf_hf : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadd_sf_hf_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vadd_sf_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadd_sf_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vassign_fp : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vassign_fp_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vconv_hf_qf16 : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vconv_hf_qf16_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vconv_hf_qf32 : HexagonBuiltin<"_Vector<16, int>(_Vector<32, int>)">;
		+ def V6_vconv_hf_qf32_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<64, int>)">;
		+ def V6_vconv_sf_qf32 : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vconv_sf_qf32_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vcvt_b_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vcvt_b_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vcvt_h_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vcvt_h_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vcvt_hf_b : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>)">;
		+ def V6_vcvt_hf_b_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>)">;
		+ def V6_vcvt_hf_h : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vcvt_hf_h_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vcvt_hf_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vcvt_hf_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vcvt_hf_ub : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>)">;
		+ def V6_vcvt_hf_ub_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>)">;
		+ def V6_vcvt_hf_uh : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vcvt_hf_uh_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vcvt_sf_hf : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>)">;
		+ def V6_vcvt_sf_hf_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>)">;
		+ def V6_vcvt_ub_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vcvt_ub_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vcvt_uh_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vcvt_uh_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vdmpy_sf_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vdmpy_sf_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vdmpy_sf_hf_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vdmpy_sf_hf_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vfmax_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vfmax_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vfmax_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vfmax_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vfmin_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vfmin_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vfmin_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vfmin_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vfneg_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vfneg_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vfneg_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vfneg_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vgthf : HexagonBuiltin<"_Vector<64, bool>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgthf_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgthf_and : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgthf_and_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgthf_or : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgthf_or_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgthf_xor : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgthf_xor_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtsf : HexagonBuiltin<"_Vector<64, bool>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtsf_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtsf_and : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtsf_and_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtsf_or : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtsf_or_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtsf_xor : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtsf_xor_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmax_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmax_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmax_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmax_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmin_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmin_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmin_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmin_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_hf_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_hf_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_hf_hf_acc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_hf_hf_acc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_qf16 : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_qf16_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_qf16_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_qf16_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_qf16_mix_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_qf16_mix_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_qf32 : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_qf32_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_qf32_hf : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_qf32_hf_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_qf32_mix_hf : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_qf32_mix_hf_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_qf32_qf16 : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_qf32_qf16_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_qf32_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_qf32_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_sf_hf : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_sf_hf_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_sf_hf_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_sf_hf_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_sf_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_sf_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsub_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsub_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsub_hf_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsub_hf_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsub_qf16 : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsub_qf16_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsub_qf16_mix : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsub_qf16_mix_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsub_qf32 : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsub_qf32_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsub_qf32_mix : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsub_qf32_mix_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsub_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsub_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsub_sf_hf : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsub_sf_hf_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsub_sf_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsub_sf_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+}
		+
		+// V69 HVX Instructions.
		+
		+let Features = HVXV69.Features in {
		+ def V6_vasrvuhubrndsat : HexagonBuiltin<"_Vector<16, int>(_Vector<32, int>, _Vector<16, int>)">;
		+ def V6_vasrvuhubrndsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<64, int>, _Vector<32, int>)">;
		+ def V6_vasrvuhubsat : HexagonBuiltin<"_Vector<16, int>(_Vector<32, int>, _Vector<16, int>)">;
		+ def V6_vasrvuhubsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<64, int>, _Vector<32, int>)">;
		+ def V6_vasrvwuhrndsat : HexagonBuiltin<"_Vector<16, int>(_Vector<32, int>, _Vector<16, int>)">;
		+ def V6_vasrvwuhrndsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<64, int>, _Vector<32, int>)">;
		+ def V6_vasrvwuhsat : HexagonBuiltin<"_Vector<16, int>(_Vector<32, int>, _Vector<16, int>)">;
		+ def V6_vasrvwuhsat_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<64, int>, _Vector<32, int>)">;
		+ def V6_vmpyuhvs : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpyuhvs_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+}
		+
		+// V73 HVX Instructions.
		+
		+let Features = HVXV73.Features in {
		+ def V6_vadd_sf_bf : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadd_sf_bf_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vconv_h_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vconv_h_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vconv_hf_h : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vconv_hf_h_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vconv_sf_w : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vconv_sf_w_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vconv_w_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vconv_w_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vcvt_bf_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vcvt_bf_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtbf : HexagonBuiltin<"_Vector<64, bool>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtbf_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtbf_and : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtbf_and_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtbf_or : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtbf_or_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vgtbf_xor : HexagonBuiltin<"_Vector<64, bool>(_Vector<64, bool>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vgtbf_xor_128B : HexagonBuiltin<"_Vector<128, bool>(_Vector<128, bool>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmax_bf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmax_bf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmin_bf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmin_bf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_sf_bf : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_sf_bf_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_sf_bf_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_sf_bf_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vsub_sf_bf : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsub_sf_bf_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+}
		+
		+// V79 HVX Instructions.
		+
		+let Features = HVXV79.Features in {
		+ def V6_get_qfext : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_get_qfext_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_get_qfext_oracc : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, int)">;
		+ def V6_get_qfext_oracc_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>, int)">;
		+ def V6_set_qfext : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_set_qfext_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vabs_f8 : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vabs_f8_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vadd_hf_f8 : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vadd_hf_f8_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vcvt2_b_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vcvt2_b_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vcvt2_hf_b : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>)">;
		+ def V6_vcvt2_hf_b_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>)">;
		+ def V6_vcvt2_hf_ub : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>)">;
		+ def V6_vcvt2_hf_ub_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>)">;
		+ def V6_vcvt2_ub_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vcvt2_ub_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vcvt_f8_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vcvt_f8_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vcvt_hf_f8 : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>)">;
		+ def V6_vcvt_hf_f8_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>)">;
		+ def V6_vfmax_f8 : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vfmax_f8_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vfmin_f8 : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vfmin_f8_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vfneg_f8 : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>)">;
		+ def V6_vfneg_f8_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>)">;
		+ def V6_vmerge_qf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmerge_qf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_hf_f8 : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_hf_f8_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_hf_f8_acc : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, _Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vmpy_hf_f8_acc_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<64, int>, _Vector<32, int>, _Vector<32, int>)">;
		+ def V6_vmpy_rt_hf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vmpy_rt_hf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vmpy_rt_qf16 : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vmpy_rt_qf16_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vmpy_rt_sf : HexagonBuiltin<"_Vector<16, int>(_Vector<16, int>, int)">;
		+ def V6_vmpy_rt_sf_128B : HexagonBuiltin<"_Vector<32, int>(_Vector<32, int>, int)">;
		+ def V6_vsub_hf_f8 : HexagonBuiltin<"_Vector<32, int>(_Vector<16, int>, _Vector<16, int>)">;
		+ def V6_vsub_hf_f8_128B : HexagonBuiltin<"_Vector<64, int>(_Vector<32, int>, _Vector<32, int>)">;
		+}

clang/include/clang/Basic/BuiltinsHexagonDep.def→/dev/null

		@@ -1,1970 +0,0 @@
		-//===----------------------------------------------------------------------===//
		-//
		-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
		-// See https://llvm.org/LICENSE.txt for license information.
		-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
		-//
		-//===----------------------------------------------------------------------===//
		-// Automatically generated file, do not edit!
		-//===----------------------------------------------------------------------===//
		-
		-
		-// V5 Scalar Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_abs, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_absp, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_abssat, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_add, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addh_h16_hh, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addh_h16_hl, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addh_h16_lh, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addh_h16_ll, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addh_h16_sat_hh, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addh_h16_sat_hl, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addh_h16_sat_lh, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addh_h16_sat_ll, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addh_l16_hl, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addh_l16_ll, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addh_l16_sat_hl, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addh_l16_sat_ll, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addi, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addp, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addpsat, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addsat, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_addsp, "LLiiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_and, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_andir, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_andp, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_aslh, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_asrh, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_combine_hh, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_combine_hl, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_combine_lh, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_combine_ll, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_combineii, "LLiIiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_combinew, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_max, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_maxp, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_maxu, "Uiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_maxup, "ULLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_min, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_minp, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_minu, "Uiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_minup, "ULLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_neg, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_negp, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_negsat, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_not, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_notp, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_or, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_orir, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_orp, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_roundsat, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_sat, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_satb, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_sath, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_satub, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_satuh, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_sub, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subh_h16_hh, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subh_h16_hl, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subh_h16_lh, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subh_h16_ll, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subh_h16_sat_hh, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subh_h16_sat_hl, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subh_h16_sat_lh, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subh_h16_sat_ll, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subh_l16_hl, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subh_l16_ll, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subh_l16_sat_hl, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subh_l16_sat_ll, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subp, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subri, "iIii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_subsat, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_svaddh, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_svaddhs, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_svadduhs, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_svavgh, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_svavghs, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_svnavgh, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_svsubh, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_svsubhs, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_svsubuhs, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_swiz, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_sxtb, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_sxth, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_sxtw, "LLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_tfr, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_tfrih, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_tfril, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_tfrp, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_tfrpi, "LLiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_tfrsi, "iIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vabsh, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vabshsat, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vabsw, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vabswsat, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vaddb_map, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vaddh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vaddhs, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vaddub, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vaddubs, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vadduhs, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vaddw, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vaddws, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vavgh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vavghcr, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vavghr, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vavgub, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vavgubr, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vavguh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vavguhr, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vavguw, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vavguwr, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vavgw, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vavgwcr, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vavgwr, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vcmpbeq, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vcmpbgtu, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vcmpheq, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vcmphgt, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vcmphgtu, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vcmpweq, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vcmpwgt, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vcmpwgtu, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vconj, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vmaxb, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vmaxh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vmaxub, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vmaxuh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vmaxuw, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vmaxw, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vminb, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vminh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vminub, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vminuh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vminuw, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vminw, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vnavgh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vnavghcr, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vnavghr, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vnavgw, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vnavgwcr, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vnavgwr, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vraddub, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vraddub_acc, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vrsadub, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vrsadub_acc, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vsubb_map, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vsubh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vsubhs, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vsubub, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vsububs, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vsubuhs, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vsubw, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_vsubws, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_xor, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_xorp, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_zxtb, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A2_zxth, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_andn, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_andnp, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_bitsplit, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_bitspliti, "LLiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_boundscheck, "iiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_cmpbeq, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_cmpbeqi, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_cmpbgt, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_cmpbgti, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_cmpbgtu, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_cmpbgtui, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_cmpheq, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_cmpheqi, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_cmphgt, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_cmphgti, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_cmphgtu, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_cmphgtui, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_combineir, "LLiIii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_combineri, "LLiiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_cround_ri, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_cround_rr, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_modwrapu, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_orn, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_ornp, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_rcmpeq, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_rcmpeqi, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_rcmpneq, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_rcmpneqi, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_round_ri, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_round_ri_sat, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_round_rr, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_round_rr_sat, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_tlbmatch, "iLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vcmpbeq_any, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vcmpbeqi, "iLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vcmpbgt, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vcmpbgti, "iLLiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vcmpbgtui, "iLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vcmpheqi, "iLLiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vcmphgti, "iLLiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vcmphgtui, "iLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vcmpweqi, "iLLiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vcmpwgti, "iLLiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vcmpwgtui, "iLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vrmaxh, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vrmaxuh, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vrmaxuw, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vrmaxw, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vrminh, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vrminuh, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vrminuw, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A4_vrminw, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_A5_vaddhubs, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_all8, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_and, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_andn, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_any8, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_bitsclr, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_bitsclri, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_bitsset, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpeq, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpeqi, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpeqp, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpgei, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpgeui, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpgt, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpgti, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpgtp, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpgtu, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpgtui, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpgtup, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_cmplt, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpltu, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_mask, "LLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_mux, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_muxii, "iiIiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_muxir, "iiiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_muxri, "iiIii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_not, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_or, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_orn, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_pxfer_map, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_tfrpr, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_tfrrp, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_vitpack, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_vmux, "LLiiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C2_xor, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_and_and, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_and_andn, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_and_or, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_and_orn, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_cmplte, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_cmpltei, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_cmplteu, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_cmplteui, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_cmpneq, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_cmpneqi, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_fastcorner9, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_fastcorner9_not, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_nbitsclr, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_nbitsclri, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_nbitsset, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_or_and, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_or_andn, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_or_or, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_C4_or_orn, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_d2df, "dLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_d2sf, "fLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_df2d, "LLid", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_df2d_chop, "LLid", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_df2sf, "fd", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_df2ud, "LLid", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_df2ud_chop, "LLid", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_df2uw, "id", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_df2uw_chop, "id", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_df2w, "id", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_df2w_chop, "id", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_sf2d, "LLif", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_sf2d_chop, "LLif", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_sf2df, "df", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_sf2ud, "LLif", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_sf2ud_chop, "LLif", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_sf2uw, "if", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_sf2uw_chop, "if", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_sf2w, "if", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_sf2w_chop, "if", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_ud2df, "dLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_ud2sf, "fLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_uw2df, "di", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_uw2sf, "fi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_w2df, "di", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_conv_w2sf, "fi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfclass, "idUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfcmpeq, "idd", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfcmpge, "idd", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfcmpgt, "idd", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfcmpuo, "idd", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfimm_n, "dUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfimm_p, "dUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sfadd, "fff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sfclass, "ifUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sfcmpeq, "iff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sfcmpge, "iff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sfcmpgt, "iff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sfcmpuo, "iff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sffixupd, "fff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sffixupn, "fff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sffixupr, "ff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sffma, "ffff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sffma_lib, "ffff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sffma_sc, "ffffi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sffms, "ffff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sffms_lib, "ffff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sfimm_n, "fUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sfimm_p, "fUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sfmax, "fff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sfmin, "fff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sfmpy, "fff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_sfsub, "fff", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_acci, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_accii, "iiiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmaci_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmacr_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmacs_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmacs_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmacsc_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmacsc_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmpyi_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmpyr_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmpyrs_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmpyrs_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmpyrsc_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmpyrsc_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmpys_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmpys_s1, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmpysc_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cmpysc_s1, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cnacs_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cnacs_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cnacsc_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_cnacsc_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_dpmpyss_acc_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_dpmpyss_nac_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_dpmpyss_rnd_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_dpmpyss_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_dpmpyuu_acc_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_dpmpyuu_nac_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_dpmpyuu_s0, "ULLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_hmmpyh_rs1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_hmmpyh_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_hmmpyl_rs1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_hmmpyl_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_maci, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_macsin, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_macsip, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmachs_rs0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmachs_rs1, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmachs_s0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmachs_s1, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmacls_rs0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmacls_rs1, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmacls_s0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmacls_s1, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmacuhs_rs0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmacuhs_rs1, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmacuhs_s0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmacuhs_s1, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmaculs_rs0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmaculs_rs1, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmaculs_s0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmaculs_s1, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyh_rs0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyh_rs1, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyh_s0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyh_s1, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyl_rs0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyl_rs1, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyl_s0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyl_s1, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyuh_rs0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyuh_rs1, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyuh_s0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyuh_s1, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyul_rs0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyul_rs1, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyul_s0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mmpyul_s1, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_hh_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_hh_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_hl_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_hl_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_lh_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_lh_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_ll_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_ll_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_sat_hh_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_sat_hh_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_sat_hl_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_sat_hl_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_sat_lh_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_sat_lh_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_sat_ll_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_acc_sat_ll_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_hh_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_hh_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_hl_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_hl_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_lh_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_lh_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_ll_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_ll_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_hh_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_hh_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_hl_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_hl_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_lh_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_lh_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_ll_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_ll_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_sat_hh_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_sat_hh_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_sat_hl_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_sat_hl_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_sat_lh_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_sat_lh_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_sat_ll_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_nac_sat_ll_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_rnd_hh_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_rnd_hh_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_rnd_hl_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_rnd_hl_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_rnd_lh_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_rnd_lh_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_rnd_ll_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_rnd_ll_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_hh_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_hh_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_hl_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_hl_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_lh_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_lh_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_ll_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_ll_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_up, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_up_s1, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpy_up_s1_sat, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_acc_hh_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_acc_hh_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_acc_hl_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_acc_hl_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_acc_lh_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_acc_lh_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_acc_ll_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_acc_ll_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_hh_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_hh_s1, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_hl_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_hl_s1, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_lh_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_lh_s1, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_ll_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_ll_s1, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_nac_hh_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_nac_hh_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_nac_hl_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_nac_hl_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_nac_lh_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_nac_lh_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_nac_ll_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_nac_ll_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_rnd_hh_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_rnd_hh_s1, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_rnd_hl_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_rnd_hl_s1, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_rnd_lh_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_rnd_lh_s1, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_rnd_ll_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyd_rnd_ll_s1, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyi, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpysmi, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpysu_up, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_acc_hh_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_acc_hh_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_acc_hl_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_acc_hl_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_acc_lh_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_acc_lh_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_acc_ll_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_acc_ll_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_hh_s0, "Uiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_hh_s1, "Uiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_hl_s0, "Uiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_hl_s1, "Uiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_lh_s0, "Uiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_lh_s1, "Uiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_ll_s0, "Uiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_ll_s1, "Uiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_nac_hh_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_nac_hh_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_nac_hl_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_nac_hl_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_nac_lh_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_nac_lh_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_nac_ll_s0, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_nac_ll_s1, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyu_up, "Uiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_acc_hh_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_acc_hh_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_acc_hl_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_acc_hl_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_acc_lh_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_acc_lh_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_acc_ll_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_acc_ll_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_hh_s0, "ULLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_hh_s1, "ULLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_hl_s0, "ULLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_hl_s1, "ULLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_lh_s0, "ULLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_lh_s1, "ULLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_ll_s0, "ULLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_ll_s1, "ULLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_nac_hh_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_nac_hh_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_nac_hl_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_nac_hl_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_nac_lh_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_nac_lh_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_nac_ll_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyud_nac_ll_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mpyui, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_nacci, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_naccii, "iiiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_subacc, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vabsdiffh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vabsdiffw, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vcmac_s0_sat_i, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vcmac_s0_sat_r, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vcmpy_s0_sat_i, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vcmpy_s0_sat_r, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vcmpy_s1_sat_i, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vcmpy_s1_sat_r, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vdmacs_s0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vdmacs_s1, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vdmpyrs_s0, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vdmpyrs_s1, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vdmpys_s0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vdmpys_s1, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmac2, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmac2es, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmac2es_s0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmac2es_s1, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmac2s_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmac2s_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmac2su_s0, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmac2su_s1, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmpy2es_s0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmpy2es_s1, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmpy2s_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmpy2s_s0pack, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmpy2s_s1, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmpy2s_s1pack, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmpy2su_s0, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vmpy2su_s1, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vraddh, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vradduh, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vrcmaci_s0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vrcmaci_s0c, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vrcmacr_s0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vrcmacr_s0c, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vrcmpyi_s0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vrcmpyi_s0c, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vrcmpyr_s0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vrcmpyr_s0c, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vrcmpys_acc_s1, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vrcmpys_s1, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vrcmpys_s1rp, "iLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vrmac_s0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_vrmpy_s0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_xor_xacc, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_and_and, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_and_andn, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_and_or, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_and_xor, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_cmpyi_wh, "iLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_cmpyi_whc, "iLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_cmpyr_wh, "iLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_cmpyr_whc, "iLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_mac_up_s1_sat, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_mpyri_addi, "iUIiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_mpyri_addr, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_mpyri_addr_u2, "iiUIii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_mpyrr_addi, "iUIiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_mpyrr_addr, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_nac_up_s1_sat, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_or_and, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_or_andn, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_or_or, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_or_xor, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_pmpyw, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_pmpyw_acc, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_vpmpyh, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_vpmpyh_acc, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_vrmpyeh_acc_s0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_vrmpyeh_acc_s1, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_vrmpyeh_s0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_vrmpyeh_s1, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_vrmpyoh_acc_s0, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_vrmpyoh_acc_s1, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_vrmpyoh_s0, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_vrmpyoh_s1, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_xor_and, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_xor_andn, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_xor_or, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M4_xor_xacc, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M5_vdmacbsu, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M5_vdmpybsu, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M5_vmacbsu, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M5_vmacbuu, "LLiLLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M5_vmpybsu, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M5_vmpybuu, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M5_vrmacbsu, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M5_vrmacbuu, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M5_vrmpybsu, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_M5_vrmpybuu, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_addasl_rrri, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_p, "LLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_p_acc, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_p_and, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_p_nac, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_p_or, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_p_xacc, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_r, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_r_acc, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_r_and, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_r_nac, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_r_or, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_r_sat, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_r_xacc, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_vh, "LLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_i_vw, "LLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_r_p, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_r_p_acc, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_r_p_and, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_r_p_nac, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_r_p_or, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_r_p_xor, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_r_r, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_r_r_acc, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_r_r_and, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_r_r_nac, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_r_r_or, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_r_r_sat, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_r_vh, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asl_r_vw, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_p, "LLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_p_acc, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_p_and, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_p_nac, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_p_or, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_p_rnd, "LLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax, "LLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_r, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_r_acc, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_r_and, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_r_nac, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_r_or, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_r_rnd, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_svw_trun, "iLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_vh, "LLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_i_vw, "LLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_p, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_p_acc, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_p_and, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_p_nac, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_p_or, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_p_xor, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_r, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_r_acc, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_r_and, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_r_nac, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_r_or, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_r_sat, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_svw_trun, "iLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_vh, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_asr_r_vw, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_brev, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_brevp, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_cl0, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_cl0p, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_cl1, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_cl1p, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_clb, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_clbnorm, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_clbp, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_clrbit_i, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_clrbit_r, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_ct0, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_ct0p, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_ct1, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_ct1p, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_deinterleave, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_extractu, "iiUIiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_extractu_rp, "iiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_extractup, "LLiLLiUIiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_extractup_rp, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_insert, "iiiUIiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_insert_rp, "iiiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_insertp, "LLiLLiLLiUIiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_insertp_rp, "LLiLLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_interleave, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lfsp, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsl_r_p, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsl_r_p_acc, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsl_r_p_and, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsl_r_p_nac, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsl_r_p_or, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsl_r_p_xor, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsl_r_r, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsl_r_r_acc, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsl_r_r_and, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsl_r_r_nac, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsl_r_r_or, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsl_r_vh, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsl_r_vw, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_i_p, "LLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_i_p_acc, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_i_p_and, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_i_p_nac, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_i_p_or, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_i_p_xacc, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_i_r, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_i_r_acc, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_i_r_and, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_i_r_nac, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_i_r_or, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_i_r_xacc, "iiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_i_vh, "LLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_i_vw, "LLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_r_p, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_r_p_acc, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_r_p_and, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_r_p_nac, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_r_p_or, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_r_p_xor, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_r_r, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_r_r_acc, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_r_r_and, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_r_r_nac, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_r_r_or, "iiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_r_vh, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_lsr_r_vw, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_packhl, "LLiii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_parityp, "iLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_setbit_i, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_setbit_r, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_shuffeb, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_shuffeh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_shuffob, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_shuffoh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_svsathb, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_svsathub, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_tableidxb_goodsyntax, "iiiUIiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_tableidxd_goodsyntax, "iiiUIiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_tableidxh_goodsyntax, "iiiUIiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_tableidxw_goodsyntax, "iiiUIiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_togglebit_i, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_togglebit_r, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_tstbit_i, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_tstbit_r, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_valignib, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_valignrb, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vcnegh, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vcrotate, "LLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vrcnegh, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vrndpackwh, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vrndpackwhs, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vsathb, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vsathb_nopack, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vsathub, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vsathub_nopack, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vsatwh, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vsatwh_nopack, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vsatwuh, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vsatwuh_nopack, "LLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vsplatrb, "ii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vsplatrh, "LLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vspliceib, "LLiLLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vsplicerb, "LLiLLiLLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vsxtbh, "LLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vsxthw, "LLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vtrunehb, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vtrunewh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vtrunohb, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vtrunowh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vzxtbh, "LLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_vzxthw, "LLii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_addaddi, "iiiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_addi_asl_ri, "iUIiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_addi_lsr_ri, "iUIiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_andi_asl_ri, "iUIiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_andi_lsr_ri, "iUIiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_clbaddi, "iiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_clbpaddi, "iLLiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_clbpnorm, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_extract, "iiUIiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_extract_rp, "iiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_extractp, "LLiLLiUIiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_extractp_rp, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_lsli, "iIii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_ntstbit_i, "iiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_ntstbit_r, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_or_andi, "iiiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_or_andix, "iiiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_or_ori, "iiiIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_ori_asl_ri, "iUIiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_ori_lsr_ri, "iUIiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_parity, "iii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_subaddi, "iiIii", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_subi_asl_ri, "iUIiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_subi_lsr_ri, "iUIiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_vrcrotate, "LLiLLiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_vrcrotate_acc, "LLiLLiLLiiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_vxaddsubh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_vxaddsubhr, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_vxaddsubw, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_vxsubaddh, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_vxsubaddhr, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S4_vxsubaddw, "LLiLLiLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax, "iLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S5_asrhub_sat, "iLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S5_popcountp, "iLLi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_S5_vasrhrnd_goodsyntax, "LLiLLiUIi", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_Y2_dccleana, "vv*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_Y2_dccleaninva, "vv*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_Y2_dcfetch, "vv*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_Y2_dcinva, "vv*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_Y2_dczeroa, "vv*", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_Y4_l2fetch, "vv*i", "", V5)
		-TARGET_BUILTIN(__builtin_HEXAGON_Y5_l2fetch, "vv*LLi", "", V5)
		-
		-// V60 Scalar Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_p, "LLiLLiUIi", "", V60)
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_p_acc, "LLiLLiLLiUIi", "", V60)
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_p_and, "LLiLLiLLiUIi", "", V60)
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_p_nac, "LLiLLiLLiUIi", "", V60)
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_p_or, "LLiLLiLLiUIi", "", V60)
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_p_xacc, "LLiLLiLLiUIi", "", V60)
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_r, "iiUIi", "", V60)
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_r_acc, "iiiUIi", "", V60)
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_r_and, "iiiUIi", "", V60)
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_r_nac, "iiiUIi", "", V60)
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_r_or, "iiiUIi", "", V60)
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_r_xacc, "iiiUIi", "", V60)
		-
		-// V62 Scalar Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_M6_vabsdiffb, "LLiLLiLLi", "", V62)
		-TARGET_BUILTIN(__builtin_HEXAGON_M6_vabsdiffub, "LLiLLiLLi", "", V62)
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_vsplatrbp, "LLii", "", V62)
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_vtrunehb_ppp, "LLiLLiLLi", "", V62)
		-TARGET_BUILTIN(__builtin_HEXAGON_S6_vtrunohb_ppp, "LLiLLiLLi", "", V62)
		-
		-// V65 Scalar Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_A6_vcmpbeq_notany, "iLLiLLi", "", V65)
		-
		-// V66 Scalar Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfadd, "ddd", "", V66)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfsub, "ddd", "", V66)
		-TARGET_BUILTIN(__builtin_HEXAGON_M2_mnaci, "iiii", "", V66)
		-TARGET_BUILTIN(__builtin_HEXAGON_S2_mask, "iUIiUIi", "", V66)
		-
		-// V67 Scalar Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_A7_clip, "iiUIi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_A7_croundd_ri, "LLiLLiUIi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_A7_croundd_rr, "LLiLLii", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_A7_vclip, "LLiLLiUIi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfmax, "ddd", "", V67)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfmin, "ddd", "", V67)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfmpyfix, "ddd", "", V67)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfmpyhh, "dddd", "", V67)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfmpylh, "dddd", "", V67)
		-TARGET_BUILTIN(__builtin_HEXAGON_F2_dfmpyll, "ddd", "", V67)
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_dcmpyiw, "LLiLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_dcmpyiw_acc, "LLiLLiLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_dcmpyiwc, "LLiLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_dcmpyiwc_acc, "LLiLLiLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_dcmpyrw, "LLiLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_dcmpyrw_acc, "LLiLLiLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_dcmpyrwc, "LLiLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_dcmpyrwc_acc, "LLiLLiLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_vdmpy, "LLiLLiLLi", "", V67)
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_vdmpy_acc, "LLiLLiLLiLLi", "", V67)
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_wcmpyiw, "iLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_wcmpyiw_rnd, "iLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_wcmpyiwc, "iLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_wcmpyiwc_rnd, "iLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_wcmpyrw, "iLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_wcmpyrw_rnd, "iLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_wcmpyrwc, "iLLiLLi", "", "audio")
		-TARGET_BUILTIN(__builtin_HEXAGON_M7_wcmpyrwc_rnd, "iLLiLLi", "", "audio")
		-
		-// V68 Scalar Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_Y6_dmlink, "vv*v*", "", V68)
		-TARGET_BUILTIN(__builtin_HEXAGON_Y6_dmpause, "i", "", V68)
		-TARGET_BUILTIN(__builtin_HEXAGON_Y6_dmpoll, "i", "", V68)
		-TARGET_BUILTIN(__builtin_HEXAGON_Y6_dmresume, "vv*", "", V68)
		-TARGET_BUILTIN(__builtin_HEXAGON_Y6_dmstart, "vv*", "", V68)
		-TARGET_BUILTIN(__builtin_HEXAGON_Y6_dmwait, "i", "", V68)
		-
		-// V60 HVX Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_extractw, "iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_extractw_128B, "iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_hi, "V16iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_hi_128B, "V32iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_lo, "V16iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_lo_128B, "V32iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_lvsplatw, "V16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_lvsplatw_128B, "V32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_and, "V64bV64bV64b", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_and_128B, "V128bV128bV128b", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_and_n, "V64bV64bV64b", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_and_n_128B, "V128bV128bV128b", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_not, "V64bV64b", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_not_128B, "V128bV128b", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_or, "V64bV64bV64b", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_or_128B, "V128bV128bV128b", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_or_n, "V64bV64bV64b", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_or_n_128B, "V128bV128bV128b", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_scalar2, "V64bi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_scalar2_128B, "V128bi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_xor, "V64bV64bV64b", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_xor_128B, "V128bV128bV128b", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vS32b_nqpred_ai, "vV64bv*V16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vS32b_nqpred_ai_128B, "vV128bv*V32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai, "vV64bv*V16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai_128B, "vV128bv*V32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai, "vV64bv*V16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai_128B, "vV128bv*V32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vS32b_qpred_ai, "vV64bv*V16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vS32b_qpred_ai_128B, "vV128bv*V32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsdiffh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsdiffh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsdiffub, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsdiffub_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsdiffuh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsdiffuh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsdiffw, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsdiffw_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsh, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsh_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsh_sat, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsh_sat_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsw, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsw_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsw_sat, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsw_sat_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddb, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddb_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddb_dv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddb_dv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddbnq, "V16iV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddbnq_128B, "V32iV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddbq, "V16iV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddbq_128B, "V32iV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddh_dv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddh_dv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddhnq, "V16iV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddhnq_128B, "V32iV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddhq, "V16iV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddhq_128B, "V32iV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddhsat, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddhsat_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddhsat_dv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddhsat_dv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddhw, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddhw_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddubh, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddubh_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddubsat, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddubsat_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddubsat_dv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddubsat_dv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadduhsat, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadduhsat_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadduhsat_dv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadduhsat_dv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadduhw, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadduhw_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddw, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddw_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddw_dv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddw_dv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddwnq, "V16iV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddwnq_128B, "V32iV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddwq, "V16iV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddwq_128B, "V32iV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddwsat, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddwsat_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddwsat_dv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddwsat_dv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_valignb, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_valignb_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_valignbi, "V16iV16iV16iUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_valignbi_128B, "V32iV32iV32iUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vand, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vand_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandqrt, "V16iV64bi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandqrt_128B, "V32iV128bi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandqrt_acc, "V16iV16iV64bi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandqrt_acc_128B, "V32iV32iV128bi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandvrt, "V64bV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandvrt_128B, "V128bV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandvrt_acc, "V64bV64bV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandvrt_acc_128B, "V128bV128bV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaslh, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaslh_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaslhv, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaslhv_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaslw, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaslw_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaslw_acc, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaslw_acc_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaslwv, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaslwv_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrh, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrh_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrhbrndsat, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrhbrndsat_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrhubrndsat, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrhubrndsat_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrhubsat, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrhubsat_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrhv, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrhv_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrw, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrw_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrw_acc, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrw_acc_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrwh, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrwh_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrwhrndsat, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrwhrndsat_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrwhsat, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrwhsat_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrwuhsat, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrwuhsat_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrwv, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrwv_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vassign, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vassign_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vassignp, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vassignp_128B, "V64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavgh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavgh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavghrnd, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavghrnd_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavgub, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavgub_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavgubrnd, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavgubrnd_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavguh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavguh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavguhrnd, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavguhrnd_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavgw, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavgw_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavgwrnd, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavgwrnd_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcl0h, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcl0h_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcl0w, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcl0w_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcombine, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcombine_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vd0, "V16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vd0_128B, "V32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdealb, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdealb_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdealb4w, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdealb4w_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdealh, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdealh_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdealvdd, "V32iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdealvdd_128B, "V64iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdelta, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdelta_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpybus, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpybus_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpybus_acc, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpybus_acc_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpybus_dv, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpybus_dv_128B, "V64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpybus_dv_acc, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpybus_dv_acc_128B, "V64iV64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhb, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhb_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhb_acc, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhb_acc_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhb_dv, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhb_dv_128B, "V64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhb_dv_acc, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhb_dv_acc_128B, "V64iV64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhisat, "V16iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhisat_128B, "V32iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhisat_acc, "V16iV16iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhisat_acc_128B, "V32iV32iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhsat, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhsat_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhsat_acc, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhsat_acc_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhsuisat, "V16iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhsuisat_128B, "V32iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhsuisat_acc, "V16iV16iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhsuisat_acc_128B, "V32iV32iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhsusat, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhsusat_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhsusat_acc, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhsusat_acc_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhvsat, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhvsat_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhvsat_acc, "V16iV16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpyhvsat_acc_128B, "V32iV32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdsaduh, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdsaduh_128B, "V64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdsaduh_acc, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdsaduh_acc_128B, "V64iV64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqb, "V64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqb_128B, "V128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqb_and, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqb_and_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqb_or, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqb_or_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqb_xor, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqb_xor_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqh, "V64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqh_128B, "V128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqh_and, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqh_and_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqh_or, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqh_or_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqh_xor, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqh_xor_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqw, "V64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqw_128B, "V128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqw_and, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqw_and_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqw_or, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqw_or_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqw_xor, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_veqw_xor_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtb, "V64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtb_128B, "V128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtb_and, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtb_and_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtb_or, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtb_or_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtb_xor, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtb_xor_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgth, "V64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgth_128B, "V128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgth_and, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgth_and_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgth_or, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgth_or_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgth_xor, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgth_xor_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtub, "V64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtub_128B, "V128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtub_and, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtub_and_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtub_or, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtub_or_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtub_xor, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtub_xor_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuh, "V64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuh_128B, "V128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuh_and, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuh_and_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuh_or, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuh_or_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuh_xor, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuh_xor_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuw, "V64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuw_128B, "V128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuw_and, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuw_and_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuw_or, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuw_or_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuw_xor, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtuw_xor_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtw, "V64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtw_128B, "V128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtw_and, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtw_and_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtw_or, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtw_or_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtw_xor, "V64bV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtw_xor_128B, "V128bV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vinsertwr, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vinsertwr_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlalignb, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlalignb_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlalignbi, "V16iV16iV16iUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlalignbi_128B, "V32iV32iV32iUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlsrh, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlsrh_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlsrhv, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlsrhv_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlsrw, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlsrw_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlsrwv, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlsrwv_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvvb, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvvb_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvvb_oracc, "V16iV16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvvb_oracc_128B, "V32iV32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvwh, "V32iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvwh_128B, "V64iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvwh_oracc, "V32iV32iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvwh_oracc_128B, "V64iV64iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaxh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaxh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaxub, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaxub_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaxuh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaxuh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaxw, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaxw_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vminh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vminh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vminub, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vminub_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vminuh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vminuh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vminw, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vminw_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpabus, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpabus_128B, "V64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpabus_acc, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpabus_acc_128B, "V64iV64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpabusv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpabusv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpabuuv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpabuuv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpahb, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpahb_128B, "V64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpahb_acc, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpahb_acc_128B, "V64iV64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpybus, "V32iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpybus_128B, "V64iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpybus_acc, "V32iV32iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpybus_acc_128B, "V64iV64iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpybusv, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpybusv_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpybusv_acc, "V32iV32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpybusv_acc_128B, "V64iV64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpybv, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpybv_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpybv_acc, "V32iV32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpybv_acc_128B, "V64iV64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyewuh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyewuh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyh, "V32iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyh_128B, "V64iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhsat_acc, "V32iV32iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhsat_acc_128B, "V64iV64iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhsrs, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhsrs_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhss, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhss_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhus, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhus_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhus_acc, "V32iV32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhus_acc_128B, "V64iV64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhv, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhv_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhv_acc, "V32iV32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhv_acc_128B, "V64iV64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhvsrs, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyhvsrs_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyieoh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyieoh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiewh_acc, "V16iV16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiewh_acc_128B, "V32iV32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiewuh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiewuh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiewuh_acc, "V16iV16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiewuh_acc_128B, "V32iV32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyih, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyih_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyih_acc, "V16iV16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyih_acc_128B, "V32iV32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyihb, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyihb_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyihb_acc, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyihb_acc_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiowh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiowh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiwb, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiwb_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiwb_acc, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiwb_acc_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiwh, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiwh_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiwh_acc, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiwh_acc_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyowh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyowh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyowh_rnd, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyowh_rnd_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc, "V16iV16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc_128B, "V32iV32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyowh_sacc, "V16iV16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyowh_sacc_128B, "V32iV32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyub, "V32iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyub_128B, "V64iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyub_acc, "V32iV32iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyub_acc_128B, "V64iV64iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyubv, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyubv_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyubv_acc, "V32iV32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyubv_acc_128B, "V64iV64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuh, "V32iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuh_128B, "V64iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuh_acc, "V32iV32iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuh_acc_128B, "V64iV64iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuhv, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuhv_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuhv_acc, "V32iV32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuhv_acc_128B, "V64iV64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmux, "V16iV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmux_128B, "V32iV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vnavgh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vnavgh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vnavgub, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vnavgub_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vnavgw, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vnavgw_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vnormamth, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vnormamth_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vnormamtw, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vnormamtw_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vnot, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vnot_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vor, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vor_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackeb, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackeb_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackeh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackeh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackhb_sat, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackhb_sat_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackhub_sat, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackhub_sat_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackob, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackob_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackoh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackoh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackwh_sat, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackwh_sat_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackwuh_sat, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpackwuh_sat_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpopcounth, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vpopcounth_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrdelta, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrdelta_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybus, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybus_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybus_acc, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybus_acc_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybusi, "V32iV32iiUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybusi_128B, "V64iV64iiUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybusi_acc, "V32iV32iV32iiUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybusi_acc_128B, "V64iV64iV64iiUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybusv, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybusv_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybusv_acc, "V16iV16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybusv_acc_128B, "V32iV32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybv, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybv_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybv_acc, "V16iV16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybv_acc_128B, "V32iV32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_acc, "V16iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_acc_128B, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyubi, "V32iV32iiUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyubi_128B, "V64iV64iiUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyubi_acc, "V32iV32iV32iiUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyubi_acc_128B, "V64iV64iV64iiUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyubv, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyubv_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyubv_acc, "V16iV16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyubv_acc_128B, "V32iV32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vror, "V16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vror_128B, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vroundhb, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vroundhb_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vroundhub, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vroundhub_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vroundwh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vroundwh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vroundwuh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vroundwuh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrsadubi, "V32iV32iiUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrsadubi_128B, "V64iV64iiUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrsadubi_acc, "V32iV32iV32iiUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrsadubi_acc_128B, "V64iV64iV64iiUIi", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsathub, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsathub_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsatwh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsatwh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsb, "V32iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsb_128B, "V64iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsh, "V32iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsh_128B, "V64iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshufeh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshufeh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshuffb, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshuffb_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshuffeb, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshuffeb_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshuffh, "V16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshuffh_128B, "V32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshuffob, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshuffob_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshuffvdd, "V32iV16iV16ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshuffvdd_128B, "V64iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshufoeb, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshufoeb_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshufoeh, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshufoeh_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshufoh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vshufoh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubb, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubb_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubb_dv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubb_dv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubbnq, "V16iV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubbnq_128B, "V32iV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubbq, "V16iV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubbq_128B, "V32iV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubh, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubh_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubh_dv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubh_dv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubhnq, "V16iV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubhnq_128B, "V32iV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubhq, "V16iV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubhq_128B, "V32iV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubhsat, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubhsat_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubhsat_dv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubhsat_dv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubhw, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubhw_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsububh, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsububh_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsububsat, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsububsat_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsububsat_dv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsububsat_dv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubuhsat, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubuhsat_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubuhsat_dv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubuhsat_dv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubuhw, "V32iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubuhw_128B, "V64iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubw, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubw_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubw_dv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubw_dv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubwnq, "V16iV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubwnq_128B, "V32iV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubwq, "V16iV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubwq_128B, "V32iV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubwsat, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubwsat_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubwsat_dv, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubwsat_dv_128B, "V64iV64iV64i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vswap, "V32iV64bV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vswap_128B, "V64iV128bV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vtmpyb, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vtmpyb_128B, "V64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vtmpyb_acc, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vtmpyb_acc_128B, "V64iV64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vtmpybus, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vtmpybus_128B, "V64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vtmpybus_acc, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vtmpybus_acc_128B, "V64iV64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vtmpyhb, "V32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vtmpyhb_128B, "V64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vtmpyhb_acc, "V32iV32iV32ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vtmpyhb_acc_128B, "V64iV64iV64ii", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vunpackb, "V32iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vunpackb_128B, "V64iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vunpackh, "V32iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vunpackh_128B, "V64iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vunpackob, "V32iV32iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vunpackob_128B, "V64iV64iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vunpackoh, "V32iV32iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vunpackoh_128B, "V64iV64iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vunpackub, "V32iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vunpackub_128B, "V64iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vunpackuh, "V32iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vunpackuh_128B, "V64iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vxor, "V16iV16iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vxor_128B, "V32iV32iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vzb, "V32iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vzb_128B, "V64iV32i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vzh, "V32iV16i", "", HVXV60)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vzh_128B, "V64iV32i", "", HVXV60)
		-
		-// V62 HVX Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_lvsplatb, "V16ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_lvsplatb_128B, "V32ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_lvsplath, "V16ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_lvsplath_128B, "V32ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_scalar2v2, "V64bi", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_pred_scalar2v2_128B, "V128bi", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_shuffeqh, "V64bV64bV64b", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_shuffeqh_128B, "V128bV128bV128b", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_shuffeqw, "V64bV64bV64b", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_shuffeqw_128B, "V128bV128bV128b", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddbsat, "V16iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddbsat_128B, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddbsat_dv, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddbsat_dv_128B, "V64iV64iV64i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddcarry, "V16iV16iV16iv*", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddcarry_128B, "V32iV32iV32iv*", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddclbh, "V16iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddclbh_128B, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddclbw, "V16iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddclbw_128B, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddhw_acc, "V32iV32iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddhw_acc_128B, "V64iV64iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddubh_acc, "V32iV32iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddubh_acc_128B, "V64iV64iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddububb_sat, "V16iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddububb_sat_128B, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadduhw_acc, "V32iV32iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadduhw_acc_128B, "V64iV64iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadduwsat, "V16iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadduwsat_128B, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadduwsat_dv, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadduwsat_dv_128B, "V64iV64iV64i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandnqrt, "V16iV64bi", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandnqrt_128B, "V32iV128bi", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandnqrt_acc, "V16iV16iV64bi", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandnqrt_acc_128B, "V32iV32iV128bi", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandvnqv, "V16iV64bV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandvnqv_128B, "V32iV128bV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandvqv, "V16iV64bV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vandvqv_128B, "V32iV128bV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrhbsat, "V16iV16iV16ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrhbsat_128B, "V32iV32iV32ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasruwuhrndsat, "V16iV16iV16ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasruwuhrndsat_128B, "V32iV32iV32ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrwuhrndsat, "V16iV16iV16ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrwuhrndsat_128B, "V32iV32iV32ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlsrb, "V16iV16ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlsrb_128B, "V32iV32ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvvb_nm, "V16iV16iV16ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvvb_nm_128B, "V32iV32iV32ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvvb_oracci, "V16iV16iV16iV16iUIi", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvvb_oracci_128B, "V32iV32iV32iV32iUIi", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvvbi, "V16iV16iV16iUIi", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvvbi_128B, "V32iV32iV32iUIi", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvwh_nm, "V32iV16iV16ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvwh_nm_128B, "V64iV32iV32ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvwh_oracci, "V32iV32iV16iV16iUIi", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvwh_oracci_128B, "V64iV64iV32iV32iUIi", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvwhi, "V32iV16iV16iUIi", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlutvwhi_128B, "V64iV32iV32iUIi", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaxb, "V16iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaxb_128B, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vminb, "V16iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vminb_128B, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpauhb, "V32iV32ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpauhb_128B, "V64iV64ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpauhb_acc, "V32iV32iV32ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpauhb_acc_128B, "V64iV64iV64ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyewuh_64, "V32iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyewuh_64_128B, "V64iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiwub, "V16iV16ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiwub_128B, "V32iV32ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiwub_acc, "V16iV16iV16ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyiwub_acc_128B, "V32iV32iV32ii", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyowh_64_acc, "V32iV32iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyowh_64_acc_128B, "V64iV64iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrounduhub, "V16iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrounduhub_128B, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrounduwuh, "V16iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrounduwuh_128B, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsatuwuh, "V16iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsatuwuh_128B, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubbsat, "V16iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubbsat_128B, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubbsat_dv, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubbsat_dv_128B, "V64iV64iV64i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubcarry, "V16iV16iV16iv*", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubcarry_128B, "V32iV32iV32iv*", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubububb_sat, "V16iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubububb_sat_128B, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubuwsat, "V16iV16iV16i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubuwsat_128B, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubuwsat_dv, "V32iV32iV32i", "", HVXV62)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubuwsat_dv_128B, "V64iV64iV64i", "", HVXV62)
		-
		-// V65 HVX Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsb, "V16iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsb_128B, "V32iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsb_sat, "V16iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabsb_sat_128B, "V32iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaslh_acc, "V16iV16iV16ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaslh_acc_128B, "V32iV32iV32ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrh_acc, "V16iV16iV16ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrh_acc_128B, "V32iV32iV32ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasruhubrndsat, "V16iV16iV16ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasruhubrndsat_128B, "V32iV32iV32ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasruhubsat, "V16iV16iV16ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasruhubsat_128B, "V32iV32iV32ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasruwuhsat, "V16iV16iV16ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasruwuhsat_128B, "V32iV32iV32ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavgb, "V16iV16iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavgb_128B, "V32iV32iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavgbrnd, "V16iV16iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavgbrnd_128B, "V32iV32iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavguw, "V16iV16iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavguw_128B, "V32iV32iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavguwrnd, "V16iV16iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vavguwrnd_128B, "V32iV32iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdd0, "V32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdd0_128B, "V64i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgathermh, "vv*iiV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgathermh_128B, "vv*iiV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgathermhq, "vv*V64biiV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgathermhq_128B, "vv*V128biiV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgathermhw, "vv*iiV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgathermhw_128B, "vv*iiV64i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgathermhwq, "vv*V64biiV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgathermhwq_128B, "vv*V128biiV64i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgathermw, "vv*iiV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgathermw_128B, "vv*iiV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgathermwq, "vv*V64biiV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgathermwq_128B, "vv*V128biiV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlut4, "V16iV16iLLi", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vlut4_128B, "V32iV32iLLi", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpabuu, "V32iV32ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpabuu_128B, "V64iV64ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpabuu_acc, "V32iV32iV32ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpabuu_acc_128B, "V64iV64iV64ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpahhsat, "V16iV16iV16iLLi", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpahhsat_128B, "V32iV32iV32iLLi", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpauhuhsat, "V16iV16iV16iLLi", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpauhuhsat_128B, "V32iV32iV32iLLi", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpsuhuhsat, "V16iV16iV16iLLi", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpsuhuhsat_128B, "V32iV32iV32iLLi", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyh_acc, "V32iV32iV16ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyh_acc_128B, "V64iV64iV32ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuhe, "V16iV16ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuhe_128B, "V32iV32ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuhe_acc, "V16iV16iV16ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuhe_acc_128B, "V32iV32iV32ii", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vnavgb, "V16iV16iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vnavgb_128B, "V32iV32iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vprefixqb, "V16iV64b", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vprefixqb_128B, "V32iV128b", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vprefixqh, "V16iV64b", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vprefixqh_128B, "V32iV128b", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vprefixqw, "V16iV64b", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vprefixqw_128B, "V32iV128b", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermh, "viiV16iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermh_128B, "viiV32iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermh_add, "viiV16iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermh_add_128B, "viiV32iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermhq, "vV64biiV16iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermhq_128B, "vV128biiV32iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermhw, "viiV32iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermhw_128B, "viiV64iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermhw_add, "viiV32iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermhw_add_128B, "viiV64iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermhwq, "vV64biiV32iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermhwq_128B, "vV128biiV64iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermw, "viiV16iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermw_128B, "viiV32iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermw_add, "viiV16iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermw_add_128B, "viiV32iV32i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermwq, "vV64biiV16iV16i", "", HVXV65)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vscattermwq_128B, "vV128biiV32iV32i", "", HVXV65)
		-
		-// V66 HVX Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddcarryo, "V16iV16iV16iv*", "", HVXV66)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddcarryo_128B, "V32iV32iV32iv*", "", HVXV66)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddcarrysat, "V16iV16iV16iV64b", "", HVXV66)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vaddcarrysat_128B, "V32iV32iV32iV128b", "", HVXV66)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasr_into, "V32iV32iV16iV16i", "", HVXV66)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasr_into_128B, "V64iV64iV32iV32i", "", HVXV66)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrotr, "V16iV16iV16i", "", HVXV66)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vrotr_128B, "V32iV32iV32i", "", HVXV66)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsatdw, "V16iV16iV16i", "", HVXV66)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsatdw_128B, "V32iV32iV32i", "", HVXV66)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubcarryo, "V16iV16iV16iv*", "", HVXV66)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsubcarryo_128B, "V32iV32iV32iv*", "", HVXV66)
		-
		-// V68 HVX Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_v6mpyhubs10, "V32iV32iV32iUIi", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_v6mpyhubs10_128B, "V64iV64iV64iUIi", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_v6mpyhubs10_vxx, "V32iV32iV32iV32iUIi", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_v6mpyhubs10_vxx_128B, "V64iV64iV64iV64iUIi", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_v6mpyvubs10, "V32iV32iV32iUIi", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_v6mpyvubs10_128B, "V64iV64iV64iUIi", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_v6mpyvubs10_vxx, "V32iV32iV32iV32iUIi", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_v6mpyvubs10_vxx_128B, "V64iV64iV64iV64iUIi", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabs_hf, "V16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabs_hf_128B, "V32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabs_sf, "V16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabs_sf_128B, "V32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_hf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_hf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_hf_hf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_hf_hf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_qf16, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_qf16_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_qf16_mix, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_qf16_mix_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_qf32, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_qf32_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_qf32_mix, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_qf32_mix_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_sf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_sf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_sf_hf, "V32iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_sf_hf_128B, "V64iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_sf_sf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_sf_sf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vassign_fp, "V16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vassign_fp_128B, "V32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_hf_qf16, "V16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_hf_qf16_128B, "V32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_hf_qf32, "V16iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_hf_qf32_128B, "V32iV64i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_sf_qf32, "V16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_sf_qf32_128B, "V32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_b_hf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_b_hf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_h_hf, "V16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_h_hf_128B, "V32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_hf_b, "V32iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_hf_b_128B, "V64iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_hf_h, "V16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_hf_h_128B, "V32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_hf_sf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_hf_sf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_hf_ub, "V32iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_hf_ub_128B, "V64iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_hf_uh, "V16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_hf_uh_128B, "V32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_sf_hf, "V32iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_sf_hf_128B, "V64iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_ub_hf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_ub_hf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_uh_hf, "V16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_uh_hf_128B, "V32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpy_sf_hf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpy_sf_hf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpy_sf_hf_acc, "V16iV16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vdmpy_sf_hf_acc_128B, "V32iV32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmax_hf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmax_hf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmax_sf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmax_sf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmin_hf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmin_hf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmin_sf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmin_sf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfneg_hf, "V16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfneg_hf_128B, "V32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfneg_sf, "V16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfneg_sf_128B, "V32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgthf, "V64bV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgthf_128B, "V128bV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgthf_and, "V64bV64bV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgthf_and_128B, "V128bV128bV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgthf_or, "V64bV64bV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgthf_or_128B, "V128bV128bV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgthf_xor, "V64bV64bV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgthf_xor_128B, "V128bV128bV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtsf, "V64bV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtsf_128B, "V128bV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtsf_and, "V64bV64bV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtsf_and_128B, "V128bV128bV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtsf_or, "V64bV64bV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtsf_or_128B, "V128bV128bV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtsf_xor, "V64bV64bV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtsf_xor_128B, "V128bV128bV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmax_hf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmax_hf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmax_sf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmax_sf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmin_hf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmin_hf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmin_sf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmin_sf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_hf_hf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_hf_hf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_hf_hf_acc, "V16iV16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_hf_hf_acc_128B, "V32iV32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf16, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf16_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf16_hf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf16_hf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf16_mix_hf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf16_mix_hf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf32, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf32_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf32_hf, "V32iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf32_hf_128B, "V64iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf32_mix_hf, "V32iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf32_mix_hf_128B, "V64iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf32_qf16, "V32iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf32_qf16_128B, "V64iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf32_sf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_qf32_sf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_hf, "V32iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_hf_128B, "V64iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_hf_acc, "V32iV32iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_hf_acc_128B, "V64iV64iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_sf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_sf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_hf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_hf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_hf_hf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_hf_hf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_qf16, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_qf16_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_qf16_mix, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_qf16_mix_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_qf32, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_qf32_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_qf32_mix, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_qf32_mix_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_sf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_sf_128B, "V32iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_sf_hf, "V32iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_sf_hf_128B, "V64iV32iV32i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_sf_sf, "V16iV16iV16i", "", HVXV68)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_sf_sf_128B, "V32iV32iV32i", "", HVXV68)
		-
		-// V69 HVX Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrvuhubrndsat, "V16iV32iV16i", "", HVXV69)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrvuhubrndsat_128B, "V32iV64iV32i", "", HVXV69)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrvuhubsat, "V16iV32iV16i", "", HVXV69)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrvuhubsat_128B, "V32iV64iV32i", "", HVXV69)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrvwuhrndsat, "V16iV32iV16i", "", HVXV69)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrvwuhrndsat_128B, "V32iV64iV32i", "", HVXV69)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrvwuhsat, "V16iV32iV16i", "", HVXV69)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrvwuhsat_128B, "V32iV64iV32i", "", HVXV69)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuhvs, "V16iV16iV16i", "", HVXV69)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuhvs_128B, "V32iV32iV32i", "", HVXV69)
		-
		-// V73 HVX Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_sf_bf, "V32iV16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_sf_bf_128B, "V64iV32iV32i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_h_hf, "V16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_h_hf_128B, "V32iV32i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_hf_h, "V16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_hf_h_128B, "V32iV32i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_sf_w, "V16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_sf_w_128B, "V32iV32i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_w_sf, "V16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_w_sf_128B, "V32iV32i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_bf_sf, "V16iV16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_bf_sf_128B, "V32iV32iV32i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf, "V64bV16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_128B, "V128bV32iV32i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_and, "V64bV64bV16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_and_128B, "V128bV128bV32iV32i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_or, "V64bV64bV16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_or_128B, "V128bV128bV32iV32i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_xor, "V64bV64bV16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_xor_128B, "V128bV128bV32iV32i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmax_bf, "V16iV16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmax_bf_128B, "V32iV32iV32i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmin_bf, "V16iV16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmin_bf_128B, "V32iV32iV32i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_bf, "V32iV16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_bf_128B, "V64iV32iV32i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_bf_acc, "V32iV32iV16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_bf_acc_128B, "V64iV64iV32iV32i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_sf_bf, "V32iV16iV16i", "", HVXV73)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_sf_bf_128B, "V64iV32iV32i", "", HVXV73)
		-
		-// V79 HVX Instructions.
		-
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_get_qfext, "V16iV16ii", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_get_qfext_128B, "V32iV32ii", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_get_qfext_oracc, "V16iV16iV16ii", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_get_qfext_oracc_128B, "V32iV32iV32ii", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_set_qfext, "V16iV16ii", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_set_qfext_128B, "V32iV32ii", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabs_f8, "V16iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vabs_f8_128B, "V32iV32i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_hf_f8, "V32iV16iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_hf_f8_128B, "V64iV32iV32i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_b_hf, "V16iV16iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_b_hf_128B, "V32iV32iV32i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_hf_b, "V32iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_hf_b_128B, "V64iV32i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_hf_ub, "V32iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_hf_ub_128B, "V64iV32i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_ub_hf, "V16iV16iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_ub_hf_128B, "V32iV32iV32i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_f8_hf, "V16iV16iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_f8_hf_128B, "V32iV32iV32i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_hf_f8, "V32iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_hf_f8_128B, "V64iV32i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmax_f8, "V16iV16iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmax_f8_128B, "V32iV32iV32i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmin_f8, "V16iV16iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmin_f8_128B, "V32iV32iV32i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfneg_f8, "V16iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vfneg_f8_128B, "V32iV32i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmerge_qf, "V16iV16iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmerge_qf_128B, "V32iV32iV32i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_hf_f8, "V32iV16iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_hf_f8_128B, "V64iV32iV32i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_hf_f8_acc, "V32iV32iV16iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_hf_f8_acc_128B, "V64iV64iV32iV32i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_rt_hf, "V16iV16ii", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_rt_hf_128B, "V32iV32ii", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_rt_qf16, "V16iV16ii", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_rt_qf16_128B, "V32iV32ii", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_rt_sf, "V16iV16ii", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_rt_sf_128B, "V32iV32ii", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_hf_f8, "V32iV16iV16i", "", HVXV79)
		-TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_hf_f8_128B, "V64iV32iV32i", "", HVXV79)

clang/include/clang/Basic/BuiltinsNVPTX.def→/dev/null

		@@ -1,1119 +0,0 @@
		-//===--- BuiltinsPTX.def - PTX Builtin function database ----*- C++ -*-===//
		-//
		-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
		-// See https://llvm.org/LICENSE.txt for license information.
		-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
		-//
		-//===----------------------------------------------------------------------===//
		-//
		-// This file defines the PTX-specific builtin function database. Users of
		-// this file must define the BUILTIN macro to make use of this information.
		-//
		-//===----------------------------------------------------------------------===//
		-
		-// The format of this database matches clang/Basic/Builtins.def.
		-
		-#if defined(BUILTIN) && !defined(TARGET_BUILTIN)
		-# define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
		-#endif
		-
		-#pragma push_macro("SM_53")
		-#pragma push_macro("SM_70")
		-#pragma push_macro("SM_72")
		-#pragma push_macro("SM_75")
		-#pragma push_macro("SM_80")
		-#pragma push_macro("SM_86")
		-#pragma push_macro("SM_87")
		-#pragma push_macro("SM_89")
		-#pragma push_macro("SM_90")
		-#pragma push_macro("SM_90a")
		-#pragma push_macro("SM_100")
		-#pragma push_macro("SM_100a")
		-#define SM_100a "sm_100a"
		-#define SM_100 "sm_100|" SM_100a
		-#define SM_90a "sm_90a"
		-#define SM_90 "sm_90|" SM_90a "|" SM_100
		-#define SM_89 "sm_89|" SM_90
		-#define SM_87 "sm_87|" SM_89
		-#define SM_86 "sm_86|" SM_87
		-#define SM_80 "sm_80|" SM_86
		-#define SM_75 "sm_75|" SM_80
		-#define SM_72 "sm_72|" SM_75
		-#define SM_70 "sm_70|" SM_72
		-
		-#pragma push_macro("SM_60")
		-#define SM_60 "sm_60|sm_61|sm_62|" SM_70
		-#define SM_53 "sm_53|" SM_60
		-
		-#pragma push_macro("PTX42")
		-#pragma push_macro("PTX60")
		-#pragma push_macro("PTX61")
		-#pragma push_macro("PTX62")
		-#pragma push_macro("PTX63")
		-#pragma push_macro("PTX64")
		-#pragma push_macro("PTX65")
		-#pragma push_macro("PTX70")
		-#pragma push_macro("PTX71")
		-#pragma push_macro("PTX72")
		-#pragma push_macro("PTX73")
		-#pragma push_macro("PTX74")
		-#pragma push_macro("PTX75")
		-#pragma push_macro("PTX76")
		-#pragma push_macro("PTX77")
		-#pragma push_macro("PTX78")
		-#pragma push_macro("PTX80")
		-#pragma push_macro("PTX81")
		-#pragma push_macro("PTX82")
		-#pragma push_macro("PTX83")
		-#pragma push_macro("PTX84")
		-#pragma push_macro("PTX85")
		-#pragma push_macro("PTX86")
		-#define PTX86 "ptx86"
		-#define PTX85 "ptx85|" PTX86
		-#define PTX84 "ptx84|" PTX85
		-#define PTX83 "ptx83|" PTX84
		-#define PTX82 "ptx82|" PTX83
		-#define PTX81 "ptx81|" PTX82
		-#define PTX80 "ptx80|" PTX81
		-#define PTX78 "ptx78|" PTX80
		-#define PTX77 "ptx77|" PTX78
		-#define PTX76 "ptx76|" PTX77
		-#define PTX75 "ptx75|" PTX76
		-#define PTX74 "ptx74|" PTX75
		-#define PTX73 "ptx73|" PTX74
		-#define PTX72 "ptx72|" PTX73
		-#define PTX71 "ptx71|" PTX72
		-#define PTX70 "ptx70|" PTX71
		-#define PTX65 "ptx65|" PTX70
		-#define PTX64 "ptx64|" PTX65
		-#define PTX63 "ptx63|" PTX64
		-#define PTX62 "ptx62|" PTX63
		-#define PTX61 "ptx61|" PTX62
		-#define PTX60 "ptx60|" PTX61
		-#define PTX42 "ptx42|" PTX60
		-
		-#pragma push_macro("AND")
		-#define AND(a, b) "(" a "),(" b ")"
		-
		-// Special Registers
		-
		-BUILTIN(__nvvm_read_ptx_sreg_tid_x, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_tid_y, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_tid_z, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_tid_w, "i", "nc")
		-
		-BUILTIN(__nvvm_read_ptx_sreg_ntid_x, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_ntid_y, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_ntid_z, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_ntid_w, "i", "nc")
		-
		-BUILTIN(__nvvm_read_ptx_sreg_ctaid_x, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_ctaid_y, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_ctaid_z, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_ctaid_w, "i", "nc")
		-
		-BUILTIN(__nvvm_read_ptx_sreg_nctaid_x, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_nctaid_y, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_nctaid_z, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_nctaid_w, "i", "nc")
		-
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_clusterid_x, "i", "nc", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_clusterid_y, "i", "nc", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_clusterid_z, "i", "nc", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_clusterid_w, "i", "nc", AND(SM_90, PTX78))
		-
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_nclusterid_x, "i", "nc", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_nclusterid_y, "i", "nc", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_nclusterid_z, "i", "nc", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_nclusterid_w, "i", "nc", AND(SM_90, PTX78))
		-
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_cluster_ctaid_x, "i", "nc", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_cluster_ctaid_y, "i", "nc", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_cluster_ctaid_z, "i", "nc", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_cluster_ctaid_w, "i", "nc", AND(SM_90, PTX78))
		-
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_cluster_nctaid_x, "i", "nc", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_cluster_nctaid_y, "i", "nc", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_cluster_nctaid_z, "i", "nc", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_cluster_nctaid_w, "i", "nc", AND(SM_90, PTX78))
		-
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_cluster_ctarank, "i", "nc", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_read_ptx_sreg_cluster_nctarank, "i", "nc", AND(SM_90, PTX78))
		-
		-TARGET_BUILTIN(__nvvm_is_explicit_cluster, "b", "nc", AND(SM_90, PTX78))
		-
		-BUILTIN(__nvvm_read_ptx_sreg_laneid, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_warpid, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_nwarpid, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_warpsize, "i", "nc")
		-
		-BUILTIN(__nvvm_read_ptx_sreg_smid, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_nsmid, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_gridid, "i", "nc")
		-
		-BUILTIN(__nvvm_read_ptx_sreg_lanemask_eq, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_lanemask_le, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_lanemask_lt, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_lanemask_ge, "i", "nc")
		-BUILTIN(__nvvm_read_ptx_sreg_lanemask_gt, "i", "nc")
		-
		-BUILTIN(__nvvm_read_ptx_sreg_clock, "i", "n")
		-BUILTIN(__nvvm_read_ptx_sreg_clock64, "LLi", "n")
		-BUILTIN(__nvvm_read_ptx_sreg_globaltimer, "LLi", "n")
		-
		-BUILTIN(__nvvm_read_ptx_sreg_pm0, "i", "n")
		-BUILTIN(__nvvm_read_ptx_sreg_pm1, "i", "n")
		-BUILTIN(__nvvm_read_ptx_sreg_pm2, "i", "n")
		-BUILTIN(__nvvm_read_ptx_sreg_pm3, "i", "n")
		-
		-// MISC
		-
		-BUILTIN(__nvvm_prmt, "UiUiUiUi", "")
		-BUILTIN(__nvvm_exit, "v", "r")
		-BUILTIN(__nvvm_reflect, "UicC*", "r")
		-TARGET_BUILTIN(__nvvm_nanosleep, "vUi", "n", AND(SM_70, PTX63))
		-
		-// Min Max
		-
		-TARGET_BUILTIN(__nvvm_fmin_f16, "hhh", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_f16, "hhh", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_nan_f16, "hhh", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_nan_f16, "hhh", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_xorsign_abs_f16, "hhh", "", AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_xorsign_abs_f16, "hhh", "", AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmin_nan_xorsign_abs_f16, "hhh", "", AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_nan_xorsign_abs_f16, "hhh", "",
		- AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmin_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_nan_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_nan_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_xorsign_abs_f16x2, "V2hV2hV2h", "",
		- AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_xorsign_abs_f16x2, "V2hV2hV2h", "",
		- AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmin_nan_xorsign_abs_f16x2, "V2hV2hV2h", "",
		- AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_nan_xorsign_abs_f16x2, "V2hV2hV2h", "",
		- AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmin_bf16, "yyy", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_bf16, "yyy", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_nan_bf16, "yyy", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_nan_bf16, "yyy", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_xorsign_abs_bf16, "yyy", "", AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmin_nan_xorsign_abs_bf16, "yyy", "",
		- AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmin_bf16x2, "V2yV2yV2y", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_bf16x2, "V2yV2yV2y", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_nan_bf16x2, "V2yV2yV2y", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_nan_bf16x2, "V2yV2yV2y", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_xorsign_abs_bf16x2, "V2yV2yV2y", "",
		- AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmin_nan_xorsign_abs_bf16x2, "V2yV2yV2y", "",
		- AND(SM_86, PTX72))
		-BUILTIN(__nvvm_fmin_f, "fff", "")
		-BUILTIN(__nvvm_fmin_ftz_f, "fff", "")
		-TARGET_BUILTIN(__nvvm_fmin_nan_f, "fff", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_nan_f, "fff", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmin_xorsign_abs_f, "fff", "", AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_xorsign_abs_f, "fff", "", AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmin_nan_xorsign_abs_f, "fff", "", AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmin_ftz_nan_xorsign_abs_f, "fff", "", AND(SM_86, PTX72))
		-BUILTIN(__nvvm_fmin_d, "ddd", "")
		-
		-TARGET_BUILTIN(__nvvm_fmax_f16, "hhh", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_f16, "hhh", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_nan_f16, "hhh", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_nan_f16, "hhh", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_xorsign_abs_f16, "hhh", "", AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_xorsign_abs_f16, "hhh", "", AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmax_nan_xorsign_abs_f16, "hhh", "", AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_nan_xorsign_abs_f16, "hhh", "",
		- AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmax_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_nan_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_nan_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_xorsign_abs_f16x2, "V2hV2hV2h", "",
		- AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_xorsign_abs_f16x2, "V2hV2hV2h", "",
		- AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmax_nan_xorsign_abs_f16x2, "V2hV2hV2h", "",
		- AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_nan_xorsign_abs_f16x2, "V2hV2hV2h", "",
		- AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmax_bf16, "yyy", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_bf16, "yyy", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_nan_bf16, "yyy", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_nan_bf16, "yyy", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_xorsign_abs_bf16, "yyy", "", AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmax_nan_xorsign_abs_bf16, "yyy", "",
		- AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmax_bf16x2, "V2yV2yV2y", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_bf16x2, "V2yV2yV2y", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_nan_bf16x2, "V2yV2yV2y", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_nan_bf16x2, "V2yV2yV2y", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_xorsign_abs_bf16x2, "V2yV2yV2y", "",
		- AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmax_nan_xorsign_abs_bf16x2, "V2yV2yV2y", "",
		- AND(SM_86, PTX72))
		-BUILTIN(__nvvm_fmax_f, "fff", "")
		-BUILTIN(__nvvm_fmax_ftz_f, "fff", "")
		-TARGET_BUILTIN(__nvvm_fmax_nan_f, "fff", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_nan_f, "fff", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fmax_xorsign_abs_f, "fff", "", AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_xorsign_abs_f, "fff", "", AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmax_nan_xorsign_abs_f, "fff", "", AND(SM_86, PTX72))
		-TARGET_BUILTIN(__nvvm_fmax_ftz_nan_xorsign_abs_f, "fff", "", AND(SM_86, PTX72))
		-BUILTIN(__nvvm_fmax_d, "ddd", "")
		-
		-// Multiplication
		-
		-BUILTIN(__nvvm_mulhi_i, "iii", "")
		-BUILTIN(__nvvm_mulhi_ui, "UiUiUi", "")
		-BUILTIN(__nvvm_mulhi_ll, "LLiLLiLLi", "")
		-BUILTIN(__nvvm_mulhi_ull, "ULLiULLiULLi", "")
		-
		-BUILTIN(__nvvm_mul_rn_ftz_f, "fff", "")
		-BUILTIN(__nvvm_mul_rn_f, "fff", "")
		-BUILTIN(__nvvm_mul_rz_ftz_f, "fff", "")
		-BUILTIN(__nvvm_mul_rz_f, "fff", "")
		-BUILTIN(__nvvm_mul_rm_ftz_f, "fff", "")
		-BUILTIN(__nvvm_mul_rm_f, "fff", "")
		-BUILTIN(__nvvm_mul_rp_ftz_f, "fff", "")
		-BUILTIN(__nvvm_mul_rp_f, "fff", "")
		-
		-BUILTIN(__nvvm_mul_rn_d, "ddd", "")
		-BUILTIN(__nvvm_mul_rz_d, "ddd", "")
		-BUILTIN(__nvvm_mul_rm_d, "ddd", "")
		-BUILTIN(__nvvm_mul_rp_d, "ddd", "")
		-
		-BUILTIN(__nvvm_mul24_i, "iii", "")
		-BUILTIN(__nvvm_mul24_ui, "UiUiUi", "")
		-
		-// Div
		-
		-BUILTIN(__nvvm_div_approx_ftz_f, "fff", "")
		-BUILTIN(__nvvm_div_approx_f, "fff", "")
		-
		-BUILTIN(__nvvm_div_rn_ftz_f, "fff", "")
		-BUILTIN(__nvvm_div_rn_f, "fff", "")
		-BUILTIN(__nvvm_div_rz_ftz_f, "fff", "")
		-BUILTIN(__nvvm_div_rz_f, "fff", "")
		-BUILTIN(__nvvm_div_rm_ftz_f, "fff", "")
		-BUILTIN(__nvvm_div_rm_f, "fff", "")
		-BUILTIN(__nvvm_div_rp_ftz_f, "fff", "")
		-BUILTIN(__nvvm_div_rp_f, "fff", "")
		-
		-BUILTIN(__nvvm_div_rn_d, "ddd", "")
		-BUILTIN(__nvvm_div_rz_d, "ddd", "")
		-BUILTIN(__nvvm_div_rm_d, "ddd", "")
		-BUILTIN(__nvvm_div_rp_d, "ddd", "")
		-
		-// Sad
		-
		-BUILTIN(__nvvm_sad_i, "iiii", "")
		-BUILTIN(__nvvm_sad_ui, "UiUiUiUi", "")
		-
		-// Floor, Ceil
		-
		-BUILTIN(__nvvm_floor_ftz_f, "ff", "")
		-BUILTIN(__nvvm_floor_f, "ff", "")
		-BUILTIN(__nvvm_floor_d, "dd", "")
		-
		-BUILTIN(__nvvm_ceil_ftz_f, "ff", "")
		-BUILTIN(__nvvm_ceil_f, "ff", "")
		-BUILTIN(__nvvm_ceil_d, "dd", "")
		-
		-// Abs
		-
		-BUILTIN(__nvvm_fabs_ftz_f, "ff", "")
		-BUILTIN(__nvvm_fabs_f, "ff", "")
		-BUILTIN(__nvvm_fabs_d, "dd", "")
		-
		-// Round
		-
		-BUILTIN(__nvvm_round_ftz_f, "ff", "")
		-BUILTIN(__nvvm_round_f, "ff", "")
		-BUILTIN(__nvvm_round_d, "dd", "")
		-
		-// Trunc
		-
		-BUILTIN(__nvvm_trunc_ftz_f, "ff", "")
		-BUILTIN(__nvvm_trunc_f, "ff", "")
		-BUILTIN(__nvvm_trunc_d, "dd", "")
		-
		-// Saturate
		-
		-BUILTIN(__nvvm_saturate_ftz_f, "ff", "")
		-BUILTIN(__nvvm_saturate_f, "ff", "")
		-BUILTIN(__nvvm_saturate_d, "dd", "")
		-
		-// Exp2, Log2
		-
		-BUILTIN(__nvvm_ex2_approx_ftz_f, "ff", "")
		-BUILTIN(__nvvm_ex2_approx_f, "ff", "")
		-BUILTIN(__nvvm_ex2_approx_d, "dd", "")
		-TARGET_BUILTIN(__nvvm_ex2_approx_f16, "hh", "", AND(SM_75, PTX70))
		-TARGET_BUILTIN(__nvvm_ex2_approx_f16x2, "V2hV2h", "", AND(SM_75, PTX70))
		-
		-BUILTIN(__nvvm_lg2_approx_ftz_f, "ff", "")
		-BUILTIN(__nvvm_lg2_approx_f, "ff", "")
		-BUILTIN(__nvvm_lg2_approx_d, "dd", "")
		-
		-// Sin, Cos
		-
		-BUILTIN(__nvvm_sin_approx_ftz_f, "ff", "")
		-BUILTIN(__nvvm_sin_approx_f, "ff", "")
		-
		-BUILTIN(__nvvm_cos_approx_ftz_f, "ff", "")
		-BUILTIN(__nvvm_cos_approx_f, "ff", "")
		-
		-// Fma
		-
		-TARGET_BUILTIN(__nvvm_fma_rn_f16, "hhhh", "", AND(SM_53, PTX42))
		-TARGET_BUILTIN(__nvvm_fma_rn_ftz_f16, "hhhh", "", AND(SM_53, PTX42))
		-TARGET_BUILTIN(__nvvm_fma_rn_sat_f16, "hhhh", "", AND(SM_53, PTX42))
		-TARGET_BUILTIN(__nvvm_fma_rn_ftz_sat_f16, "hhhh", "", AND(SM_53, PTX42))
		-TARGET_BUILTIN(__nvvm_fma_rn_relu_f16, "hhhh", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fma_rn_ftz_relu_f16, "hhhh", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fma_rn_f16x2, "V2hV2hV2hV2h", "", AND(SM_53, PTX42))
		-TARGET_BUILTIN(__nvvm_fma_rn_ftz_f16x2, "V2hV2hV2hV2h", "", AND(SM_53, PTX42))
		-TARGET_BUILTIN(__nvvm_fma_rn_sat_f16x2, "V2hV2hV2hV2h", "", AND(SM_53, PTX42))
		-TARGET_BUILTIN(__nvvm_fma_rn_ftz_sat_f16x2, "V2hV2hV2hV2h", "", AND(SM_53, PTX42))
		-TARGET_BUILTIN(__nvvm_fma_rn_relu_f16x2, "V2hV2hV2hV2h", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fma_rn_ftz_relu_f16x2, "V2hV2hV2hV2h", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fma_rn_bf16, "yyyy", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fma_rn_relu_bf16, "yyyy", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fma_rn_bf16x2, "V2yV2yV2yV2y", "", AND(SM_80, PTX70))
		-TARGET_BUILTIN(__nvvm_fma_rn_relu_bf16x2, "V2yV2yV2yV2y", "", AND(SM_80, PTX70))
		-BUILTIN(__nvvm_fma_rn_ftz_f, "ffff", "")
		-BUILTIN(__nvvm_fma_rn_f, "ffff", "")
		-BUILTIN(__nvvm_fma_rz_ftz_f, "ffff", "")
		-BUILTIN(__nvvm_fma_rz_f, "ffff", "")
		-BUILTIN(__nvvm_fma_rm_ftz_f, "ffff", "")
		-BUILTIN(__nvvm_fma_rm_f, "ffff", "")
		-BUILTIN(__nvvm_fma_rp_ftz_f, "ffff", "")
		-BUILTIN(__nvvm_fma_rp_f, "ffff", "")
		-BUILTIN(__nvvm_fma_rn_d, "dddd", "")
		-BUILTIN(__nvvm_fma_rz_d, "dddd", "")
		-BUILTIN(__nvvm_fma_rm_d, "dddd", "")
		-BUILTIN(__nvvm_fma_rp_d, "dddd", "")
		-
		-// Rcp
		-
		-BUILTIN(__nvvm_rcp_rn_ftz_f, "ff", "")
		-BUILTIN(__nvvm_rcp_rn_f, "ff", "")
		-BUILTIN(__nvvm_rcp_rz_ftz_f, "ff", "")
		-BUILTIN(__nvvm_rcp_rz_f, "ff", "")
		-BUILTIN(__nvvm_rcp_rm_ftz_f, "ff", "")
		-BUILTIN(__nvvm_rcp_rm_f, "ff", "")
		-BUILTIN(__nvvm_rcp_rp_ftz_f, "ff", "")
		-BUILTIN(__nvvm_rcp_rp_f, "ff", "")
		-
		-BUILTIN(__nvvm_rcp_rn_d, "dd", "")
		-BUILTIN(__nvvm_rcp_rz_d, "dd", "")
		-BUILTIN(__nvvm_rcp_rm_d, "dd", "")
		-BUILTIN(__nvvm_rcp_rp_d, "dd", "")
		-
		-BUILTIN(__nvvm_rcp_approx_ftz_f, "ff", "")
		-BUILTIN(__nvvm_rcp_approx_ftz_d, "dd", "")
		-
		-// Sqrt
		-
		-BUILTIN(__nvvm_sqrt_rn_ftz_f, "ff", "")
		-BUILTIN(__nvvm_sqrt_rn_f, "ff", "")
		-BUILTIN(__nvvm_sqrt_rz_ftz_f, "ff", "")
		-BUILTIN(__nvvm_sqrt_rz_f, "ff", "")
		-BUILTIN(__nvvm_sqrt_rm_ftz_f, "ff", "")
		-BUILTIN(__nvvm_sqrt_rm_f, "ff", "")
		-BUILTIN(__nvvm_sqrt_rp_ftz_f, "ff", "")
		-BUILTIN(__nvvm_sqrt_rp_f, "ff", "")
		-BUILTIN(__nvvm_sqrt_approx_ftz_f, "ff", "")
		-BUILTIN(__nvvm_sqrt_approx_f, "ff", "")
		-
		-BUILTIN(__nvvm_sqrt_rn_d, "dd", "")
		-BUILTIN(__nvvm_sqrt_rz_d, "dd", "")
		-BUILTIN(__nvvm_sqrt_rm_d, "dd", "")
		-BUILTIN(__nvvm_sqrt_rp_d, "dd", "")
		-
		-// Rsqrt
		-
		-BUILTIN(__nvvm_rsqrt_approx_ftz_f, "ff", "")
		-BUILTIN(__nvvm_rsqrt_approx_f, "ff", "")
		-BUILTIN(__nvvm_rsqrt_approx_d, "dd", "")
		-
		-// Add
		-
		-BUILTIN(__nvvm_add_rn_ftz_f, "fff", "")
		-BUILTIN(__nvvm_add_rn_f, "fff", "")
		-BUILTIN(__nvvm_add_rz_ftz_f, "fff", "")
		-BUILTIN(__nvvm_add_rz_f, "fff", "")
		-BUILTIN(__nvvm_add_rm_ftz_f, "fff", "")
		-BUILTIN(__nvvm_add_rm_f, "fff", "")
		-BUILTIN(__nvvm_add_rp_ftz_f, "fff", "")
		-BUILTIN(__nvvm_add_rp_f, "fff", "")
		-
		-BUILTIN(__nvvm_add_rn_d, "ddd", "")
		-BUILTIN(__nvvm_add_rz_d, "ddd", "")
		-BUILTIN(__nvvm_add_rm_d, "ddd", "")
		-BUILTIN(__nvvm_add_rp_d, "ddd", "")
		-
		-// Convert
		-
		-BUILTIN(__nvvm_d2f_rn_ftz, "fd", "")
		-BUILTIN(__nvvm_d2f_rn, "fd", "")
		-BUILTIN(__nvvm_d2f_rz_ftz, "fd", "")
		-BUILTIN(__nvvm_d2f_rz, "fd", "")
		-BUILTIN(__nvvm_d2f_rm_ftz, "fd", "")
		-BUILTIN(__nvvm_d2f_rm, "fd", "")
		-BUILTIN(__nvvm_d2f_rp_ftz, "fd", "")
		-BUILTIN(__nvvm_d2f_rp, "fd", "")
		-
		-BUILTIN(__nvvm_d2i_rn, "id", "")
		-BUILTIN(__nvvm_d2i_rz, "id", "")
		-BUILTIN(__nvvm_d2i_rm, "id", "")
		-BUILTIN(__nvvm_d2i_rp, "id", "")
		-
		-BUILTIN(__nvvm_d2ui_rn, "Uid", "")
		-BUILTIN(__nvvm_d2ui_rz, "Uid", "")
		-BUILTIN(__nvvm_d2ui_rm, "Uid", "")
		-BUILTIN(__nvvm_d2ui_rp, "Uid", "")
		-
		-BUILTIN(__nvvm_i2d_rn, "di", "")
		-BUILTIN(__nvvm_i2d_rz, "di", "")
		-BUILTIN(__nvvm_i2d_rm, "di", "")
		-BUILTIN(__nvvm_i2d_rp, "di", "")
		-
		-BUILTIN(__nvvm_ui2d_rn, "dUi", "")
		-BUILTIN(__nvvm_ui2d_rz, "dUi", "")
		-BUILTIN(__nvvm_ui2d_rm, "dUi", "")
		-BUILTIN(__nvvm_ui2d_rp, "dUi", "")
		-
		-BUILTIN(__nvvm_f2i_rn_ftz, "if", "")
		-BUILTIN(__nvvm_f2i_rn, "if", "")
		-BUILTIN(__nvvm_f2i_rz_ftz, "if", "")
		-BUILTIN(__nvvm_f2i_rz, "if", "")
		-BUILTIN(__nvvm_f2i_rm_ftz, "if", "")
		-BUILTIN(__nvvm_f2i_rm, "if", "")
		-BUILTIN(__nvvm_f2i_rp_ftz, "if", "")
		-BUILTIN(__nvvm_f2i_rp, "if", "")
		-
		-BUILTIN(__nvvm_f2ui_rn_ftz, "Uif", "")
		-BUILTIN(__nvvm_f2ui_rn, "Uif", "")
		-BUILTIN(__nvvm_f2ui_rz_ftz, "Uif", "")
		-BUILTIN(__nvvm_f2ui_rz, "Uif", "")
		-BUILTIN(__nvvm_f2ui_rm_ftz, "Uif", "")
		-BUILTIN(__nvvm_f2ui_rm, "Uif", "")
		-BUILTIN(__nvvm_f2ui_rp_ftz, "Uif", "")
		-BUILTIN(__nvvm_f2ui_rp, "Uif", "")
		-
		-BUILTIN(__nvvm_i2f_rn, "fi", "")
		-BUILTIN(__nvvm_i2f_rz, "fi", "")
		-BUILTIN(__nvvm_i2f_rm, "fi", "")
		-BUILTIN(__nvvm_i2f_rp, "fi", "")
		-
		-BUILTIN(__nvvm_ui2f_rn, "fUi", "")
		-BUILTIN(__nvvm_ui2f_rz, "fUi", "")
		-BUILTIN(__nvvm_ui2f_rm, "fUi", "")
		-BUILTIN(__nvvm_ui2f_rp, "fUi", "")
		-
		-BUILTIN(__nvvm_lohi_i2d, "dii", "")
		-
		-BUILTIN(__nvvm_d2i_lo, "id", "")
		-BUILTIN(__nvvm_d2i_hi, "id", "")
		-
		-BUILTIN(__nvvm_f2ll_rn_ftz, "LLif", "")
		-BUILTIN(__nvvm_f2ll_rn, "LLif", "")
		-BUILTIN(__nvvm_f2ll_rz_ftz, "LLif", "")
		-BUILTIN(__nvvm_f2ll_rz, "LLif", "")
		-BUILTIN(__nvvm_f2ll_rm_ftz, "LLif", "")
		-BUILTIN(__nvvm_f2ll_rm, "LLif", "")
		-BUILTIN(__nvvm_f2ll_rp_ftz, "LLif", "")
		-BUILTIN(__nvvm_f2ll_rp, "LLif", "")
		-
		-BUILTIN(__nvvm_f2ull_rn_ftz, "ULLif", "")
		-BUILTIN(__nvvm_f2ull_rn, "ULLif", "")
		-BUILTIN(__nvvm_f2ull_rz_ftz, "ULLif", "")
		-BUILTIN(__nvvm_f2ull_rz, "ULLif", "")
		-BUILTIN(__nvvm_f2ull_rm_ftz, "ULLif", "")
		-BUILTIN(__nvvm_f2ull_rm, "ULLif", "")
		-BUILTIN(__nvvm_f2ull_rp_ftz, "ULLif", "")
		-BUILTIN(__nvvm_f2ull_rp, "ULLif", "")
		-
		-BUILTIN(__nvvm_d2ll_rn, "LLid", "")
		-BUILTIN(__nvvm_d2ll_rz, "LLid", "")
		-BUILTIN(__nvvm_d2ll_rm, "LLid", "")
		-BUILTIN(__nvvm_d2ll_rp, "LLid", "")
		-
		-BUILTIN(__nvvm_d2ull_rn, "ULLid", "")
		-BUILTIN(__nvvm_d2ull_rz, "ULLid", "")
		-BUILTIN(__nvvm_d2ull_rm, "ULLid", "")
		-BUILTIN(__nvvm_d2ull_rp, "ULLid", "")
		-
		-BUILTIN(__nvvm_ll2f_rn, "fLLi", "")
		-BUILTIN(__nvvm_ll2f_rz, "fLLi", "")
		-BUILTIN(__nvvm_ll2f_rm, "fLLi", "")
		-BUILTIN(__nvvm_ll2f_rp, "fLLi", "")
		-
		-BUILTIN(__nvvm_ull2f_rn, "fULLi", "")
		-BUILTIN(__nvvm_ull2f_rz, "fULLi", "")
		-BUILTIN(__nvvm_ull2f_rm, "fULLi", "")
		-BUILTIN(__nvvm_ull2f_rp, "fULLi", "")
		-
		-BUILTIN(__nvvm_ll2d_rn, "dLLi", "")
		-BUILTIN(__nvvm_ll2d_rz, "dLLi", "")
		-BUILTIN(__nvvm_ll2d_rm, "dLLi", "")
		-BUILTIN(__nvvm_ll2d_rp, "dLLi", "")
		-
		-BUILTIN(__nvvm_ull2d_rn, "dULLi", "")
		-BUILTIN(__nvvm_ull2d_rz, "dULLi", "")
		-BUILTIN(__nvvm_ull2d_rm, "dULLi", "")
		-BUILTIN(__nvvm_ull2d_rp, "dULLi", "")
		-
		-BUILTIN(__nvvm_f2h_rn_ftz, "Usf", "")
		-BUILTIN(__nvvm_f2h_rn, "Usf", "")
		-
		-TARGET_BUILTIN(__nvvm_ff2bf16x2_rn, "V2yff", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_ff2bf16x2_rn_relu, "V2yff", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_ff2bf16x2_rz, "V2yff", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_ff2bf16x2_rz_relu, "V2yff", "", AND(SM_80,PTX70))
		-
		-TARGET_BUILTIN(__nvvm_ff2f16x2_rn, "V2hff", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_ff2f16x2_rn_relu, "V2hff", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_ff2f16x2_rz, "V2hff", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_ff2f16x2_rz_relu, "V2hff", "", AND(SM_80,PTX70))
		-
		-TARGET_BUILTIN(__nvvm_f2bf16_rn, "yf", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_f2bf16_rn_relu, "yf", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_f2bf16_rz, "yf", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_f2bf16_rz_relu, "yf", "", AND(SM_80,PTX70))
		-
		-TARGET_BUILTIN(__nvvm_f2tf32_rna, "ZUif", "", AND(SM_80,PTX70))
		-
		-TARGET_BUILTIN(__nvvm_ff_to_e4m3x2_rn, "sff", "", AND(SM_89,PTX81))
		-TARGET_BUILTIN(__nvvm_ff_to_e4m3x2_rn_relu, "sff", "", AND(SM_89,PTX81))
		-TARGET_BUILTIN(__nvvm_ff_to_e5m2x2_rn, "sff", "", AND(SM_89,PTX81))
		-TARGET_BUILTIN(__nvvm_ff_to_e5m2x2_rn_relu, "sff", "", AND(SM_89,PTX81))
		-
		-TARGET_BUILTIN(__nvvm_f16x2_to_e4m3x2_rn, "sV2h", "", AND(SM_89,PTX81))
		-TARGET_BUILTIN(__nvvm_f16x2_to_e4m3x2_rn_relu, "sV2h", "", AND(SM_89,PTX81))
		-TARGET_BUILTIN(__nvvm_f16x2_to_e5m2x2_rn, "sV2h", "", AND(SM_89,PTX81))
		-TARGET_BUILTIN(__nvvm_f16x2_to_e5m2x2_rn_relu, "sV2h", "", AND(SM_89,PTX81))
		-
		-TARGET_BUILTIN(__nvvm_e4m3x2_to_f16x2_rn, "V2hs", "", AND(SM_89,PTX81))
		-TARGET_BUILTIN(__nvvm_e4m3x2_to_f16x2_rn_relu, "V2hs", "", AND(SM_89,PTX81))
		-TARGET_BUILTIN(__nvvm_e5m2x2_to_f16x2_rn, "V2hs", "", AND(SM_89,PTX81))
		-TARGET_BUILTIN(__nvvm_e5m2x2_to_f16x2_rn_relu, "V2hs", "", AND(SM_89,PTX81))
		-
		-// FNS
		-TARGET_BUILTIN(__nvvm_fns, "UiUiUii", "n", PTX60)
		-
		-// Sync
		-
		-BUILTIN(__syncthreads, "v", "")
		-BUILTIN(__nvvm_bar0_popc, "ii", "")
		-BUILTIN(__nvvm_bar0_and, "ii", "")
		-BUILTIN(__nvvm_bar0_or, "ii", "")
		-BUILTIN(__nvvm_bar_sync, "vi", "n")
		-TARGET_BUILTIN(__nvvm_bar_warp_sync, "vUi", "n", PTX60)
		-TARGET_BUILTIN(__nvvm_barrier_sync, "vUi", "n", PTX60)
		-TARGET_BUILTIN(__nvvm_barrier_sync_cnt, "vUiUi", "n", PTX60)
		-
		-TARGET_BUILTIN(__nvvm_barrier_cluster_arrive, "v", "n", AND(SM_90,PTX78))
		-TARGET_BUILTIN(__nvvm_barrier_cluster_arrive_relaxed, "v", "n", AND(SM_90,PTX80))
		-TARGET_BUILTIN(__nvvm_barrier_cluster_wait, "v", "n", AND(SM_90,PTX78))
		-TARGET_BUILTIN(__nvvm_fence_sc_cluster, "v", "n", AND(SM_90,PTX78))
		-
		-// Shuffle
		-
		-BUILTIN(__nvvm_shfl_down_i32, "iiii", "")
		-BUILTIN(__nvvm_shfl_down_f32, "ffii", "")
		-BUILTIN(__nvvm_shfl_up_i32, "iiii", "")
		-BUILTIN(__nvvm_shfl_up_f32, "ffii", "")
		-BUILTIN(__nvvm_shfl_bfly_i32, "iiii", "")
		-BUILTIN(__nvvm_shfl_bfly_f32, "ffii", "")
		-BUILTIN(__nvvm_shfl_idx_i32, "iiii", "")
		-BUILTIN(__nvvm_shfl_idx_f32, "ffii", "")
		-
		-TARGET_BUILTIN(__nvvm_shfl_sync_down_i32, "iUiiii", "", PTX60)
		-TARGET_BUILTIN(__nvvm_shfl_sync_down_f32, "fUifii", "", PTX60)
		-TARGET_BUILTIN(__nvvm_shfl_sync_up_i32, "iUiiii", "", PTX60)
		-TARGET_BUILTIN(__nvvm_shfl_sync_up_f32, "fUifii", "", PTX60)
		-TARGET_BUILTIN(__nvvm_shfl_sync_bfly_i32, "iUiiii", "", PTX60)
		-TARGET_BUILTIN(__nvvm_shfl_sync_bfly_f32, "fUifii", "", PTX60)
		-TARGET_BUILTIN(__nvvm_shfl_sync_idx_i32, "iUiiii", "", PTX60)
		-TARGET_BUILTIN(__nvvm_shfl_sync_idx_f32, "fUifii", "", PTX60)
		-
		-// Vote
		-BUILTIN(__nvvm_vote_all, "bb", "")
		-BUILTIN(__nvvm_vote_any, "bb", "")
		-BUILTIN(__nvvm_vote_uni, "bb", "")
		-BUILTIN(__nvvm_vote_ballot, "Uib", "")
		-
		-TARGET_BUILTIN(__nvvm_vote_all_sync, "bUib", "", PTX60)
		-TARGET_BUILTIN(__nvvm_vote_any_sync, "bUib", "", PTX60)
		-TARGET_BUILTIN(__nvvm_vote_uni_sync, "bUib", "", PTX60)
		-TARGET_BUILTIN(__nvvm_vote_ballot_sync, "UiUib", "", PTX60)
		-
		-// Mask
		-TARGET_BUILTIN(__nvvm_activemask, "Ui", "n", PTX62)
		-
		-// Match
		-TARGET_BUILTIN(__nvvm_match_any_sync_i32, "UiUiUi", "", AND(SM_70,PTX60))
		-TARGET_BUILTIN(__nvvm_match_any_sync_i64, "UiUiWi", "", AND(SM_70,PTX60))
		-// These return a pair {value, predicate}, which requires custom lowering.
		-TARGET_BUILTIN(__nvvm_match_all_sync_i32p, "UiUiUii*", "", AND(SM_70,PTX60))
		-TARGET_BUILTIN(__nvvm_match_all_sync_i64p, "UiUiWii*", "", AND(SM_70,PTX60))
		-
		-// Redux
		-TARGET_BUILTIN(__nvvm_redux_sync_add, "iii", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_redux_sync_min, "iii", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_redux_sync_max, "iii", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_redux_sync_umin, "UiUii", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_redux_sync_umax, "UiUii", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_redux_sync_and, "iii", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_redux_sync_xor, "iii", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_redux_sync_or, "iii", "", AND(SM_80,PTX70))
		-
		-// Membar
		-
		-BUILTIN(__nvvm_membar_cta, "v", "")
		-BUILTIN(__nvvm_membar_gl, "v", "")
		-BUILTIN(__nvvm_membar_sys, "v", "")
		-
		-// mbarrier
		-
		-TARGET_BUILTIN(__nvvm_mbarrier_init, "vWi*i", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_mbarrier_init_shared, "vWi*3i", "", AND(SM_80,PTX70))
		-
		-TARGET_BUILTIN(__nvvm_mbarrier_inval, "vWi*", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_mbarrier_inval_shared, "vWi*3", "", AND(SM_80,PTX70))
		-
		-TARGET_BUILTIN(__nvvm_mbarrier_arrive, "WiWi*", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_mbarrier_arrive_shared, "WiWi*3", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_mbarrier_arrive_noComplete, "WiWi*i", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_mbarrier_arrive_noComplete_shared, "WiWi*3i", "", AND(SM_80,PTX70))
		-
		-TARGET_BUILTIN(__nvvm_mbarrier_arrive_drop, "WiWi*", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_mbarrier_arrive_drop_shared, "WiWi*3", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_mbarrier_arrive_drop_noComplete, "WiWi*i", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_mbarrier_arrive_drop_noComplete_shared, "WiWi*3i", "", AND(SM_80,PTX70))
		-
		-TARGET_BUILTIN(__nvvm_mbarrier_test_wait, "bWi*Wi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_mbarrier_test_wait_shared, "bWi*3Wi", "", AND(SM_80,PTX70))
		-
		-TARGET_BUILTIN(__nvvm_mbarrier_pending_count, "iWi", "", AND(SM_80,PTX70))
		-
		-// Memcpy, Memset
		-
		-BUILTIN(__nvvm_memcpy, "vUc*Uc*zi","")
		-BUILTIN(__nvvm_memset, "vUc*Uczi","")
		-
		-// Image
		-
		-BUILTIN(__builtin_ptx_read_image2Dfi_, "V4fiiii", "")
		-BUILTIN(__builtin_ptx_read_image2Dff_, "V4fiiff", "")
		-BUILTIN(__builtin_ptx_read_image2Dii_, "V4iiiii", "")
		-BUILTIN(__builtin_ptx_read_image2Dif_, "V4iiiff", "")
		-
		-BUILTIN(__builtin_ptx_read_image3Dfi_, "V4fiiiiii", "")
		-BUILTIN(__builtin_ptx_read_image3Dff_, "V4fiiffff", "")
		-BUILTIN(__builtin_ptx_read_image3Dii_, "V4iiiiiii", "")
		-BUILTIN(__builtin_ptx_read_image3Dif_, "V4iiiffff", "")
		-
		-BUILTIN(__builtin_ptx_write_image2Df_, "viiiffff", "")
		-BUILTIN(__builtin_ptx_write_image2Di_, "viiiiiii", "")
		-BUILTIN(__builtin_ptx_write_image2Dui_, "viiiUiUiUiUi", "")
		-BUILTIN(__builtin_ptx_get_image_depthi_, "ii", "")
		-BUILTIN(__builtin_ptx_get_image_heighti_, "ii", "")
		-BUILTIN(__builtin_ptx_get_image_widthi_, "ii", "")
		-BUILTIN(__builtin_ptx_get_image_channel_data_typei_, "ii", "")
		-BUILTIN(__builtin_ptx_get_image_channel_orderi_, "ii", "")
		-
		-// Atomic
		-//
		-// We need the atom intrinsics because
		-// - they are used in converging analysis
		-// - they are used in address space analysis and optimization
		-// So it does not hurt to expose them as builtins.
		-//
		-BUILTIN(__nvvm_atom_add_gen_i, "iiD*i", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_add_gen_i, "iiD*i", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_add_gen_i, "iiD*i", "n", SM_60)
		-BUILTIN(__nvvm_atom_add_gen_l, "LiLiD*Li", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_add_gen_l, "LiLiD*Li", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_add_gen_l, "LiLiD*Li", "n", SM_60)
		-BUILTIN(__nvvm_atom_add_gen_ll, "LLiLLiD*LLi", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_add_gen_ll, "LLiLLiD*LLi", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_add_gen_ll, "LLiLLiD*LLi", "n", SM_60)
		-BUILTIN(__nvvm_atom_add_gen_f, "ffD*f", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_add_gen_f, "ffD*f", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_add_gen_f, "ffD*f", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_add_gen_d, "ddD*d", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_cta_add_gen_d, "ddD*d", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_add_gen_d, "ddD*d", "n", SM_60)
		-
		-BUILTIN(__nvvm_atom_sub_gen_i, "iiD*i", "n")
		-BUILTIN(__nvvm_atom_sub_gen_l, "LiLiD*Li", "n")
		-BUILTIN(__nvvm_atom_sub_gen_ll, "LLiLLiD*LLi", "n")
		-
		-BUILTIN(__nvvm_atom_xchg_gen_i, "iiD*i", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_xchg_gen_i, "iiD*i", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_xchg_gen_i, "iiD*i", "n", SM_60)
		-BUILTIN(__nvvm_atom_xchg_gen_l, "LiLiD*Li", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_xchg_gen_l, "LiLiD*Li", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_xchg_gen_l, "LiLiD*Li", "n", SM_60)
		-BUILTIN(__nvvm_atom_xchg_gen_ll, "LLiLLiD*LLi", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_xchg_gen_ll, "LLiLLiD*LLi", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_xchg_gen_ll, "LLiLLiD*LLi", "n", SM_60)
		-
		-BUILTIN(__nvvm_atom_max_gen_i, "iiD*i", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_max_gen_i, "iiD*i", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_max_gen_i, "iiD*i", "n", SM_60)
		-BUILTIN(__nvvm_atom_max_gen_ui, "UiUiD*Ui", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_max_gen_ui, "UiUiD*Ui", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_max_gen_ui, "UiUiD*Ui", "n", SM_60)
		-BUILTIN(__nvvm_atom_max_gen_l, "LiLiD*Li", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_max_gen_l, "LiLiD*Li", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_max_gen_l, "LiLiD*Li", "n", SM_60)
		-BUILTIN(__nvvm_atom_max_gen_ul, "ULiULiD*ULi", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_max_gen_ul, "ULiULiD*ULi", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_max_gen_ul, "ULiULiD*ULi", "n", SM_60)
		-BUILTIN(__nvvm_atom_max_gen_ll, "LLiLLiD*LLi", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_max_gen_ll, "LLiLLiD*LLi", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_max_gen_ll, "LLiLLiD*LLi", "n", SM_60)
		-BUILTIN(__nvvm_atom_max_gen_ull, "ULLiULLiD*ULLi", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_max_gen_ull, "ULLiULLiD*ULLi", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_max_gen_ull, "ULLiULLiD*ULLi", "n", SM_60)
		-
		-BUILTIN(__nvvm_atom_min_gen_i, "iiD*i", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_min_gen_i, "iiD*i", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_min_gen_i, "iiD*i", "n", SM_60)
		-BUILTIN(__nvvm_atom_min_gen_ui, "UiUiD*Ui", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_min_gen_ui, "UiUiD*Ui", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_min_gen_ui, "UiUiD*Ui", "n", SM_60)
		-BUILTIN(__nvvm_atom_min_gen_l, "LiLiD*Li", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_min_gen_l, "LiLiD*Li", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_min_gen_l, "LiLiD*Li", "n", SM_60)
		-BUILTIN(__nvvm_atom_min_gen_ul, "ULiULiD*ULi", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_min_gen_ul, "ULiULiD*ULi", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_min_gen_ul, "ULiULiD*ULi", "n", SM_60)
		-BUILTIN(__nvvm_atom_min_gen_ll, "LLiLLiD*LLi", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_min_gen_ll, "LLiLLiD*LLi", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_min_gen_ll, "LLiLLiD*LLi", "n", SM_60)
		-BUILTIN(__nvvm_atom_min_gen_ull, "ULLiULLiD*ULLi", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_min_gen_ull, "ULLiULLiD*ULLi", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_min_gen_ull, "ULLiULLiD*ULLi", "n", SM_60)
		-
		-BUILTIN(__nvvm_atom_inc_gen_ui, "UiUiD*Ui", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_inc_gen_ui, "UiUiD*Ui", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_inc_gen_ui, "UiUiD*Ui", "n", SM_60)
		-BUILTIN(__nvvm_atom_dec_gen_ui, "UiUiD*Ui", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_dec_gen_ui, "UiUiD*Ui", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_dec_gen_ui, "UiUiD*Ui", "n", SM_60)
		-
		-BUILTIN(__nvvm_atom_and_gen_i, "iiD*i", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_and_gen_i, "iiD*i", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_and_gen_i, "iiD*i", "n", SM_60)
		-BUILTIN(__nvvm_atom_and_gen_l, "LiLiD*Li", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_and_gen_l, "LiLiD*Li", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_and_gen_l, "LiLiD*Li", "n", SM_60)
		-BUILTIN(__nvvm_atom_and_gen_ll, "LLiLLiD*LLi", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_and_gen_ll, "LLiLLiD*LLi", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_and_gen_ll, "LLiLLiD*LLi", "n", SM_60)
		-
		-BUILTIN(__nvvm_atom_or_gen_i, "iiD*i", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_or_gen_i, "iiD*i", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_or_gen_i, "iiD*i", "n", SM_60)
		-BUILTIN(__nvvm_atom_or_gen_l, "LiLiD*Li", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_or_gen_l, "LiLiD*Li", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_or_gen_l, "LiLiD*Li", "n", SM_60)
		-BUILTIN(__nvvm_atom_or_gen_ll, "LLiLLiD*LLi", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_or_gen_ll, "LLiLLiD*LLi", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_or_gen_ll, "LLiLLiD*LLi", "n", SM_60)
		-
		-BUILTIN(__nvvm_atom_xor_gen_i, "iiD*i", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_xor_gen_i, "iiD*i", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_xor_gen_i, "iiD*i", "n", SM_60)
		-BUILTIN(__nvvm_atom_xor_gen_l, "LiLiD*Li", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_xor_gen_l, "LiLiD*Li", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_xor_gen_l, "LiLiD*Li", "n", SM_60)
		-BUILTIN(__nvvm_atom_xor_gen_ll, "LLiLLiD*LLi", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_xor_gen_ll, "LLiLLiD*LLi", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_xor_gen_ll, "LLiLLiD*LLi", "n", SM_60)
		-
		-TARGET_BUILTIN(__nvvm_atom_cas_gen_us, "UsUsD*UsUs", "n", SM_70)
		-TARGET_BUILTIN(__nvvm_atom_cta_cas_gen_us, "UsUsD*UsUs", "n", SM_70)
		-TARGET_BUILTIN(__nvvm_atom_sys_cas_gen_us, "UsUsD*UsUs", "n", SM_70)
		-BUILTIN(__nvvm_atom_cas_gen_i, "iiD*ii", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_cas_gen_i, "iiD*ii", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_cas_gen_i, "iiD*ii", "n", SM_60)
		-BUILTIN(__nvvm_atom_cas_gen_l, "LiLiD*LiLi", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_cas_gen_l, "LiLiD*LiLi", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_cas_gen_l, "LiLiD*LiLi", "n", SM_60)
		-BUILTIN(__nvvm_atom_cas_gen_ll, "LLiLLiD*LLiLLi", "n")
		-TARGET_BUILTIN(__nvvm_atom_cta_cas_gen_ll, "LLiLLiD*LLiLLi", "n", SM_60)
		-TARGET_BUILTIN(__nvvm_atom_sys_cas_gen_ll, "LLiLLiD*LLiLLi", "n", SM_60)
		-
		-// Compiler Error Warn
		-BUILTIN(__nvvm_compiler_error, "vcC*4", "n")
		-BUILTIN(__nvvm_compiler_warn, "vcC*4", "n")
		-
		-BUILTIN(__nvvm_ldu_c, "ccC*", "")
		-BUILTIN(__nvvm_ldu_sc, "ScScC*", "")
		-BUILTIN(__nvvm_ldu_s, "ssC*", "")
		-BUILTIN(__nvvm_ldu_i, "iiC*", "")
		-BUILTIN(__nvvm_ldu_l, "LiLiC*", "")
		-BUILTIN(__nvvm_ldu_ll, "LLiLLiC*", "")
		-
		-BUILTIN(__nvvm_ldu_uc, "UcUcC*", "")
		-BUILTIN(__nvvm_ldu_us, "UsUsC*", "")
		-BUILTIN(__nvvm_ldu_ui, "UiUiC*", "")
		-BUILTIN(__nvvm_ldu_ul, "ULiULiC*", "")
		-BUILTIN(__nvvm_ldu_ull, "ULLiULLiC*", "")
		-
		-BUILTIN(__nvvm_ldu_h, "hhC*", "")
		-BUILTIN(__nvvm_ldu_f, "ffC*", "")
		-BUILTIN(__nvvm_ldu_d, "ddC*", "")
		-
		-BUILTIN(__nvvm_ldu_c2, "E2cE2cC*", "")
		-BUILTIN(__nvvm_ldu_sc2, "E2ScE2ScC*", "")
		-BUILTIN(__nvvm_ldu_c4, "E4cE4cC*", "")
		-BUILTIN(__nvvm_ldu_sc4, "E4ScE4ScC*", "")
		-BUILTIN(__nvvm_ldu_s2, "E2sE2sC*", "")
		-BUILTIN(__nvvm_ldu_s4, "E4sE4sC*", "")
		-BUILTIN(__nvvm_ldu_i2, "E2iE2iC*", "")
		-BUILTIN(__nvvm_ldu_i4, "E4iE4iC*", "")
		-BUILTIN(__nvvm_ldu_l2, "E2LiE2LiC*", "")
		-BUILTIN(__nvvm_ldu_ll2, "E2LLiE2LLiC*", "")
		-
		-BUILTIN(__nvvm_ldu_uc2, "E2UcE2UcC*", "")
		-BUILTIN(__nvvm_ldu_uc4, "E4UcE4UcC*", "")
		-BUILTIN(__nvvm_ldu_us2, "E2UsE2UsC*", "")
		-BUILTIN(__nvvm_ldu_us4, "E4UsE4UsC*", "")
		-BUILTIN(__nvvm_ldu_ui2, "E2UiE2UiC*", "")
		-BUILTIN(__nvvm_ldu_ui4, "E4UiE4UiC*", "")
		-BUILTIN(__nvvm_ldu_ul2, "E2ULiE2ULiC*", "")
		-BUILTIN(__nvvm_ldu_ull2, "E2ULLiE2ULLiC*", "")
		-
		-BUILTIN(__nvvm_ldu_h2, "E2hE2hC*", "")
		-BUILTIN(__nvvm_ldu_f2, "E2fE2fC*", "")
		-BUILTIN(__nvvm_ldu_f4, "E4fE4fC*", "")
		-BUILTIN(__nvvm_ldu_d2, "E2dE2dC*", "")
		-
		-BUILTIN(__nvvm_ldg_c, "ccC*", "")
		-BUILTIN(__nvvm_ldg_sc, "ScScC*", "")
		-BUILTIN(__nvvm_ldg_s, "ssC*", "")
		-BUILTIN(__nvvm_ldg_i, "iiC*", "")
		-BUILTIN(__nvvm_ldg_l, "LiLiC*", "")
		-BUILTIN(__nvvm_ldg_ll, "LLiLLiC*", "")
		-
		-BUILTIN(__nvvm_ldg_uc, "UcUcC*", "")
		-BUILTIN(__nvvm_ldg_us, "UsUsC*", "")
		-BUILTIN(__nvvm_ldg_ui, "UiUiC*", "")
		-BUILTIN(__nvvm_ldg_ul, "ULiULiC*", "")
		-BUILTIN(__nvvm_ldg_ull, "ULLiULLiC*", "")
		-
		-BUILTIN(__nvvm_ldg_h, "hhC*", "")
		-BUILTIN(__nvvm_ldg_f, "ffC*", "")
		-BUILTIN(__nvvm_ldg_d, "ddC*", "")
		-
		-BUILTIN(__nvvm_ldg_c2, "E2cE2cC*", "")
		-BUILTIN(__nvvm_ldg_sc2, "E2ScE2ScC*", "")
		-BUILTIN(__nvvm_ldg_c4, "E4cE4cC*", "")
		-BUILTIN(__nvvm_ldg_sc4, "E4ScE4ScC*", "")
		-BUILTIN(__nvvm_ldg_s2, "E2sE2sC*", "")
		-BUILTIN(__nvvm_ldg_s4, "E4sE4sC*", "")
		-BUILTIN(__nvvm_ldg_i2, "E2iE2iC*", "")
		-BUILTIN(__nvvm_ldg_i4, "E4iE4iC*", "")
		-BUILTIN(__nvvm_ldg_l2, "E2LiE2LiC*", "")
		-BUILTIN(__nvvm_ldg_ll2, "E2LLiE2LLiC*", "")
		-
		-BUILTIN(__nvvm_ldg_uc2, "E2UcE2UcC*", "")
		-BUILTIN(__nvvm_ldg_uc4, "E4UcE4UcC*", "")
		-BUILTIN(__nvvm_ldg_us2, "E2UsE2UsC*", "")
		-BUILTIN(__nvvm_ldg_us4, "E4UsE4UsC*", "")
		-BUILTIN(__nvvm_ldg_ui2, "E2UiE2UiC*", "")
		-BUILTIN(__nvvm_ldg_ui4, "E4UiE4UiC*", "")
		-BUILTIN(__nvvm_ldg_ul2, "E2ULiE2ULiC*", "")
		-BUILTIN(__nvvm_ldg_ull2, "E2ULLiE2ULLiC*", "")
		-
		-BUILTIN(__nvvm_ldg_h2, "E2hE2hC*", "")
		-BUILTIN(__nvvm_ldg_f2, "E2fE2fC*", "")
		-BUILTIN(__nvvm_ldg_f4, "E4fE4fC*", "")
		-BUILTIN(__nvvm_ldg_d2, "E2dE2dC*", "")
		-
		-// Address space predicates.
		-BUILTIN(__nvvm_isspacep_const, "bvC*", "nc")
		-BUILTIN(__nvvm_isspacep_global, "bvC*", "nc")
		-BUILTIN(__nvvm_isspacep_local, "bvC*", "nc")
		-BUILTIN(__nvvm_isspacep_shared, "bvC*", "nc")
		-TARGET_BUILTIN(__nvvm_isspacep_shared_cluster,"bvC*", "nc", AND(SM_90,PTX78))
		-
		-// Builtins to support WMMA instructions on sm_70
		-TARGET_BUILTIN(__hmma_m16n16k16_ld_a, "vi*iC*UiIi", "", AND(SM_70,PTX60))
		-TARGET_BUILTIN(__hmma_m16n16k16_ld_b, "vi*iC*UiIi", "", AND(SM_70,PTX60))
		-TARGET_BUILTIN(__hmma_m16n16k16_ld_c_f16, "vi*iC*UiIi", "", AND(SM_70,PTX60))
		-TARGET_BUILTIN(__hmma_m16n16k16_ld_c_f32, "vf*fC*UiIi", "", AND(SM_70,PTX60))
		-TARGET_BUILTIN(__hmma_m16n16k16_st_c_f16, "vi*iC*UiIi", "", AND(SM_70,PTX60))
		-TARGET_BUILTIN(__hmma_m16n16k16_st_c_f32, "vf*fC*UiIi", "", AND(SM_70,PTX60))
		-
		-TARGET_BUILTIN(__hmma_m32n8k16_ld_a, "vi*iC*UiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m32n8k16_ld_b, "vi*iC*UiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m32n8k16_ld_c_f16, "vi*iC*UiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m32n8k16_ld_c_f32, "vf*fC*UiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m32n8k16_st_c_f16, "vi*iC*UiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m32n8k16_st_c_f32, "vf*fC*UiIi", "", AND(SM_70,PTX61))
		-
		-TARGET_BUILTIN(__hmma_m8n32k16_ld_a, "vi*iC*UiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m8n32k16_ld_b, "vi*iC*UiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m8n32k16_ld_c_f16, "vi*iC*UiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m8n32k16_ld_c_f32, "vf*fC*UiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m8n32k16_st_c_f16, "vi*iC*UiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m8n32k16_st_c_f32, "vf*fC*UiIi", "", AND(SM_70,PTX61))
		-
		-TARGET_BUILTIN(__hmma_m16n16k16_mma_f16f16, "vi*iC*iC*iC*IiIi", "", AND(SM_70,PTX60))
		-TARGET_BUILTIN(__hmma_m16n16k16_mma_f32f16, "vf*iC*iC*iC*IiIi", "", AND(SM_70,PTX60))
		-TARGET_BUILTIN(__hmma_m16n16k16_mma_f32f32, "vf*iC*iC*fC*IiIi", "", AND(SM_70,PTX60))
		-TARGET_BUILTIN(__hmma_m16n16k16_mma_f16f32, "vi*iC*iC*fC*IiIi", "", AND(SM_70,PTX60))
		-
		-TARGET_BUILTIN(__hmma_m32n8k16_mma_f16f16, "vi*iC*iC*iC*IiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m32n8k16_mma_f32f16, "vf*iC*iC*iC*IiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m32n8k16_mma_f32f32, "vf*iC*iC*fC*IiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m32n8k16_mma_f16f32, "vi*iC*iC*fC*IiIi", "", AND(SM_70,PTX61))
		-
		-TARGET_BUILTIN(__hmma_m8n32k16_mma_f16f16, "vi*iC*iC*iC*IiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m8n32k16_mma_f32f16, "vf*iC*iC*iC*IiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m8n32k16_mma_f32f32, "vf*iC*iC*fC*IiIi", "", AND(SM_70,PTX61))
		-TARGET_BUILTIN(__hmma_m8n32k16_mma_f16f32, "vi*iC*iC*fC*IiIi", "", AND(SM_70,PTX61))
		-
		-// Builtins to support integer and sub-integer WMMA instructions on sm_72/sm_75
		-TARGET_BUILTIN(__bmma_m8n8k128_ld_a_b1, "vi*iC*UiIi", "", AND(SM_75,PTX63))
		-TARGET_BUILTIN(__bmma_m8n8k128_ld_b_b1, "vi*iC*UiIi", "", AND(SM_75,PTX63))
		-TARGET_BUILTIN(__bmma_m8n8k128_ld_c, "vi*iC*UiIi", "", AND(SM_75,PTX63))
		-TARGET_BUILTIN(__bmma_m8n8k128_mma_and_popc_b1, "vi*iC*iC*iC*Ii", "", AND(SM_80,PTX71))
		-TARGET_BUILTIN(__bmma_m8n8k128_mma_xor_popc_b1, "vi*iC*iC*iC*Ii", "", AND(SM_75,PTX63))
		-TARGET_BUILTIN(__bmma_m8n8k128_st_c_i32, "vi*iC*UiIi", "", AND(SM_75,PTX63))
		-TARGET_BUILTIN(__imma_m16n16k16_ld_a_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m16n16k16_ld_a_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m16n16k16_ld_b_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m16n16k16_ld_b_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m16n16k16_ld_c, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m16n16k16_mma_s8, "vi*iC*iC*iC*IiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m16n16k16_mma_u8, "vi*iC*iC*iC*IiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m16n16k16_st_c_i32, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m32n8k16_ld_a_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m32n8k16_ld_a_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m32n8k16_ld_b_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m32n8k16_ld_b_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m32n8k16_ld_c, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m32n8k16_mma_s8, "vi*iC*iC*iC*IiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m32n8k16_mma_u8, "vi*iC*iC*iC*IiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m32n8k16_st_c_i32, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m8n32k16_ld_a_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m8n32k16_ld_a_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m8n32k16_ld_b_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m8n32k16_ld_b_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m8n32k16_ld_c, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m8n32k16_mma_s8, "vi*iC*iC*iC*IiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m8n32k16_mma_u8, "vi*iC*iC*iC*IiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m8n32k16_st_c_i32, "vi*iC*UiIi", "", AND(SM_72,PTX63))
		-TARGET_BUILTIN(__imma_m8n8k32_ld_a_s4, "vi*iC*UiIi", "", AND(SM_75,PTX63))
		-TARGET_BUILTIN(__imma_m8n8k32_ld_a_u4, "vi*iC*UiIi", "", AND(SM_75,PTX63))
		-TARGET_BUILTIN(__imma_m8n8k32_ld_b_s4, "vi*iC*UiIi", "", AND(SM_75,PTX63))
		-TARGET_BUILTIN(__imma_m8n8k32_ld_b_u4, "vi*iC*UiIi", "", AND(SM_75,PTX63))
		-TARGET_BUILTIN(__imma_m8n8k32_ld_c, "vi*iC*UiIi", "", AND(SM_75,PTX63))
		-TARGET_BUILTIN(__imma_m8n8k32_mma_s4, "vi*iC*iC*iC*IiIi", "", AND(SM_75,PTX63))
		-TARGET_BUILTIN(__imma_m8n8k32_mma_u4, "vi*iC*iC*iC*IiIi", "", AND(SM_75,PTX63))
		-TARGET_BUILTIN(__imma_m8n8k32_st_c_i32, "vi*iC*UiIi", "", AND(SM_75,PTX63))
		-
		-// Builtins to support double and alternate float WMMA instructions on sm_80
		-TARGET_BUILTIN(__dmma_m8n8k4_ld_a, "vd*dC*UiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__dmma_m8n8k4_ld_b, "vd*dC*UiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__dmma_m8n8k4_ld_c, "vd*dC*UiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__dmma_m8n8k4_st_c_f64, "vd*dC*UiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__dmma_m8n8k4_mma_f64, "vd*dC*dC*dC*IiIi", "", AND(SM_80,PTX70))
		-
		-TARGET_BUILTIN(__mma_bf16_m16n16k16_ld_a, "vi*iC*UiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__mma_bf16_m16n16k16_ld_b, "vi*iC*UiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__mma_bf16_m16n16k16_mma_f32, "vf*iC*iC*fC*IiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__mma_bf16_m8n32k16_ld_a, "vi*iC*UiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__mma_bf16_m8n32k16_ld_b, "vi*iC*UiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__mma_bf16_m8n32k16_mma_f32, "vf*iC*iC*fC*IiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__mma_bf16_m32n8k16_ld_a, "vi*iC*UiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__mma_bf16_m32n8k16_ld_b, "vi*iC*UiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__mma_bf16_m32n8k16_mma_f32, "vf*iC*iC*fC*IiIi", "", AND(SM_80,PTX70))
		-
		-TARGET_BUILTIN(__mma_tf32_m16n16k8_ld_a, "vi*iC*UiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__mma_tf32_m16n16k8_ld_b, "vi*iC*UiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__mma_tf32_m16n16k8_ld_c, "vf*fC*UiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__mma_m16n16k8_st_c_f32, "vf*fC*UiIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__mma_tf32_m16n16k8_mma_f32, "vf*iC*iC*fC*IiIi", "", AND(SM_80,PTX70))
		-
		-// Async Copy
		-TARGET_BUILTIN(__nvvm_cp_async_mbarrier_arrive, "vWi*", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_cp_async_mbarrier_arrive_shared, "vWi*3", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_cp_async_mbarrier_arrive_noinc, "vWi*", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_cp_async_mbarrier_arrive_noinc_shared, "vWi*3", "", AND(SM_80,PTX70))
		-
		-TARGET_BUILTIN(__nvvm_cp_async_ca_shared_global_4, "vv*3vC*1.", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_cp_async_ca_shared_global_8, "vv*3vC*1.", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_cp_async_ca_shared_global_16, "vv*3vC*1.", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_cp_async_cg_shared_global_16, "vv*3vC*1.", "", AND(SM_80,PTX70))
		-
		-TARGET_BUILTIN(__nvvm_cp_async_commit_group, "v", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_cp_async_wait_group, "vIi", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_cp_async_wait_all, "v", "", AND(SM_80,PTX70))
		-
		-
		-// bf16, bf16x2 abs, neg
		-TARGET_BUILTIN(__nvvm_abs_bf16, "yy", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_abs_bf16x2, "V2yV2y", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_neg_bf16, "yy", "", AND(SM_80,PTX70))
		-TARGET_BUILTIN(__nvvm_neg_bf16x2, "V2yV2y", "", AND(SM_80,PTX70))
		-
		-TARGET_BUILTIN(__nvvm_mapa, "v*v*i", "", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_mapa_shared_cluster, "v*3v*3i", "", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_getctarank, "iv*", "", AND(SM_90, PTX78))
		-TARGET_BUILTIN(__nvvm_getctarank_shared_cluster, "iv*3", "", AND(SM_90,PTX78))
		-
		-#undef BUILTIN
		-#undef TARGET_BUILTIN
		-#pragma pop_macro("AND")
		-#pragma pop_macro("SM_53")
		-#pragma pop_macro("SM_60")
		-#pragma pop_macro("SM_70")
		-#pragma pop_macro("SM_72")
		-#pragma pop_macro("SM_75")
		-#pragma pop_macro("SM_80")
		-#pragma pop_macro("SM_86")
		-#pragma pop_macro("SM_87")
		-#pragma pop_macro("SM_89")
		-#pragma pop_macro("SM_90")
		-#pragma pop_macro("SM_90a")
		-#pragma pop_macro("SM_100")
		-#pragma pop_macro("SM_100a")
		-#pragma pop_macro("PTX42")
		-#pragma pop_macro("PTX60")
		-#pragma pop_macro("PTX61")
		-#pragma pop_macro("PTX62")
		-#pragma pop_macro("PTX63")
		-#pragma pop_macro("PTX64")
		-#pragma pop_macro("PTX65")
		-#pragma pop_macro("PTX70")
		-#pragma pop_macro("PTX71")
		-#pragma pop_macro("PTX72")
		-#pragma pop_macro("PTX73")
		-#pragma pop_macro("PTX74")
		-#pragma pop_macro("PTX75")
		-#pragma pop_macro("PTX76")
		-#pragma pop_macro("PTX77")
		-#pragma pop_macro("PTX78")
		-#pragma pop_macro("PTX80")
		-#pragma pop_macro("PTX81")
		-#pragma pop_macro("PTX82")
		-#pragma pop_macro("PTX83")
		-#pragma pop_macro("PTX84")
		-#pragma pop_macro("PTX85")
		-#pragma pop_macro("PTX86")

clang/include/clang/Basic/BuiltinsNVPTX.td

		@@ -0,0 +1,1079 @@
		+//===--- BuiltinsNVPTX.td - NVPTX Builtin function defs ---------*- C++ -*-===//
		+//
		+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
		+// See https://llvm.org/LICENSE.txt for license information.
		+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
		+//
		+//===----------------------------------------------------------------------===//
		+//
		+// This file defines the PTX-specific builtin function database.
		+//
		+//===----------------------------------------------------------------------===//
		+
		+include "clang/Basic/BuiltinsBase.td"
		+
		+class SMFeatures {
		+ string Features;
		+}
		+
		+class SM<string version, list<SMFeatures> newer_list> : SMFeatures {
		+ let Features = !foldl(!strconcat("sm_", version), newer_list, f, newer,
		+ !strconcat(f, "|", newer.Features));
		+}
		+
		+let Features = "sm_100a" in def SM_100a : SMFeatures;
		+
		+def SM_100 : SM<"100", [SM_100a]>;
		+
		+let Features = "sm_90a" in def SM_90a : SMFeatures;
		+
		+def SM_90 : SM<"90", [SM_90a, SM_100]>;
		+def SM_89 : SM<"89", [SM_90]>;
		+def SM_87 : SM<"87", [SM_89]>;
		+def SM_86 : SM<"86", [SM_87]>;
		+def SM_80 : SM<"80", [SM_86]>;
		+def SM_75 : SM<"75", [SM_80]>;
		+def SM_72 : SM<"72", [SM_75]>;
		+def SM_70 : SM<"70", [SM_72]>;
		+def SM_62 : SM<"62", [SM_70]>;
		+def SM_61 : SM<"61", [SM_62]>;
		+def SM_60 : SM<"60", [SM_61]>;
		+def SM_53 : SM<"53", [SM_60]>;
		+
		+class PTXFeatures {
		+ string Features;
		+}
		+
		+class PTX<string version, PTXFeatures newer> : PTXFeatures {
		+ let Features = !strconcat("ptx", version, "|", newer.Features);
		+}
		+
		+let Features = "ptx87" in def PTX87 : PTXFeatures;
		+
		+def PTX86 : PTX<"86", PTX87>;
		+def PTX85 : PTX<"85", PTX86>;
		+def PTX84 : PTX<"84", PTX85>;
		+def PTX83 : PTX<"83", PTX84>;
		+def PTX82 : PTX<"82", PTX83>;
		+def PTX81 : PTX<"81", PTX82>;
		+def PTX80 : PTX<"80", PTX81>;
		+def PTX78 : PTX<"78", PTX80>;
		+def PTX77 : PTX<"77", PTX78>;
		+def PTX76 : PTX<"76", PTX77>;
		+def PTX75 : PTX<"75", PTX76>;
		+def PTX74 : PTX<"74", PTX75>;
		+def PTX73 : PTX<"73", PTX74>;
		+def PTX72 : PTX<"72", PTX73>;
		+def PTX71 : PTX<"71", PTX72>;
		+def PTX70 : PTX<"70", PTX71>;
		+def PTX65 : PTX<"65", PTX70>;
		+def PTX64 : PTX<"64", PTX65>;
		+def PTX63 : PTX<"63", PTX64>;
		+def PTX62 : PTX<"62", PTX63>;
		+def PTX61 : PTX<"61", PTX62>;
		+def PTX60 : PTX<"60", PTX61>;
		+def PTX42 : PTX<"42", PTX60>;
		+
		+class NVPTXBuiltin<string prototype> : TargetBuiltin {
		+ let Spellings = [NAME];
		+ let Prototype = prototype;
		+}
		+
		+class NVPTXBuiltinSM<string prototype, SMFeatures sm> : NVPTXBuiltin<prototype> {
		+ let Features = sm.Features;
		+}
		+
		+class NVPTXBuiltinPTX<string prototype, PTXFeatures ptx> : NVPTXBuiltin<prototype> {
		+ let Features = ptx.Features;
		+}
		+
		+class NVPTXBuiltinSMAndPTX<string prototype, SMFeatures sm, PTXFeatures ptx> : NVPTXBuiltin<prototype> {
		+ let Features = !strconcat("(", sm.Features, "),(", ptx.Features, ")");
		+}
		+
		+// Special Registers
		+
		+let Attributes = [NoThrow, Const] in {
		+ def __nvvm_read_ptx_sreg_tid_x : NVPTXBuiltin<"int()">;
		+ def __nvvm_read_ptx_sreg_tid_y : NVPTXBuiltin<"int()">;
		+ def __nvvm_read_ptx_sreg_tid_z : NVPTXBuiltin<"int()">;
		+ def __nvvm_read_ptx_sreg_tid_w : NVPTXBuiltin<"int()">;
		+
		+ def __nvvm_read_ptx_sreg_ntid_x : NVPTXBuiltin<"int()">;
		+ def __nvvm_read_ptx_sreg_ntid_y : NVPTXBuiltin<"int()">;
		+ def __nvvm_read_ptx_sreg_ntid_z : NVPTXBuiltin<"int()">;
		+ def __nvvm_read_ptx_sreg_ntid_w : NVPTXBuiltin<"int()">;
		+
		+ def __nvvm_read_ptx_sreg_ctaid_x : NVPTXBuiltin<"int()">;
		+ def __nvvm_read_ptx_sreg_ctaid_y : NVPTXBuiltin<"int()">;
		+ def __nvvm_read_ptx_sreg_ctaid_z : NVPTXBuiltin<"int()">;
		+ def __nvvm_read_ptx_sreg_ctaid_w : NVPTXBuiltin<"int()">;
		+
		+ def __nvvm_read_ptx_sreg_nctaid_x : NVPTXBuiltin<"int()">;
		+ def __nvvm_read_ptx_sreg_nctaid_y : NVPTXBuiltin<"int()">;
		+ def __nvvm_read_ptx_sreg_nctaid_z : NVPTXBuiltin<"int()">;
		+ def __nvvm_read_ptx_sreg_nctaid_w : NVPTXBuiltin<"int()">;
		+
		+ def __nvvm_read_ptx_sreg_clusterid_x : NVPTXBuiltinSMAndPTX<"int()", SM_90, PTX78>;
		+ def __nvvm_read_ptx_sreg_clusterid_y : NVPTXBuiltinSMAndPTX<"int()", SM_90, PTX78>;
		+ def __nvvm_read_ptx_sreg_clusterid_z : NVPTXBuiltinSMAndPTX<"int()", SM_90, PTX78>;
		+ def __nvvm_read_ptx_sreg_clusterid_w : NVPTXBuiltinSMAndPTX<"int()", SM_90, PTX78>;
		+
		+ def __nvvm_read_ptx_sreg_nclusterid_x : NVPTXBuiltinSMAndPTX<"int()", SM_90, PTX78>;
		+ def __nvvm_read_ptx_sreg_nclusterid_y : NVPTXBuiltinSMAndPTX<"int()", SM_90, PTX78>;
		+ def __nvvm_read_ptx_sreg_nclusterid_z : NVPTXBuiltinSMAndPTX<"int()", SM_90, PTX78>;
		+ def __nvvm_read_ptx_sreg_nclusterid_w : NVPTXBuiltinSMAndPTX<"int()", SM_90, PTX78>;
		+
		+ def __nvvm_read_ptx_sreg_cluster_ctaid_x : NVPTXBuiltinSMAndPTX<"int()", SM_90, PTX78>;
		+ def __nvvm_read_ptx_sreg_cluster_ctaid_y : NVPTXBuiltinSMAndPTX<"int()", SM_90, PTX78>;
		+ def __nvvm_read_ptx_sreg_cluster_ctaid_z : NVPTXBuiltinSMAndPTX<"int()", SM_90, PTX78>;
		+ def __nvvm_read_ptx_sreg_cluster_ctaid_w : NVPTXBuiltinSMAndPTX<"int()", SM_90, PTX78>;
		+
		+ def __nvvm_read_ptx_sreg_cluster_nctaid_x : NVPTXBuiltinSMAndPTX<"int()", SM_90, PTX78>;
		[diff truncated]