HardenedBSD / src / 84943d6

  DT_SCHEMA_LINT = $(shell which yamllint || \
    echo "warning: python package 'yamllint' not installed, skipping" >&2)
--DT_SCHEMA_MIN_VERSION = 2022.3
++DT_SCHEMA_MIN_VERSION = 2023.9
  PHONY += check_dtschema_version
  check_dtschema_version:

sys/contrib/device-tree/Bindings/arm/amd,pensando.yaml
@@ -0,0 +1,26 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/arm/amd,pensando.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: AMD Pensando SoC Platforms
			+
			+maintainers:
			+ - Brad Larson <blarson@amd.com>
			+
			+properties:
			+ $nodename:
			+ const: "/"
			+ compatible:
			+ oneOf:
			+
			+ - description: Boards with Pensando Elba SoC
			+ items:
			+ - enum:
			+ - amd,pensando-elba-ortano
			+ - const: amd,pensando-elba
			+
			+additionalProperties: true
			+
			+...

            - enum:
                - bananapi,bpi-m2s
                - khadas,vim3
++              - libretech,aml-a311d-cc
                - radxa,zero2
            - const: amlogic,a311d
            - const: amlogic,g12b
                - hardkernel,odroid-hc4
                - haochuangyi,h96-max
                - khadas,vim3l
++              - libretech,aml-s905d3-cc
                - seirobotics,sei610
            - const: amlogic,sm1
          items:
            - enum:
                - amlogic,ad401
++              - amlogic,ad402
            - const: amlogic,a1
        - description: Boards with the Amlogic C3 C302X/C308L SoC

sys/contrib/device-tree/Bindings/arm/arm,coresight-cti.yaml
@@ -92,11 +92,8 @@ properties:
	maxItems: 1	maxItems: 1

	cpu:	cpu:
	- $ref: /schemas/types.yaml#/definitions/phandle
	description:	description:
	- Handle to cpu this ~~device~~ is associated with. ~~This must appear in the~~	+ Handle to cpu this CTI is associated with.
	- base cti node if compatible string arm,coresight-cti-v8-arch is used,
	- or may appear in a trig-conns child node when appropriate.

	power-domains:	power-domains:
	maxItems: 1	maxItems: 1
@@ -113,12 +110,12 @@ properties:
	description:	description:
	defines a phandle reference to an associated CoreSight trace device.	defines a phandle reference to an associated CoreSight trace device.
	When the associated trace device is enabled, then the respective CTI	When the associated trace device is enabled, then the respective CTI
	- will be enabled. Use in ~~a trig-conns node, or in~~ CTI base node when	+ will be enabled. Use in CTI base node when compatible string
	- ~~compatible string~~ arm,coresight-cti-v8-arch used. If the associated	+ arm,coresight-cti-v8-arch used. If the associated device has not been
	- ~~device has not been~~ registered then the node name will be stored as	+ registered then the node name will be stored as the connection name for
	- ~~the connection name for~~ later resolution. If the associated device is	+ later resolution. If the associated device is not a CoreSight device or
	- not ~~a CoreSight device or not~~ registered then the node name will remain	+ not registered then the node name will remain the connection name and
	- ~~the connection name and~~ automatic enabling will not occur.	+ automatic enabling will not occur.

	# size cells and address cells required if trig-conns node present.	# size cells and address cells required if trig-conns node present.
	"#size-cells":	"#size-cells":
@@ -130,6 +127,8 @@ properties:
	patternProperties:	patternProperties:
	'^trig-conns@([0-9]+)$':	'^trig-conns@([0-9]+)$':
	type: object	type: object
		+ additionalProperties: false
		+
	description:	description:
	A trigger connections child node which describes the trigger signals	A trigger connections child node which describes the trigger signals
	between this CTI and another hardware device. This device may be a CPU,	between this CTI and another hardware device. This device may be a CPU,
@@ -141,6 +140,21 @@ patternProperties:
	reg:	reg:
	maxItems: 1	maxItems: 1

		+ cpu:
		+ description:
		+ Handle to cpu this trigger connection is associated with.
		+
		+ arm,cs-dev-assoc:
		+ $ref: /schemas/types.yaml#/definitions/phandle
		+ description:
		+ defines a phandle reference to an associated CoreSight trace device.
		+ When the associated trace device is enabled, then the respective CTI
		+ will be enabled. If the associated device has not been registered
		+ then the node name will be stored as the connection name for later
		+ resolution. If the associated device is not a CoreSight device or
		+ not registered then the node name will remain the connection name
		+ and automatic enabling will not occur.
		+
	arm,trig-in-sigs:	arm,trig-in-sigs:
	$ref: /schemas/types.yaml#/definitions/uint32-array	$ref: /schemas/types.yaml#/definitions/uint32-array
	minItems: 1	minItems: 1

sys/contrib/device-tree/Bindings/arm/arm,integrator.yaml
@@ -40,45 +40,6 @@ properties:
	items:	items:
	- const: arm,integrator-sp	- const: arm,integrator-sp

	- core-module@10000000:
	- type: object
	- description: the root node in the Integrator platforms must contain
	- a core module child node. They are always at physical address
	- 0x10000000 in all the Integrator variants.
	- properties:
	- compatible:
	- items:
	- - const: arm,core-module-integrator
	- - const: syscon
	- - const: simple-mfd
	- reg:
	- maxItems: 1
	-
	- required:
	- - compatible
	- - reg
	-
	-patternProperties:
	- "^syscon@[0-9a-f]+$":
	- description: All Integrator boards must provide a system controller as a
	- node in the root of the device tree.
	- type: object
	- properties:
	- compatible:
	- items:
	- - enum:
	- - arm,integrator-ap-syscon
	- - arm,integrator-cp-syscon
	- - arm,integrator-sp-syscon
	- - const: syscon
	- reg:
	- maxItems: 1
	-
	- required:
	- - compatible
	- - reg
	-
	-
	required:	required:
	- compatible	- compatible
	- core-module@10000000	- core-module@10000000

sys/contrib/device-tree/Bindings/arm/arm,realview.yaml
@@ -75,43 +75,6 @@ properties:
	type: object	type: object
	description: All RealView boards must provide a syscon system controller	description: All RealView boards must provide a syscon system controller
	node inside the soc node.	node inside the soc node.
	- properties:
	- compatible:
	- oneOf:
	- - items:
	- - const: arm,realview-eb11mp-revb-syscon
	- - const: arm,realview-eb-syscon
	- - const: syscon
	- - const: simple-mfd
	- - items:
	- - const: arm,realview-eb11mp-revc-syscon
	- - const: arm,realview-eb-syscon
	- - const: syscon
	- - const: simple-mfd
	- - items:
	- - const: arm,realview-eb-syscon
	- - const: syscon
	- - const: simple-mfd
	- - items:
	- - const: arm,realview-pb1176-syscon
	- - const: syscon
	- - const: simple-mfd
	- - items:
	- - const: arm,realview-pb11mp-syscon
	- - const: syscon
	- - const: simple-mfd
	- - items:
	- - const: arm,realview-pba8-syscon
	- - const: syscon
	- - const: simple-mfd
	- - items:
	- - const: arm,realview-pbx-syscon
	- - const: syscon
	- - const: simple-mfd
	-
	- required:
	- - compatible
	- - reg

	required:	required:
	- compatible	- compatible

sys/contrib/device-tree/Bindings/arm/arm,versatile.yaml
@@ -14,6 +14,14 @@ description: \|+
	with various pluggable interface boards, in essence the Versatile PB version	with various pluggable interface boards, in essence the Versatile PB version
	is a superset of the Versatile AB version.	is a superset of the Versatile AB version.

		+ The root node in the Versatile platforms must contain a core module child
		+ node. They are always at physical address 0x10000000 in all the Versatile
		+ variants.
		+
		+ When fitted with the IB2 Interface Board, the Versatile AB will present an
		+ optional system controller node which controls the extra peripherals on the
		+ interface board.
		+
	properties:	properties:
	$nodename:	$nodename:
	const: '/'	const: '/'
@@ -32,38 +40,6 @@ properties:
	items:	items:
	- const: arm,versatile-pb	- const: arm,versatile-pb

	- core-module@10000000:
	- type: object
	- description: the root node in the Versatile platforms must contain
	- a core module child node. They are always at physical address
	- 0x10000000 in all the Versatile variants.
	- properties:
	- compatible:
	- items:
	- - const: arm,core-module-versatile
	- - const: syscon
	- - const: simple-mfd
	- reg:
	- maxItems: 1
	-
	- required:
	- - compatible
	- - reg
	-
	-patternProperties:
	- "^syscon@[0-9a-f]+$":
	- type: object
	- description: When fitted with the IB2 Interface Board, the Versatile
	- AB will present an optional system controller node which controls the
	- extra peripherals on the interface board.
	- properties:
	- compatible:
	- contains:
	- const: arm,versatile-ib2-syscon
	- required:
	- - compatible
	- - reg
	-
	required:	required:
	- compatible	- compatible
	- core-module@10000000	- core-module@10000000

                - facebook,elbert-bmc
                - facebook,fuji-bmc
                - facebook,greatlakes-bmc
++              - facebook,minerva-cmc
                - facebook,yosemite4-bmc
                - ibm,everest-bmc
                - ibm,rainier-bmc

sys/contrib/device-tree/Bindings/arm/atmel-at91.yaml
@@ -79,6 +79,13 @@ properties:
	- const: atmel,sama5d2	- const: atmel,sama5d2
	- const: atmel,sama5	- const: atmel,sama5

		+ - description: Microchip SAMA5D29 Curiosity
		+ items:
		+ - const: microchip,sama5d29-curiosity
		+ - const: atmel,sama5d29
		+ - const: atmel,sama5d2
		+ - const: atmel,sama5
		+
	- items:	- items:
	- const: atmel,sama5d27	- const: atmel,sama5d27
	- const: atmel,sama5d2	- const: atmel,sama5d2

        - qcom,kryo280
        - qcom,kryo360
        - qcom,kryo385
++      - qcom,kryo465
        - qcom,kryo468
        - qcom,kryo485
        - qcom,kryo560
        power-domains property.
        For PSCI based platforms, the name corresponding to the index of the PSCI
--      PM domain provider, must be "psci".
++      PM domain provider, must be "psci". For SCMI based platforms, the name
++      corresponding to the index of an SCMI performance domain provider, must be
++      "perf".
    qcom,saw:
      $ref: /schemas/types.yaml#/definitions/phandle

sys/contrib/device-tree/Bindings/arm/fsl.yaml
@@ -25,8 +25,11 @@ properties:
	- description: i.MX23 based Boards	- description: i.MX23 based Boards
	items:	items:
	- enum:	- enum:
		+ - creative,x-fi3
	- fsl,imx23-evk	- fsl,imx23-evk
		+ - fsl,stmp378x-devb
	- olimex,imx23-olinuxino	- olimex,imx23-olinuxino
		+ - sandisk,sansa_fuze_plus
	- const: fsl,imx23	- const: fsl,imx23

	- description: i.MX25 Product Development Kit	- description: i.MX25 Product Development Kit
@@ -385,6 +388,12 @@ properties:
	- const: toradex,apalis_imx6q	- const: toradex,apalis_imx6q
	- const: fsl,imx6q	- const: fsl,imx6q

		+ - description: i.MX6Q Variscite VAR-SOM-MX6 Boards
		+ items:
		+ - const: variscite,mx6customboard
		+ - const: variscite,var-som-imx6q
		+ - const: fsl,imx6q
		+
	- description: TQ-Systems TQMa6Q SoM (variant A) on MBa6x	- description: TQ-Systems TQMa6Q SoM (variant A) on MBa6x
	items:	items:
	- const: tq,imx6q-mba6x-a	- const: tq,imx6q-mba6x-a
@@ -975,7 +984,9 @@ properties:

	- description: PHYTEC phyCORE-i.MX8MM SoM based boards	- description: PHYTEC phyCORE-i.MX8MM SoM based boards
	items:	items:
	- - const: phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK	+ - enum:
		+ - phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK
		+ - phytec,imx8mm-phygate-tauri-l # phyGATE-Tauri-L Gateway
	- const: phytec,imx8mm-phycore-som # phyCORE-i.MX8MM SoM	- const: phytec,imx8mm-phycore-som # phyCORE-i.MX8MM SoM
	- const: fsl,imx8mm	- const: fsl,imx8mm

@@ -1389,6 +1400,13 @@ properties:
	- fsl,ls1043a-qds	- fsl,ls1043a-qds
	- const: fsl,ls1043a	- const: fsl,ls1043a

		+ - description: TQ-Systems LS1043A based Boards
		+ items:
		+ - enum:
		+ - tq,ls1043a-tqmls1043a-mbls10xxa
		+ - const: tq,ls1043a-tqmls1043a
		+ - const: fsl,ls1043a
		+
	- description: LS1046A based Boards	- description: LS1046A based Boards
	items:	items:
	- enum:	- enum:
@@ -1397,6 +1415,13 @@ properties:
	- fsl,ls1046a-rdb	- fsl,ls1046a-rdb
	- const: fsl,ls1046a	- const: fsl,ls1046a

		+ - description: TQ-Systems LS1046A based Boards
		+ items:
		+ - enum:
		+ - tq,ls1046a-tqmls1046a-mbls10xxa
		+ - const: tq,ls1046a-tqmls1046a
		+ - const: fsl,ls1046a
		+
	- description: LS1088A based Boards	- description: LS1088A based Boards
	items:	items:
	- enum:	- enum:
@@ -1404,6 +1429,13 @@ properties:
	- fsl,ls1088a-rdb	- fsl,ls1088a-rdb
	- const: fsl,ls1088a	- const: fsl,ls1088a

		+ - description: TQ-Systems LS1088A based Boards
		+ items:
		+ - enum:
		+ - tq,ls1088a-tqmls1088a-mbls10xxa
		+ - const: tq,ls1088a-tqmls1088a
		+ - const: fsl,ls1088a
		+
	- description: LS2080A based Boards	- description: LS2080A based Boards
	items:	items:
	- enum:	- enum:
@@ -1429,7 +1461,7 @@ properties:
	- fsl,lx2162a-qds	- fsl,lx2162a-qds
	- const: fsl,lx2160a	- const: fsl,lx2160a

	- - description: SolidRun LX2160A based Boards	+ - description: SolidRun LX2160A CEX-7 based Boards
	items:	items:
	- enum:	- enum:
	- solidrun,clearfog-cx	- solidrun,clearfog-cx
@@ -1437,6 +1469,13 @@ properties:
	- const: solidrun,lx2160a-cex7	- const: solidrun,lx2160a-cex7
	- const: fsl,lx2160a	- const: fsl,lx2160a

		+ - description: SolidRun LX2162A SoM based Boards
		+ items:
		+ - enum:
		+ - solidrun,lx2162a-clearfog
		+ - const: solidrun,lx2162a-som
		+ - const: fsl,lx2160a
		+
	- description: S32G2 based Boards	- description: S32G2 based Boards
	items:	items:
	- enum:	- enum:

sys/contrib/device-tree/Bindings/arm/intel-ixp4xx.yaml
@@ -16,12 +16,28 @@ properties:
	oneOf:	oneOf:
	- items:	- items:
	- enum:	- enum:
		+ - adieng,coyote
		+ - arcom,vulcan
		+ - dlink,dsm-g600-a
		+ - freecom,fsg-3
		+ - gateway,7001
		+ - gateworks,gw2348
		+ - goramo,multilink-router
		+ - intel,ixdp425
		+ - intel,ixdpg425
		+ - iom,nas-100d
	- linksys,nslu2	- linksys,nslu2
		+ - netgear,wg302v1
		+ - netgear,wg302v2
		+ - usr,8200
	- welltech,epbx100	- welltech,epbx100
		+ - linksys,wrv54g
		+ - gemtek,gtwx5715
	- const: intel,ixp42x	- const: intel,ixp42x
	- items:	- items:
	- enum:	- enum:
	- gateworks,gw2358	- gateworks,gw2358
		+ - intel,kixrp435
	- const: intel,ixp43x	- const: intel,ixp43x

	additionalProperties: true	additionalProperties: true

sys/contrib/device-tree/Bindings/arm/mediatek.yaml
@@ -133,11 +133,22 @@ properties:
	- enum:	- enum:
	- mediatek,mt8183-evb	- mediatek,mt8183-evb
	- const: mediatek,mt8183	- const: mediatek,mt8183
		+ - description: Google Hayato rev5
		+ items:
		+ - const: google,hayato-rev5-sku2
		+ - const: google,hayato-sku2
		+ - const: google,hayato
		+ - const: mediatek,mt8192
	- description: Google Hayato	- description: Google Hayato
	items:	items:
	- const: google,hayato-rev1	- const: google,hayato-rev1
	- const: google,hayato	- const: google,hayato
	- const: mediatek,mt8192	- const: mediatek,mt8192
		+ - description: Google Spherion rev4 (Acer Chromebook 514)
		+ items:
		+ - const: google,spherion-rev4
		+ - const: google,spherion
		+ - const: mediatek,mt8192
	- description: Google Spherion (Acer Chromebook 514)	- description: Google Spherion (Acer Chromebook 514)
	items:	items:
	- const: google,spherion-rev3	- const: google,spherion-rev3
@@ -248,6 +259,11 @@ properties:
	- enum:	- enum:
	- mediatek,mt8365-evk	- mediatek,mt8365-evk
	- const: mediatek,mt8365	- const: mediatek,mt8365
		+ - items:
		+ - enum:
		+ - mediatek,mt8395-evk
		+ - const: mediatek,mt8395
		+ - const: mediatek,mt8195
	- items:	- items:
	- enum:	- enum:
	- mediatek,mt8516-pumpkin	- mediatek,mt8516-pumpkin

            - mediatek,mt7622-wed
            - mediatek,mt7981-wed
            - mediatek,mt7986-wed
++          - mediatek,mt7988-wed
        - const: syscon
    reg:

  patternProperties:
    "^power-domain-":
      $ref: /schemas/power/power-domain.yaml#
++    unevaluatedProperties: false
      type: object
      description: |

sys/contrib/device-tree/Bindings/arm/qcom.yaml
@@ -50,6 +50,7 @@ description: \|
	msm8998	msm8998
	qcs404	qcs404
	qcm2290	qcm2290
		+ qcm6490
	qdu1000	qdu1000
	qrb2210	qrb2210
	qrb4210	qrb4210
@@ -79,6 +80,7 @@ description: \|
	sm6125	sm6125
	sm6350	sm6350
	sm6375	sm6375
		+ sm7125
	sm7225	sm7225
	sm8150	sm8150
	sm8250	sm8250
@@ -189,6 +191,7 @@ properties:

	- items:	- items:
	- enum:	- enum:
		+ - longcheer,l9100
	- samsung,a7	- samsung,a7
	- sony,kanuti-tulip	- sony,kanuti-tulip
	- square,apq8039-t2	- square,apq8039-t2
@@ -391,6 +394,11 @@ properties:
	- const: qcom,qrb2210	- const: qcom,qrb2210
	- const: qcom,qcm2290	- const: qcom,qcm2290

		+ - items:
		+ - enum:
		+ - fairphone,fp5
		+ - const: qcom,qcm6490
		+
	- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform	- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
	items:	items:
	- enum:	- enum:
@@ -479,6 +487,11 @@ properties:
	- const: google,lazor-rev8	- const: google,lazor-rev8
	- const: qcom,sc7180	- const: qcom,sc7180

		+ - description: Acer Chromebook Spin 513 (rev9)
		+ items:
		+ - const: google,lazor-rev9
		+ - const: qcom,sc7180
		+
	- description: Acer Chromebook Spin 513 (newest rev)	- description: Acer Chromebook Spin 513 (newest rev)
	items:	items:
	- const: google,lazor	- const: google,lazor
@@ -500,6 +513,11 @@ properties:
	- const: google,lazor-rev8-sku2	- const: google,lazor-rev8-sku2
	- const: qcom,sc7180	- const: qcom,sc7180

		+ - description: Acer Chromebook Spin 513 with KB Backlight (rev9)
		+ items:
		+ - const: google,lazor-rev9-sku2
		+ - const: qcom,sc7180
		+
	- description: Acer Chromebook Spin 513 with KB Backlight (newest rev)	- description: Acer Chromebook Spin 513 with KB Backlight (newest rev)
	items:	items:
	- const: google,lazor-sku2	- const: google,lazor-sku2
@@ -521,9 +539,16 @@ properties:
	- const: google,lazor-rev8-sku0	- const: google,lazor-rev8-sku0
	- const: qcom,sc7180	- const: qcom,sc7180

		+ - description: Acer Chromebook Spin 513 with LTE (rev9)
		+ items:
		+ - const: google,lazor-rev9-sku0
		+ - const: google,lazor-rev9-sku10
		+ - const: qcom,sc7180
		+
	- description: Acer Chromebook Spin 513 with LTE (newest rev)	- description: Acer Chromebook Spin 513 with LTE (newest rev)
	items:	items:
	- const: google,lazor-sku0	- const: google,lazor-sku0
		+ - const: google,lazor-sku10
	- const: qcom,sc7180	- const: qcom,sc7180

	- description: Acer Chromebook 511 (rev4 - rev8)	- description: Acer Chromebook 511 (rev4 - rev8)
@@ -535,9 +560,16 @@ properties:
	- const: google,lazor-rev8-sku4	- const: google,lazor-rev8-sku4
	- const: qcom,sc7180	- const: qcom,sc7180

		+ - description: Acer Chromebook 511 (rev9)
		+ items:
		+ - const: google,lazor-rev9-sku4
		+ - const: google,lazor-rev9-sku15
		+ - const: qcom,sc7180
		+
	- description: Acer Chromebook 511 (newest rev)	- description: Acer Chromebook 511 (newest rev)
	items:	items:
	- const: google,lazor-sku4	- const: google,lazor-sku4
		+ - const: google,lazor-sku15
	- const: qcom,sc7180	- const: qcom,sc7180

	- description: Acer Chromebook 511 without Touchscreen (rev4)	- description: Acer Chromebook 511 without Touchscreen (rev4)
@@ -554,9 +586,16 @@ properties:
	- const: google,lazor-rev8-sku6	- const: google,lazor-rev8-sku6
	- const: qcom,sc7180	- const: qcom,sc7180

		+ - description: Acer Chromebook 511 without Touchscreen (rev9)
		+ items:
		+ - const: google,lazor-rev9-sku6
		+ - const: google,lazor-rev9-sku18
		+ - const: qcom,sc7180
		+
	- description: Acer Chromebook 511 without Touchscreen (newest rev)	- description: Acer Chromebook 511 without Touchscreen (newest rev)
	items:	items:
	- const: google,lazor-sku6	- const: google,lazor-sku6
		+ - const: google,lazor-sku18
	- const: qcom,sc7180	- const: qcom,sc7180

	- description: Google Mrbland with AUO panel (rev0)	- description: Google Mrbland with AUO panel (rev0)
@@ -943,6 +982,11 @@ properties:
	- sony,pdx225	- sony,pdx225
	- const: qcom,sm6375	- const: qcom,sm6375

		+ - items:
		+ - enum:
		+ - xiaomi,joyeuse
		+ - const: qcom,sm7125
		+
	- items:	- items:
	- enum:	- enum:
	- fairphone,fp4	- fairphone,fp4
@@ -1086,6 +1130,7 @@ allOf:
	- qcom,sm6115	- qcom,sm6115
	- qcom,sm6125	- qcom,sm6125
	- qcom,sm6350	- qcom,sm6350
		+ - qcom,sm7125
	- qcom,sm7225	- qcom,sm7225
	- qcom,sm8150	- qcom,sm8150
	- qcom,sm8250	- qcom,sm8250

sys/contrib/device-tree/Bindings/arm/rockchip.yaml
@@ -660,6 +660,11 @@ properties:
	- pine64,quartz64-b	- pine64,quartz64-b
	- const: rockchip,rk3566	- const: rockchip,rk3566

		+ - description: Pine64 QuartzPro64
		+ items:
		+ - const: pine64,quartzpro64
		+ - const: rockchip,rk3588
		+
	- description: Pine64 SoQuartz SoM	- description: Pine64 SoQuartz SoM
	items:	items:
	- enum:	- enum:
@@ -669,6 +674,11 @@ properties:
	- const: pine64,soquartz	- const: pine64,soquartz
	- const: rockchip,rk3566	- const: rockchip,rk3566

		+ - description: Powkiddy RGB30
		+ items:
		+ - const: powkiddy,rgb30
		+ - const: rockchip,rk3566
		+
	- description: Radxa Compute Module 3(CM3)	- description: Radxa Compute Module 3(CM3)
	items:	items:
	- enum:	- enum:
@@ -870,6 +880,16 @@ properties:
	- const: tronsmart,orion-r68-meta	- const: tronsmart,orion-r68-meta
	- const: rockchip,rk3368	- const: rockchip,rk3368

		+ - description: Turing RK1
		+ items:
		+ - const: turing,rk1
		+ - const: rockchip,rk3588
		+
		+ - description: Xunlong Orange Pi 5 Plus
		+ items:
		+ - const: xunlong,orangepi-5-plus
		+ - const: rockchip,rk3588
		+
	- description: Xunlong Orange Pi R1 Plus / LTS	- description: Xunlong Orange Pi R1 Plus / LTS
	items:	items:
	- enum:	- enum:
@@ -877,6 +897,11 @@ properties:
	- xunlong,orangepi-r1-plus-lts	- xunlong,orangepi-r1-plus-lts
	- const: rockchip,rk3328	- const: rockchip,rk3328

		+ - description: Xunlong Orange Pi 5
		+ items:
		+ - const: xunlong,orangepi-5
		+ - const: rockchip,rk3588s
		+
	- description: Zkmagic A95X Z2	- description: Zkmagic A95X Z2
	items:	items:
	- const: zkmagic,a95x-z2	- const: zkmagic,a95x-z2

sys/contrib/device-tree/Bindings/arm/sti.yaml
@@ -1,4 +1,4 @@
	-# SPDX-License-Identifier: GPL-2.0	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	%YAML 1.2	%YAML 1.2
	---	---
	$id: http://devicetree.org/schemas/arm/sti.yaml#	$id: http://devicetree.org/schemas/arm/sti.yaml#
@@ -13,13 +13,20 @@ properties:
	$nodename:	$nodename:
	const: '/'	const: '/'
	compatible:	compatible:
	- items:	+ oneOf:
	- - ~~enum:~~	+ - items:
	- - st,~~stih415~~	+ - const: st,stih407-b2120
	- - st,~~stih416~~	+ - const: st,stih407
	- - st,stih407	+ - items:
	- - ~~st,stih410~~	+ - enum:
	- - st,~~stih418~~	+ - st,stih410-b2120
		+ - st,stih410-b2260
		+ - const: st,stih410
		+ - items:
		+ - enum:
		+ - st,stih418-b2199
		+ - st,stih418-b2264
		+ - const: st,stih418

	additionalProperties: true	additionalProperties: true

                - lxa,stm32mp157c-mc1      # Linux Automation MC-1
                - lxa,stm32mp157c-tac-gen1 # Linux Automation TAC (Generation 1)
                - lxa,stm32mp157c-tac-gen2 # Linux Automation TAC (Generation 2)
++              - oct,stm32mp157c-osd32-red # Octavo OSD32MP1 RED board
            - const: oct,stm32mp15xx-osd32
            - enum:
                - st,stm32mp157

sys/contrib/device-tree/Bindings/arm/sunxi.yaml
@@ -51,6 +51,11 @@ properties:
	- const: allwinner,parrot	- const: allwinner,parrot
	- const: allwinner,sun8i-a33	- const: allwinner,sun8i-a33

		+ - description: Anbernic RG-Nano
		+ items:
		+ - const: anbernic,rg-nano
		+ - const: allwinner,sun8i-v3s
		+
	- description: Amarula A64 Relic	- description: Amarula A64 Relic
	items:	items:
	- const: amarula,a64-relic	- const: amarula,a64-relic
@@ -151,6 +156,17 @@ properties:
	- const: roofull,beelink-x2	- const: roofull,beelink-x2
	- const: allwinner,sun8i-h3	- const: allwinner,sun8i-h3

		+ - description: BigTreeTech Manta M4/8P
		+ items:
		+ - const: bigtreetech,cb1-manta
		+ - const: bigtreetech,cb1
		+ - const: allwinner,sun50i-h616
		+
		+ - description: BigTreeTech Pi
		+ items:
		+ - const: bigtreetech,pi
		+ - const: allwinner,sun50i-h616
		+
	- description: Chuwi V7 CW0825	- description: Chuwi V7 CW0825
	items:	items:
	- const: chuwi,v7-cw0825	- const: chuwi,v7-cw0825

          - interconnects
          - power-domains
--additionalProperties: true
++additionalProperties: false
  examples:
    - |

  properties:
    compatible:
      enum:
++      - qcom,qdu1000-llcc
        - qcom,sc7180-llcc
        - qcom,sc7280-llcc
        - qcom,sc8180x-llcc
    interrupts:
      maxItems: 1
++  nvmem-cells:
++    items:
++      - description: Reference to an nvmem node for multi channel DDR
++
++  nvmem-cell-names:
++    items:
++      - const: multi-chan-ddr
++
  required:
    - compatible
    - reg
          compatible:
            contains:
              enum:
++              - qcom,qdu1000-llcc
                - qcom,sc8180x-llcc
                - qcom,sc8280xp-llcc
      then:

sys/contrib/device-tree/Bindings/clock/amlogic,s4-peripherals-clkc.yaml
@@ -0,0 +1,96 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/amlogic,s4-peripherals-clkc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Amlogic S4 Peripherals Clock Controller
			+
			+maintainers:
			+ - Yu Tu <yu.tu@amlogic.com>
			+
			+properties:
			+ compatible:
			+ const: amlogic,s4-peripherals-clkc
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ minItems: 14
			+ items:
			+ - description: input fixed pll div2
			+ - description: input fixed pll div2p5
			+ - description: input fixed pll div3
			+ - description: input fixed pll div4
			+ - description: input fixed pll div5
			+ - description: input fixed pll div7
			+ - description: input hifi pll
			+ - description: input gp0 pll
			+ - description: input mpll0
			+ - description: input mpll1
			+ - description: input mpll2
			+ - description: input mpll3
			+ - description: input hdmi pll
			+ - description: input oscillator (usually at 24MHz)
			+ - description: input external 32kHz reference (optional)
			+
			+ clock-names:
			+ minItems: 14
			+ items:
			+ - const: fclk_div2
			+ - const: fclk_div2p5
			+ - const: fclk_div3
			+ - const: fclk_div4
			+ - const: fclk_div5
			+ - const: fclk_div7
			+ - const: hifi_pll
			+ - const: gp0_pll
			+ - const: mpll0
			+ - const: mpll1
			+ - const: mpll2
			+ - const: mpll3
			+ - const: hdmi_pll
			+ - const: xtal
			+ - const: ext_32k
			+
			+ "#clock-cells":
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - clocks
			+ - clock-names
			+ - "#clock-cells"
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
			+
			+ clkc_periphs: clock-controller@fe000000 {
			+ compatible = "amlogic,s4-peripherals-clkc";
			+ reg = <0xfe000000 0x49c>;
			+ clocks = <&clkc_pll 3>,
			+ <&clkc_pll 13>,
			+ <&clkc_pll 5>,
			+ <&clkc_pll 7>,
			+ <&clkc_pll 9>,
			+ <&clkc_pll 11>,
			+ <&clkc_pll 17>,
			+ <&clkc_pll 15>,
			+ <&clkc_pll 25>,
			+ <&clkc_pll 27>,
			+ <&clkc_pll 29>,
			+ <&clkc_pll 31>,
			+ <&clkc_pll 20>,
			+ <&xtal>;
			+ clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", "fclk_div4",
			+ "fclk_div5", "fclk_div7", "hifi_pll", "gp0_pll",
			+ "mpll0", "mpll1", "mpll2", "mpll3", "hdmi_pll", "xtal";
			+ #clock-cells = <1>;
			+ };
			+...

sys/contrib/device-tree/Bindings/clock/amlogic,s4-pll-clkc.yaml
@@ -0,0 +1,49 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/amlogic,s4-pll-clkc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Amlogic S4 PLL Clock Controller
			+
			+maintainers:
			+ - Yu Tu <yu.tu@amlogic.com>
			+
			+properties:
			+ compatible:
			+ const: amlogic,s4-pll-clkc
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ maxItems: 1
			+
			+ clock-names:
			+ items:
			+ - const: xtal
			+
			+ "#clock-cells":
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - clocks
			+ - clock-names
			+ - "#clock-cells"
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ clkc_pll: clock-controller@fe008000 {
			+ compatible = "amlogic,s4-pll-clkc";
			+ reg = <0xfe008000 0x1e8>;
			+ clocks = <&xtal>;
			+ clock-names = "xtal";
			+ #clock-cells = <1>;
			+ };
			+
			+...

                          "qcom,hfpll-apq8064", "qcom,hfpll"
                          "qcom,hfpll-msm8974", "qcom,hfpll"
                          "qcom,hfpll-msm8960", "qcom,hfpll"
++                        "qcom,msm8976-hfpll-a53", "qcom,hfpll"
++                        "qcom,msm8976-hfpll-a72", "qcom,hfpll"
++                        "qcom,msm8976-hfpll-cci", "qcom,hfpll"
  - reg:
          Usage: required

        - qcom,sdx55-rpmh-clk
        - qcom,sdx65-rpmh-clk
        - qcom,sdx75-rpmh-clk
++      - qcom,sm4450-rpmh-clk
        - qcom,sm6350-rpmh-clk
        - qcom,sm8150-rpmh-clk
        - qcom,sm8250-rpmh-clk

sys/contrib/device-tree/Bindings/clock/qcom,sm4450-gcc.yaml
@@ -0,0 +1,55 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm Global Clock & Reset Controller on SM4450
			+
			+maintainers:
			+ - Ajit Pandey <quic_ajipan@quicinc.com>
			+ - Taniya Das <quic_tdas@quicinc.com>
			+
			+description: \|
			+ Qualcomm global clock control module provides the clocks, resets and power
			+ domains on SM4450
			+
			+ See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h
			+
			+properties:
			+ compatible:
			+ const: qcom,sm4450-gcc
			+
			+ clocks:
			+ items:
			+ - description: Board XO source
			+ - description: Sleep clock source
			+ - description: UFS Phy Rx symbol 0 clock source
			+ - description: UFS Phy Rx symbol 1 clock source
			+ - description: UFS Phy Tx symbol 0 clock source
			+ - description: USB3 Phy wrapper pipe clock source
			+
			+required:
			+ - compatible
			+ - clocks
			+
			+allOf:
			+ - $ref: qcom,gcc.yaml#
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/qcom,rpmh.h>
			+ clock-controller@100000 {
			+ compatible = "qcom,sm4450-gcc";
			+ reg = <0x00100000 0x001f4200>;
			+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
			+ <&ufs_mem_phy 0>, <&ufs_mem_phy 1>,
			+ <&ufs_mem_phy 2>, <&usb_1_qmpphy>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ #power-domain-cells = <1>;
			+ };
			+
			+...

sys/contrib/device-tree/Bindings/clock/qcom,sm8450-camcc.yaml
@@ -13,11 +13,15 @@ description: \|
	Qualcomm camera clock control module provides the clocks, resets and power	Qualcomm camera clock control module provides the clocks, resets and power
	domains on SM8450.	domains on SM8450.

	- See also:: ~~include/dt-bindings/clock/qcom,sm8450-camcc.h~~	+ See also::
		+ include/dt-bindings/clock/qcom,sm8450-camcc.h
		+ include/dt-bindings/clock/qcom,sm8550-camcc.h

	properties:	properties:
	compatible:	compatible:
	- const: qcom,sm8450-camcc	+ enum:
		+ - qcom,sm8450-camcc
		+ - qcom,sm8550-camcc

	clocks:	clocks:
	items:	items:

        - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
        - renesas,r9a07g044-cpg # RZ/G2{L,LC}
        - renesas,r9a07g054-cpg # RZ/V2L
++      - renesas,r9a08g045-cpg # RZ/G3S
        - renesas,r9a09g011-cpg # RZ/V2M
    reg:

            - enum:
                - qcom,qcm2290-cpufreq-hw
                - qcom,sc7180-cpufreq-hw
++              - qcom,sdm670-cpufreq-hw
                - qcom,sdm845-cpufreq-hw
                - qcom,sm6115-cpufreq-hw
                - qcom,sm6350-cpufreq-hw
                - qcom,sa8775p-cpufreq-epss
                - qcom,sc7280-cpufreq-epss
                - qcom,sc8280xp-cpufreq-epss
++              - qcom,sdx75-cpufreq-epss
                - qcom,sm6375-cpufreq-epss
                - qcom,sm8250-cpufreq-epss
                - qcom,sm8350-cpufreq-epss
                - qcom,sm8450-cpufreq-epss
                - qcom,sm8550-cpufreq-epss
++              - qcom,sm8650-cpufreq-epss
            - const: qcom,cpufreq-epss
    reg:
                - qcom,qdu1000-cpufreq-epss
                - qcom,sc7180-cpufreq-hw
                - qcom,sc8280xp-cpufreq-epss
++              - qcom,sdm670-cpufreq-hw
                - qcom,sdm845-cpufreq-hw
                - qcom,sm6115-cpufreq-hw
                - qcom,sm6350-cpufreq-hw

          enum:
            - qcom,apq8064
            - qcom,apq8096
++          - qcom,ipq5332
++          - qcom,ipq6018
            - qcom,ipq8064
            - qcom,ipq8074
++          - qcom,ipq9574
++          - qcom,msm8909
            - qcom,msm8939
            - qcom,msm8960
            - qcom,msm8974
        - if:
            properties:
              compatible:
--              const: operating-points-v2-kryo-cpu
++              enum:
++                - operating-points-v2-krait-cpu
++                - operating-points-v2-kryo-cpu
          then:
            $ref: /schemas/opp/opp-v2-kryo-cpu.yaml#

sys/contrib/device-tree/Bindings/crypto/fsl-imx-sahara.yaml
@@ -4,7 +4,7 @@
	$id: http://devicetree.org/schemas/crypto/fsl-imx-sahara.yaml#	$id: http://devicetree.org/schemas/crypto/fsl-imx-sahara.yaml#
	$schema: http://devicetree.org/meta-schemas/core.yaml#	$schema: http://devicetree.org/meta-schemas/core.yaml#

	-title: Freescale SAHARA Cryptographic Accelerator ~~included in some i.MX chips~~	+title: Freescale SAHARA Cryptographic Accelerator

	maintainers:	maintainers:
	- Steffen Trumtrar <s.trumtrar@pengutronix.de>	- Steffen Trumtrar <s.trumtrar@pengutronix.de>
@@ -19,19 +19,56 @@ properties:
	maxItems: 1	maxItems: 1

	interrupts:	interrupts:
	- ~~maxItems: 1~~	+ items:
		+ - description: SAHARA Interrupt for Host 0
		+ - description: SAHARA Interrupt for Host 1
		+ minItems: 1
		+
		+ clocks:
		+ items:
		+ - description: Sahara IPG clock
		+ - description: Sahara AHB clock
		+
		+ clock-names:
		+ items:
		+ - const: ipg
		+ - const: ahb

	required:	required:
	- compatible	- compatible
	- reg	- reg
	- interrupts	- interrupts
		+ - clocks
		+ - clock-names
		+
		+allOf:
		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ enum:
		+ - fsl,imx53-sahara
		+ then:
		+ properties:
		+ interrupts:
		+ minItems: 2
		+ maxItems: 2
		+ else:
		+ properties:
		+ interrupts:
		+ maxItems: 1

	additionalProperties: false	additionalProperties: false

	examples:	examples:
	- \|	- \|
		+ #include <dt-bindings/clock/imx27-clock.h>
		+
	crypto@10025000 {	crypto@10025000 {
	compatible = "fsl,imx27-sahara";	compatible = "fsl,imx27-sahara";
	- reg = < ~~0x10025000~~ 0x800>;	+ reg = <0x10025000 0x800>;
	interrupts = <75>;	interrupts = <75>;
		+ clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
		+ <&clks IMX27_CLK_SAHARA_AHB_GATE>;
		+ clock-names = "ipg", "ahb";
	};	};

    compatible:
      items:
        - enum:
++          - qcom,sa8775p-inline-crypto-engine
            - qcom,sm8450-inline-crypto-engine
            - qcom,sm8550-inline-crypto-engine
        - const: qcom,inline-crypto-engine

sys/contrib/device-tree/Bindings/crypto/qcom,prng.yaml
@@ -11,9 +11,17 @@ maintainers:

	properties:	properties:
	compatible:	compatible:
	- ~~enum:~~	+ oneOf:
	- - qcom,prng # 8916 etc.	+ - enum:
	- - qcom,prng~~-ee~~ # ~~8996~~ ~~and later using EE~~	+ - qcom,prng # 8916 etc.
		+ - qcom,prng-ee # 8996 and later using EE
		+ - items:
		+ - enum:
		+ - qcom,sa8775p-trng
		+ - qcom,sc7280-trng
		+ - qcom,sm8450-trng
		+ - qcom,sm8550-trng
		+ - const: qcom,trng

	reg:	reg:
	maxItems: 1	maxItems: 1
@@ -28,8 +36,18 @@ properties:
	required:	required:
	- compatible	- compatible
	- reg	- reg
	- - clocks	+
	- - clock-names	+allOf:
		+ - if:
		+ not:
		+ properties:
		+ compatible:
		+ contains:
		+ const: qcom,trng
		+ then:
		+ required:
		+ - clocks
		+ - clock-names

	additionalProperties: false	additionalProperties: false

sys/contrib/device-tree/Bindings/devfreq/event/rockchip,dfi.yaml
@@ -0,0 +1,74 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/devfreq/event/rockchip,dfi.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Rockchip DFI
			+
			+maintainers:
			+ - Sascha Hauer <s.hauer@pengutronix.de>
			+
			+properties:
			+ compatible:
			+ enum:
			+ - rockchip,rk3399-dfi
			+ - rockchip,rk3568-dfi
			+ - rockchip,rk3588-dfi
			+
			+ clocks:
			+ maxItems: 1
			+
			+ clock-names:
			+ items:
			+ - const: pclk_ddr_mon
			+
			+ interrupts:
			+ minItems: 1
			+ maxItems: 4
			+
			+ reg:
			+ maxItems: 1
			+
			+ rockchip,pmu:
			+ $ref: /schemas/types.yaml#/definitions/phandle
			+ description:
			+ Phandle to the syscon managing the "PMU general register files".
			+
			+required:
			+ - compatible
			+ - interrupts
			+ - reg
			+
			+if:
			+ properties:
			+ compatible:
			+ contains:
			+ enum:
			+ - rockchip,rk3399-dfi
			+
			+then:
			+ required:
			+ - clocks
			+ - clock-names
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/interrupt-controller/arm-gic.h>
			+ #include <dt-bindings/clock/rk3308-cru.h>
			+
			+ bus {
			+ #address-cells = <2>;
			+ #size-cells = <2>;
			+
			+ dfi: dfi@ff630000 {
			+ compatible = "rockchip,rk3399-dfi";
			+ reg = <0x00 0xff630000 0x00 0x4000>;
			+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
			+ rockchip,pmu = <&pmugrf>;
			+ clocks = <&cru PCLK_DDR_MON>;
			+ clock-names = "pclk_ddr_mon";
			+ };
			+ };

  maintainers:
    - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
++allOf:
++  - $ref: /schemas/sound/dai-common.yaml#
++
  description: |
    The ADV7533 and ADV7535 are HDMI audio and video transmitters
    compatible with HDMI 1.4 and DVI 1.0. They support color space
      $ref: /schemas/types.yaml#/definitions/uint32
      enum: [ 1, 2, 3, 4 ]
++  "#sound-dai-cells":
++    const: 0
++
    ports:
      description:
        The ADV7533/35 has two video ports and one audio port.

        - analogix,anx7808
        - analogix,anx7812
        - analogix,anx7814
++      - analogix,anx7816
        - analogix,anx7818
    reg:

sys/contrib/device-tree/Bindings/display/bridge/fsl,imx93-mipi-dsi.yaml
@@ -0,0 +1,115 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/display/bridge/fsl,imx93-mipi-dsi.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Freescale i.MX93 specific extensions to Synopsys Designware MIPI DSI
			+
			+maintainers:
			+ - Liu Ying <victor.liu@nxp.com>
			+
			+description: \|
			+ There is a Synopsys Designware MIPI DSI Host Controller and a Synopsys
			+ Designware MIPI DPHY embedded in Freescale i.MX93 SoC. Some configurations
			+ and extensions to them are controlled by i.MX93 media blk-ctrl.
			+
			+allOf:
			+ - $ref: snps,dw-mipi-dsi.yaml#
			+
			+properties:
			+ compatible:
			+ const: fsl,imx93-mipi-dsi
			+
			+ clocks:
			+ items:
			+ - description: apb clock
			+ - description: pixel clock
			+ - description: PHY configuration clock
			+ - description: PHY reference clock
			+
			+ clock-names:
			+ items:
			+ - const: pclk
			+ - const: pix
			+ - const: phy_cfg
			+ - const: phy_ref
			+
			+ interrupts:
			+ maxItems: 1
			+
			+ fsl,media-blk-ctrl:
			+ $ref: /schemas/types.yaml#/definitions/phandle
			+ description:
			+ i.MX93 media blk-ctrl, as a syscon, controls pixel component bit map
			+ configurations from LCDIF display controller to the MIPI DSI host
			+ controller and MIPI DPHY PLL related configurations through PLL SoC
			+ interface.
			+
			+ power-domains:
			+ maxItems: 1
			+
			+required:
			+ - compatible
			+ - interrupts
			+ - fsl,media-blk-ctrl
			+ - power-domains
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/imx93-clock.h>
			+ #include <dt-bindings/gpio/gpio.h>
			+ #include <dt-bindings/interrupt-controller/arm-gic.h>
			+ #include <dt-bindings/power/fsl,imx93-power.h>
			+
			+ dsi@4ae10000 {
			+ compatible = "fsl,imx93-mipi-dsi";
			+ reg = <0x4ae10000 0x10000>;
			+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
			+ clocks = <&clk IMX93_CLK_MIPI_DSI_GATE>,
			+ <&clk IMX93_CLK_MEDIA_DISP_PIX>,
			+ <&clk IMX93_CLK_MIPI_PHY_CFG>,
			+ <&clk IMX93_CLK_24M>;
			+ clock-names = "pclk", "pix", "phy_cfg", "phy_ref";
			+ fsl,media-blk-ctrl = <&media_blk_ctrl>;
			+ power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>;
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ panel@0 {
			+ compatible = "raydium,rm67191";
			+ reg = <0>;
			+ reset-gpios = <&adp5585gpio 6 GPIO_ACTIVE_LOW>;
			+ dsi-lanes = <4>;
			+ video-mode = <2>;
			+
			+ port {
			+ panel_in: endpoint {
			+ remote-endpoint = <&dsi_out>;
			+ };
			+ };
			+ };
			+
			+ ports {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ port@0 {
			+ reg = <0>;
			+
			+ dsi_to_lcdif: endpoint {
			+ remote-endpoint = <&lcdif_to_dsi>;
			+ };
			+ };
			+
			+ port@1 {
			+ reg = <1>;
			+
			+ dsi_out: endpoint {
			+ remote-endpoint = <&panel_in>;
			+ };
			+ };
			+ };
			+ };

sys/contrib/device-tree/Bindings/display/fsl,lcdif.yaml
@@ -51,7 +51,10 @@ properties:
	minItems: 1	minItems: 1

	interrupts:	interrupts:
	- ~~maxItems: 1~~	+ items:
		+ - description: LCDIF DMA interrupt
		+ - description: LCDIF Error interrupt
		+ minItems: 1

	power-domains:	power-domains:
	maxItems: 1	maxItems: 1
@@ -131,6 +134,21 @@ allOf:
	then:	then:
	required:	required:
	- power-domains	- power-domains
		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ enum:
		+ - fsl,imx23-lcdif
		+ then:
		+ properties:
		+ interrupts:
		+ minItems: 2
		+ maxItems: 2
		+ else:
		+ properties:
		+ interrupts:
		+ maxItems: 1

	examples:	examples:
	- \|	- \|

sys/contrib/device-tree/Bindings/display/ilitek,ili9486.yaml
@@ -50,10 +50,6 @@ examples:
	- \|	- \|
	#include <dt-bindings/gpio/gpio.h>	#include <dt-bindings/gpio/gpio.h>

	- backlight: backlight {
	- compatible = "gpio-backlight";
	- gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
	- };
	spi {	spi {
	#address-cells = <1>;	#address-cells = <1>;
	#size-cells = <0>;	#size-cells = <0>;

sys/contrib/device-tree/Bindings/display/lvds-data-mapping.yaml
@@ -0,0 +1,84 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/display/lvds-data-mapping.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: LVDS Data Mapping
			+
			+maintainers:
			+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
			+ - Thierry Reding <thierry.reding@gmail.com>
			+
			+description: \|
			+ LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
			+ incompatible data link layers have been used over time to transmit image data
			+ to LVDS devices. This bindings supports devices compatible with the following
			+ specifications.
			+
			+ [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
			+ 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
			+ [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
			+ Semiconductor
			+ [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
			+ Electronics Standards Association (VESA)
			+
			+ Device compatible with those specifications have been marketed under the
			+ FPD-Link and FlatLink brands.
			+
			+properties:
			+ data-mapping:
			+ enum:
			+ - jeida-18
			+ - jeida-24
			+ - vesa-24
			+ description: \|
			+ The color signals mapping order.
			+
			+ LVDS data mappings are defined as follows.
			+
			+ - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
			+ [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
			+
			+ Slot 0 1 2 3 4 5 6
			+ ________________ _________________
			+ Clock \_______________________/
			+ ______ ______ ______ ______ ______ ______ ______
			+ DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
			+ DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
			+ DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
			+
			+ - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
			+ specifications. Data are transferred as follows on 4 LVDS lanes.
			+
			+ Slot 0 1 2 3 4 5 6
			+ ________________ _________________
			+ Clock \_______________________/
			+ ______ ______ ______ ______ ______ ______ ______
			+ DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
			+ DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
			+ DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
			+ DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
			+
			+ - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
			+ Data are transferred as follows on 4 LVDS lanes.
			+
			+ Slot 0 1 2 3 4 5 6
			+ ________________ _________________
			+ Clock \_______________________/
			+ ______ ______ ______ ______ ______ ______ ______
			+ DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
			+ DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
			+ DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
			+ DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
			+
			+ Control signals are mapped as follows.
			+
			+ CTL0: HSync
			+ CTL1: VSync
			+ CTL2: Data Enable
			+ CTL3: 0
			+
			+additionalProperties: true
			+
			+...

sys/contrib/device-tree/Bindings/display/lvds.yaml
@@ -6,83 +6,24 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#

	title: LVDS Display Common Properties	title: LVDS Display Common Properties

		+allOf:
		+ - $ref: lvds-data-mapping.yaml#
		+
	maintainers:	maintainers:
	- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>	- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
	- Thierry Reding <thierry.reding@gmail.com>	- Thierry Reding <thierry.reding@gmail.com>

	-description: \|+	+description:
	- LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple	+ This binding extends the data mapping defined in lvds-data-mapping.yaml.
	- incompatible data link layers have been used over time to transmit image data	+ It supports reversing the bit order on the formats defined there in order
	- to LVDS devices. This bindings supports devices compatible with the following	+ to accomodate for even more specialized data formats, since a variety of
	- specifications.	+ data formats and layouts is used to drive LVDS displays.
	-
	- [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
	- 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
	- [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
	- Semiconductor
	- [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
	- Electronics Standards Association (VESA)
	-
	- Device compatible with those specifications have been marketed under the
	- FPD-Link and FlatLink brands.

	properties:	properties:
	- data-mapping:
	- enum:
	- - jeida-18
	- - jeida-24
	- - vesa-24
	- description: \|
	- The color signals mapping order.
	-
	- LVDS data mappings are defined as follows.
	-
	- - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
	- [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
	-
	- Slot 0 1 2 3 4 5 6
	- ________________ _________________
	- Clock \_______________________/
	- ______ ______ ______ ______ ______ ______ ______
	- DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
	- DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
	- DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
	-
	- - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
	- specifications. Data are transferred as follows on 4 LVDS lanes.
	-
	- Slot 0 1 2 3 4 5 6
	- ________________ _________________
	- Clock \_______________________/
	- ______ ______ ______ ______ ______ ______ ______
	- DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
	- DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
	- DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
	- DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
	-
	- - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
	- Data are transferred as follows on 4 LVDS lanes.
	-
	- Slot 0 1 2 3 4 5 6
	- ________________ _________________
	- Clock \_______________________/
	- ______ ______ ______ ______ ______ ______ ______
	- DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
	- DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
	- DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
	- DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
	-
	- Control signals are mapped as follows.
	-
	- CTL0: HSync
	- CTL1: VSync
	- CTL2: Data Enable
	- CTL3: 0
	-
	data-mirror:	data-mirror:
	type: boolean	type: boolean
	description:	description:
	- If set, reverse the bit order described in the data mappings ~~below~~ on all	+ If set, reverse the bit order described in the data mappings on all
	data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.	data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.

	additionalProperties: true	additionalProperties: true

  properties:
    compatible:
      enum:
++      - mediatek,mt8188-dp-tx
++      - mediatek,mt8188-edp-tx
        - mediatek,mt8195-dp-tx
        - mediatek,mt8195-edp-tx

    - Chun-Kuang Hu <chunkuang.hu@kernel.org>
    - Philipp Zabel <p.zabel@pengutronix.de>
    - Jitao Shi <jitao.shi@mediatek.com>
--  - Xinlei Lee <xinlei.lee@mediatek.com>
  description: |
    The MediaTek DSI function block is a sink of the display subsystem and can
            - mediatek,mt8173-dsi
            - mediatek,mt8183-dsi
            - mediatek,mt8186-dsi
++          - mediatek,mt8188-dsi
        - items:
            - enum:
                - mediatek,mt6795-dsi

        port@1:
          $ref: /schemas/graph.yaml#/$defs/port-base
++        unevaluatedProperties: false
          description: Output endpoint of the controller
          properties:
            endpoint:

sys/contrib/device-tree/Bindings/display/msm/gmu.yaml
@@ -21,7 +21,7 @@ properties:
	compatible:	compatible:
	oneOf:	oneOf:
	- items:	- items:
	- - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'	+ - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
	- const: qcom,adreno-gmu	- const: qcom,adreno-gmu
	- const: qcom,adreno-gmu-wrapper	- const: qcom,adreno-gmu-wrapper

@@ -64,6 +64,10 @@ properties:
	iommus:	iommus:
	maxItems: 1	maxItems: 1

		+ qcom,qmp:
		+ $ref: /schemas/types.yaml#/definitions/phandle
		+ description: Reference to the AOSS side-channel message RAM
		+
	operating-points-v2: true	operating-points-v2: true

	opp-table:	opp-table:
@@ -213,6 +217,47 @@ allOf:
	- const: axi	- const: axi
	- const: memnoc	- const: memnoc

		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ enum:
		+ - qcom,adreno-gmu-730.1
		+ - qcom,adreno-gmu-740.1
		+ then:
		+ properties:
		+ reg:
		+ items:
		+ - description: Core GMU registers
		+ - description: Resource controller registers
		+ - description: GMU PDC registers
		+ reg-names:
		+ items:
		+ - const: gmu
		+ - const: rscc
		+ - const: gmu_pdc
		+ clocks:
		+ items:
		+ - description: GPU AHB clock
		+ - description: GMU clock
		+ - description: GPU CX clock
		+ - description: GPU AXI clock
		+ - description: GPU MEMNOC clock
		+ - description: GMU HUB clock
		+ - description: GPUSS DEMET clock
		+ clock-names:
		+ items:
		+ - const: ahb
		+ - const: gmu
		+ - const: cxo
		+ - const: axi
		+ - const: memnoc
		+ - const: hub
		+ - const: demet
		+
		+ required:
		+ - qcom,qmp
		+
	- if:	- if:
	properties:	properties:
	compatible:	compatible:

            The driver is parsing the compat string for Adreno to
            figure out the gpu-id and patch level.
          items:
--          - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
++          - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]$'
            - const: qcom,adreno
        - description: |
            The driver is parsing the compat string for Imageon to
          properties:
            compatible:
              contains:
--              pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
++              pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]$'
        then: # Starting with A6xx, the clocks are usually defined in the GMU node
          properties:

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,msm8998-dpu
    "^dsi@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          items:
    "^phy@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,dsi-phy-10nm-8998

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,qcm2290-dpu
    "^dsi@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,dsi-ctrl-6g-qcm2290
    "^phy@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,dsi-phy-14nm-2290

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sc7180-dpu
    "^displayport-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sc7180-dp
    "^dsi@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          items:
    "^phy@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,dsi-phy-10nm

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sc7280-dpu
    "^displayport-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sc7280-dp
    "^dsi@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          items:
    "^edp@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sc7280-edp
    "^phy@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          enum:

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sc8280xp-dpu
    "^displayport-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          enum:

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sdm845-dpu
    "^displayport-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sdm845-dp
    "^dsi@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          items:
    "^phy@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,dsi-phy-10nm

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm6115-dpu
    "^dsi@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          oneOf:
    "^phy@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,dsi-phy-14nm-2290

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm6125-dpu
    "^dsi@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          items:
    "^phy@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm6125-dsi-phy-14nm

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm6350-dpu
    "^dsi@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          items:
    "^phy@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,dsi-phy-10nm

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm6375-dpu
    "^dsi@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          items:
    "^phy@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm6375-dsi-phy-7nm

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm8150-dpu
    "^dsi@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          items:
    "^phy@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,dsi-phy-7nm

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm8250-dpu
    "^dsi@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          items:
    "^phy@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,dsi-phy-7nm

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm8350-dpu
    "^displayport-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm8350-dp
    "^dsi@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          items:
    "^phy@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm8350-dsi-phy-5nm

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm8450-dpu
    "^displayport-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          items:
    "^dsi@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          items:
    "^phy@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm8450-dsi-phy-5nm

  patternProperties:
    "^display-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm8550-dpu
    "^displayport-controller@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          items:
    "^dsi@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          items:
    "^phy@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          const: qcom,sm8550-dsi-phy-4nm

sys/contrib/device-tree/Bindings/display/panel/ilitek,ili9163.yaml
@@ -48,10 +48,6 @@ examples:
	- \|	- \|
	#include <dt-bindings/gpio/gpio.h>	#include <dt-bindings/gpio/gpio.h>

	- backlight: backlight {
	- compatible = "gpio-backlight";
	- gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
	- };
	spi {	spi {
	#address-cells = <1>;	#address-cells = <1>;
	#size-cells = <0>;	#size-cells = <0>;

sys/contrib/device-tree/Bindings/display/panel/jdi,lpm102a188a.yaml
@@ -0,0 +1,94 @@
			+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/display/panel/jdi,lpm102a188a.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: JDI LPM102A188A 2560x1800 10.2" DSI Panel
			+
			+maintainers:
			+ - Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
			+
			+description: \|
			+ This panel requires a dual-channel DSI host to operate. It supports two modes:
			+ - left-right: each channel drives the left or right half of the screen
			+ - even-odd: each channel drives the even or odd lines of the screen
			+
			+ Each of the DSI channels controls a separate DSI peripheral. The peripheral
			+ driven by the first link (DSI-LINK1) is considered the primary peripheral
			+ and controls the device. The 'link2' property contains a phandle to the
			+ peripheral driven by the second link (DSI-LINK2).
			+
			+allOf:
			+ - $ref: panel-common.yaml#
			+
			+properties:
			+ compatible:
			+ const: jdi,lpm102a188a
			+
			+ reg: true
			+ enable-gpios: true
			+ reset-gpios: true
			+ power-supply: true
			+ backlight: true
			+
			+ ddi-supply:
			+ description: The regulator that provides IOVCC (1.8V).
			+
			+ link2:
			+ $ref: /schemas/types.yaml#/definitions/phandle
			+ description: \|
			+ phandle to the DSI peripheral on the secondary link. Note that the
			+ presence of this property marks the containing node as DSI-LINK1.
			+
			+required:
			+ - compatible
			+ - reg
			+
			+if:
			+ required:
			+ - link2
			+then:
			+ required:
			+ - power-supply
			+ - ddi-supply
			+ - enable-gpios
			+ - reset-gpios
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/gpio/gpio.h>
			+ #include <dt-bindings/gpio/tegra-gpio.h>
			+
			+ dsia: dsi@54300000 {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+ reg = <0x0 0x54300000 0x0 0x00040000>;
			+
			+ link2: panel@0 {
			+ compatible = "jdi,lpm102a188a";
			+ reg = <0>;
			+ };
			+ };
			+
			+ dsib: dsi@54400000{
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+ reg = <0x0 0x54400000 0x0 0x00040000>;
			+ nvidia,ganged-mode = <&dsia>;
			+
			+ link1: panel@0 {
			+ compatible = "jdi,lpm102a188a";
			+ reg = <0>;
			+ power-supply = <&pplcd_vdd>;
			+ ddi-supply = <&pp1800_lcdio>;
			+ enable-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
			+ reset-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
			+ link2 = <&link2>;
			+ backlight = <&backlight>;
			+ };
			+ };
			+
			+...

      enum:
        - leadtek,ltk050h3146w
        - leadtek,ltk050h3146w-a2
++      - leadtek,ltk050h3148w
    reg: true
    backlight: true
    reset-gpios: true

  title: NewVision NV3051D based LCD panel
  description: |
--  The NewVision NV3051D is a driver chip used to drive DSI panels. For now,
++  The NewVision NV3051D is a driver chip used to drive DSI panels.
--  this driver only supports the 640x480 panels found in the Anbernic RG353
--  based devices.
  maintainers:
    - Chris Morgan <macromorgan@hotmail.com>
    compatible:
      items:
        - enum:
++          - anbernic,rg351v-panel
            - anbernic,rg353p-panel
            - anbernic,rg353v-panel
        - const: newvision,nv3051d

        - lg,acx467akm-7
          # LG Corporation 7" WXGA TFT LCD panel
        - lg,ld070wx3-sl01
++        # LG Corporation 5" HD TFT LCD panel
++      - lg,lh500wx1-sd03
          # One Stop Displays OSD101T2587-53TS 10.1" 1920x1200 panel
        - osddisplays,osd101t2587-53ts
          # Panasonic 10" WUXGA TFT LCD panel

sys/contrib/device-tree/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml
@@ -0,0 +1,118 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/display/panel/panel-simple-lvds-dual-ports.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Simple LVDS panels with one power supply and dual LVDS ports
			+
			+maintainers:
			+ - Liu Ying <victor.liu@nxp.com>
			+ - Thierry Reding <thierry.reding@gmail.com>
			+ - Sam Ravnborg <sam@ravnborg.org>
			+
			+description: \|
			+ This binding file is a collection of the LVDS panels that
			+ has dual LVDS ports and requires only a single power-supply.
			+ The first port receives odd pixels, and the second port receives even pixels.
			+ There are optionally a backlight and an enable GPIO.
			+ The panel may use an OF graph binding for the association to the display,
			+ or it may be a direct child node of the display.
			+
			+ If the panel is more advanced a dedicated binding file is required.
			+
			+allOf:
			+ - $ref: panel-common.yaml#
			+
			+properties:
			+
			+ compatible:
			+ enum:
			+ # compatible must be listed in alphabetical order, ordered by compatible.
			+ # The description in the comment is mandatory for each compatible.
			+
			+ # AU Optronics Corporation 13.3" FHD (1920x1080) TFT LCD panel
			+ - auo,g133han01
			+ # AU Optronics Corporation 18.5" FHD (1920x1080) TFT LCD panel
			+ - auo,g185han01
			+ # AU Optronics Corporation 19.0" (1280x1024) TFT LCD panel
			+ - auo,g190ean01
			+ # Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel
			+ - koe,tx26d202vm0bwa
			+ # NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel
			+ - nlt,nl192108ac18-02d
			+
			+ ports:
			+ $ref: /schemas/graph.yaml#/properties/ports
			+
			+ properties:
			+ port@0:
			+ $ref: /schemas/graph.yaml#/$defs/port-base
			+ unevaluatedProperties: false
			+ description: The first sink port.
			+
			+ properties:
			+ dual-lvds-odd-pixels:
			+ type: boolean
			+ description: The first sink port for odd pixels.
			+
			+ required:
			+ - dual-lvds-odd-pixels
			+
			+ port@1:
			+ $ref: /schemas/graph.yaml#/$defs/port-base
			+ unevaluatedProperties: false
			+ description: The second sink port.
			+
			+ properties:
			+ dual-lvds-even-pixels:
			+ type: boolean
			+ description: The second sink port for even pixels.
			+
			+ required:
			+ - dual-lvds-even-pixels
			+
			+ required:
			+ - port@0
			+ - port@1
			+
			+ backlight: true
			+ enable-gpios: true
			+ power-supply: true
			+
			+additionalProperties: false
			+
			+required:
			+ - compatible
			+ - ports
			+ - power-supply
			+
			+examples:
			+ - \|
			+ panel: panel-lvds {
			+ compatible = "koe,tx26d202vm0bwa";
			+ power-supply = <&vdd_lcd_reg>;
			+
			+ ports {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ port@0 {
			+ dual-lvds-odd-pixels;
			+ reg = <0>;
			+
			+ panel_lvds0_in: endpoint {
			+ remote-endpoint = <&lvds0_out>;
			+ };
			+ };
			+
			+ port@1 {
			+ dual-lvds-even-pixels;
			+ reg = <1>;
			+
			+ panel_lvds1_in: endpoint {
			+ remote-endpoint = <&lvds1_out>;
			+ };
			+ };
			+ };
			+ };

sys/contrib/device-tree/Bindings/display/panel/panel-simple.yaml
@@ -21,9 +21,9 @@ description: \|

	allOf:	allOf:
	- $ref: panel-common.yaml#	- $ref: panel-common.yaml#
		+ - $ref: ../lvds-data-mapping.yaml#

	properties:	properties:
	-
	compatible:	compatible:
	enum:	enum:
	# compatible must be listed in alphabetical order, ordered by compatible.	# compatible must be listed in alphabetical order, ordered by compatible.
@@ -65,14 +65,8 @@ properties:
	- auo,g104sn02	- auo,g104sn02
	# AU Optronics Corporation 12.1" (1280x800) TFT LCD panel	# AU Optronics Corporation 12.1" (1280x800) TFT LCD panel
	- auo,g121ean01	- auo,g121ean01
	- # AU Optronics Corporation 13.3" FHD (1920x1080) TFT LCD panel
	- - auo,g133han01
	# AU Optronics Corporation 15.6" (1366x768) TFT LCD panel	# AU Optronics Corporation 15.6" (1366x768) TFT LCD panel
	- auo,g156xtn01	- auo,g156xtn01
	- # AU Optronics Corporation 18.5" FHD (1920x1080) TFT LCD panel
	- - auo,g185han01
	- # AU Optronics Corporation 19.0" (1280x1024) TFT LCD panel
	- - auo,g190ean01
	# AU Optronics Corporation 31.5" FHD (1920x1080) TFT LCD panel	# AU Optronics Corporation 31.5" FHD (1920x1080) TFT LCD panel
	- auo,p320hvn03	- auo,p320hvn03
	# AU Optronics Corporation 21.5" FHD (1920x1080) color TFT LCD panel	# AU Optronics Corporation 21.5" FHD (1920x1080) color TFT LCD panel
@@ -204,8 +198,6 @@ properties:
	- kingdisplay,kd116n21-30nv-a010	- kingdisplay,kd116n21-30nv-a010
	# Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel	# Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel
	- koe,tx14d24vm1bpa	- koe,tx14d24vm1bpa
	- # Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel
	- - koe,tx26d202vm0bwa
	# Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel	# Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel
	- koe,tx31d200vm0baa	- koe,tx31d200vm0baa
	# Kyocera Corporation 7" WVGA (800x480) transmissive color TFT	# Kyocera Corporation 7" WVGA (800x480) transmissive color TFT
@@ -216,8 +208,6 @@ properties:
	- lemaker,bl035-rgb-002	- lemaker,bl035-rgb-002
	# LG 7" (800x480 pixels) TFT LCD panel	# LG 7" (800x480 pixels) TFT LCD panel
	- lg,lb070wv8	- lg,lb070wv8
	- # LG Corporation 5" HD TFT LCD panel
	- - lg,lh500wx1-sd03
	# LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel	# LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel
	- lg,lp079qx1-sp0v	- lg,lp079qx1-sp0v
	# LG 9.7" (2048x1536 pixels) TFT LCD panel	# LG 9.7" (2048x1536 pixels) TFT LCD panel
@@ -238,6 +228,8 @@ properties:
	- logictechno,lttd800480070-l6wh-rt	- logictechno,lttd800480070-l6wh-rt
	# Mitsubishi "AA070MC01 7.0" WVGA TFT LCD panel	# Mitsubishi "AA070MC01 7.0" WVGA TFT LCD panel
	- mitsubishi,aa070mc01-ca1	- mitsubishi,aa070mc01-ca1
		+ # Mitsubishi AA084XE01 8.4" XGA TFT LCD panel
		+ - mitsubishi,aa084xe01
	# Multi-Inno Technology Co.,Ltd MI0700S4T-6 7" 800x480 TFT Resistive Touch Module	# Multi-Inno Technology Co.,Ltd MI0700S4T-6 7" 800x480 TFT Resistive Touch Module
	- multi-inno,mi0700s4t-6	- multi-inno,mi0700s4t-6
	# Multi-Inno Technology Co.,Ltd MI0800FT-9 8" 800x600 TFT Resistive Touch Module	# Multi-Inno Technology Co.,Ltd MI0800FT-9 8" 800x600 TFT Resistive Touch Module
@@ -254,8 +246,6 @@ properties:
	- neweast,wjfh116008a	- neweast,wjfh116008a
	# Newhaven Display International 480 x 272 TFT LCD panel	# Newhaven Display International 480 x 272 TFT LCD panel
	- newhaven,nhd-4.3-480272ef-atxl	- newhaven,nhd-4.3-480272ef-atxl
	- # NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel
	- - nlt,nl192108ac18-02d
	# New Vision Display 7.0" 800 RGB x 480 TFT LCD panel	# New Vision Display 7.0" 800 RGB x 480 TFT LCD panel
	- nvd,9128	- nvd,9128
	# OKAYA Electric America, Inc. RS800480T-7X0GP 7" WVGA LCD panel	# OKAYA Electric America, Inc. RS800480T-7X0GP 7" WVGA LCD panel
@@ -357,6 +347,17 @@ properties:
	power-supply: true	power-supply: true
	no-hpd: true	no-hpd: true
	hpd-gpios: true	hpd-gpios: true
		+ data-mapping: true
		+
		+if:
		+ not:
		+ properties:
		+ compatible:
		+ contains:
		+ const: innolux,g101ice-l01
		+then:
		+ properties:
		+ data-mapping: false

	additionalProperties: false	additionalProperties: false

@@ -376,3 +377,16 @@ examples:
	};	};
	};	};
	};	};
		+ - \|
		+ panel_lvds: panel-lvds {
		+ compatible = "innolux,g101ice-l01";
		+ power-supply = <&vcc_lcd_reg>;
		+
		+ data-mapping = "jeida-24";
		+
		+ port {
		+ panel_in_lvds: endpoint {
		+ remote-endpoint = <&ltdc_out_lvds>;
		+ };
		+ };
		+ };

sys/contrib/device-tree/Bindings/display/panel/raydium,rm692e5.yaml
@@ -0,0 +1,73 @@
			+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/display/panel/raydium,rm692e5.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Raydium RM692E5 based DSI display panels
			+
			+maintainers:
			+ - Konrad Dybcio <konradybcio@kernel.org>
			+
			+description:
			+ The Raydium RM692E5 is a generic DSI Panel IC used to control
			+ AMOLED panels.
			+
			+allOf:
			+ - $ref: panel-common.yaml#
			+
			+properties:
			+ compatible:
			+ items:
			+ - const: fairphone,fp5-rm692e5-boe
			+ - const: raydium,rm692e5
			+
			+ dvdd-supply:
			+ description: Digital voltage rail
			+
			+ vci-supply:
			+ description: Analog voltage rail
			+
			+ vddio-supply:
			+ description: I/O voltage rail
			+
			+ reg: true
			+ port: true
			+
			+required:
			+ - compatible
			+ - reg
			+ - reset-gpios
			+ - dvdd-supply
			+ - vci-supply
			+ - vddio-supply
			+ - port
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/gpio/gpio.h>
			+
			+ dsi {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ panel@0 {
			+ compatible = "fairphone,fp5-rm692e5-boe", "raydium,rm692e5";
			+ reg = <0>;
			+
			+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
			+ dvdd-supply = <&vreg_oled_vci>;
			+ vci-supply = <&vreg_l12c>;
			+ vddio-supply = <&vreg_oled_dvdd>;
			+
			+ port {
			+ panel_in_0: endpoint {
			+ remote-endpoint = <&dsi0_out>;
			+ };
			+ };
			+ };
			+ };
			+
			+...

      enum:
        # Anberic RG353V-V2 5.0" 640x480 TFT LCD panel
        - anbernic,rg353v-panel-v2
++      # Powkiddy RGB30 3.0" 720x720 TFT LCD panel
++      - powkiddy,rgb30-panel
        # Rocktech JH057N00900 5.5" 720x1440 TFT LCD panel
        - rocktech,jh057n00900
        # Xingbangda XBD599 5.99" 720x1440 TFT LCD panel

sys/contrib/device-tree/Bindings/display/renesas,shmobile-lcdc.yaml
@@ -0,0 +1,130 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/display/renesas,shmobile-lcdc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Renesas SH-Mobile LCD Controller (LCDC)
			+
			+maintainers:
			+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
			+ - Geert Uytterhoeven <geert+renesas@glider.be>
			+
			+properties:
			+ compatible:
			+ enum:
			+ - renesas,r8a7740-lcdc # R-Mobile A1
			+ - renesas,sh73a0-lcdc # SH-Mobile AG5
			+
			+ reg:
			+ maxItems: 1
			+
			+ interrupts:
			+ maxItems: 1
			+
			+ clocks:
			+ minItems: 1
			+ maxItems: 5
			+ description:
			+ Only the functional clock is mandatory.
			+ Some of the optional clocks are model-dependent (e.g. "video" (a.k.a.
			+ "vou" or "dv_clk") is available on R-Mobile A1 only).
			+
			+ clock-names:
			+ minItems: 1
			+ items:
			+ - const: fck
			+ - enum: [ media, lclk, hdmi, video ]
			+ - enum: [ media, lclk, hdmi, video ]
			+ - enum: [ media, lclk, hdmi, video ]
			+ - enum: [ media, lclk, hdmi, video ]
			+
			+ power-domains:
			+ maxItems: 1
			+
			+ ports:
			+ $ref: /schemas/graph.yaml#/properties/ports
			+
			+ properties:
			+ port@0:
			+ $ref: /schemas/graph.yaml#/properties/port
			+ description: LCD port (R-Mobile A1 and SH-Mobile AG5)
			+ unevaluatedProperties: false
			+
			+ port@1:
			+ $ref: /schemas/graph.yaml#/properties/port
			+ description: HDMI port (R-Mobile A1 LCDC1 and SH-Mobile AG5)
			+ unevaluatedProperties: false
			+
			+ port@2:
			+ $ref: /schemas/graph.yaml#/properties/port
			+ description: MIPI-DSI port (SH-Mobile AG5)
			+ unevaluatedProperties: false
			+
			+ required:
			+ - port@0
			+
			+ unevaluatedProperties: false
			+
			+required:
			+ - compatible
			+ - reg
			+ - interrupts
			+ - clocks
			+ - clock-names
			+ - power-domains
			+ - ports
			+
			+additionalProperties: false
			+
			+allOf:
			+ - if:
			+ properties:
			+ compatible:
			+ contains:
			+ const: renesas,r8a7740-lcdc
			+ then:
			+ properties:
			+ ports:
			+ properties:
			+ port@2: false
			+
			+ - if:
			+ properties:
			+ compatible:
			+ contains:
			+ const: renesas,sh73a0-lcdc
			+ then:
			+ properties:
			+ ports:
			+ required:
			+ - port@1
			+ - port@2
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/r8a7740-clock.h>
			+ #include <dt-bindings/interrupt-controller/arm-gic.h>
			+
			+ lcd-controller@fe940000 {
			+ compatible = "renesas,r8a7740-lcdc";
			+ reg = <0xfe940000 0x4000>;
			+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
			+ clocks = <&mstp1_clks R8A7740_CLK_LCDC0>,
			+ <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk0_clk>,
			+ <&vou_clk>;
			+ clock-names = "fck", "media", "lclk", "video";
			+ power-domains = <&pd_a4lc>;
			+
			+ ports {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ port@0 {
			+ reg = <0>;
			+
			+ lcdc0_rgb: endpoint {
			+ };
			+ };
			+ };
			+ };

            - rockchip,rk3288-mipi-dsi
            - rockchip,rk3399-mipi-dsi
            - rockchip,rk3568-mipi-dsi
++          - rockchip,rv1126-mipi-dsi
        - const: snps,dw-mipi-dsi
    interrupts:
              enum:
                - rockchip,px30-mipi-dsi
                - rockchip,rk3568-mipi-dsi
++              - rockchip,rv1126-mipi-dsi
      then:
        properties:

        - rockchip,rk3368-vop
        - rockchip,rk3399-vop-big
        - rockchip,rk3399-vop-lit
++      - rockchip,rv1126-vop
    reg:
      minItems: 1

sys/contrib/device-tree/Bindings/display/sitronix,st7735r.yaml
@@ -54,11 +54,6 @@ examples:
	- \|	- \|
	#include <dt-bindings/gpio/gpio.h>	#include <dt-bindings/gpio/gpio.h>

	- backlight: backlight {
	- compatible = "gpio-backlight";
	- gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
	- };
	-
	spi {	spi {
	#address-cells = <1>;	#address-cells = <1>;
	#size-cells = <0>;	#size-cells = <0>;

sys/contrib/device-tree/Bindings/display/solomon,ssd-common.yaml
@@ -0,0 +1,42 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/display/solomon,ssd-common.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Common properties for Solomon OLED Display Controllers
			+
			+maintainers:
			+ - Javier Martinez Canillas <javierm@redhat.com>
			+
			+properties:
			+ reg:
			+ maxItems: 1
			+
			+ reset-gpios:
			+ maxItems: 1
			+
			+ # Only required for SPI
			+ dc-gpios:
			+ description:
			+ GPIO connected to the controller's D/C# (Data/Command) pin,
			+ that is needed for 4-wire SPI to tell the controller if the
			+ data sent is for a command register or the display data RAM
			+ maxItems: 1
			+
			+ solomon,height:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ description:
			+ Height in pixel of the screen driven by the controller.
			+ The default value is controller-dependent.
			+
			+ solomon,width:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ description:
			+ Width in pixel of the screen driven by the controller.
			+ The default value is controller-dependent.
			+
			+allOf:
			+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
			+
			+additionalProperties: true

sys/contrib/device-tree/Bindings/display/solomon,ssd1307fb.yaml
@@ -27,38 +27,12 @@ properties:
	- solomon,ssd1307	- solomon,ssd1307
	- solomon,ssd1309	- solomon,ssd1309

	- reg:
	- maxItems: 1
	-
	pwms:	pwms:
	maxItems: 1	maxItems: 1

	- reset-gpios:
	- maxItems: 1
	-
	- # Only required for SPI
	- dc-gpios:
	- description:
	- GPIO connected to the controller's D/C# (Data/Command) pin,
	- that is needed for 4-wire SPI to tell the controller if the
	- data sent is for a command register or the display data RAM
	- maxItems: 1
	-
	vbat-supply:	vbat-supply:
	description: The supply for VBAT	description: The supply for VBAT

	- solomon,height:
	- $ref: /schemas/types.yaml#/definitions/uint32
	- description:
	- Height in pixel of the screen driven by the controller.
	- The default value is controller-dependent.
	-
	- solomon,width:
	- $ref: /schemas/types.yaml#/definitions/uint32
	- description:
	- Width in pixel of the screen driven by the controller.
	- The default value is controller-dependent.
	-
	solomon,page-offset:	solomon,page-offset:
	$ref: /schemas/types.yaml#/definitions/uint32	$ref: /schemas/types.yaml#/definitions/uint32
	default: 1	default: 1
@@ -148,7 +122,7 @@ required:
	- reg	- reg

	allOf:	allOf:
	- - $ref: /schemas/spi/spi-peripheral-props.yaml#	+ - $ref: solomon,ssd-common.yaml#

	- if:	- if:
	properties:	properties:

sys/contrib/device-tree/Bindings/display/solomon,ssd132x.yaml
@@ -0,0 +1,89 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/display/solomon,ssd132x.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Solomon SSD132x OLED Display Controllers
			+
			+maintainers:
			+ - Javier Martinez Canillas <javierm@redhat.com>
			+
			+properties:
			+ compatible:
			+ enum:
			+ - solomon,ssd1322
			+ - solomon,ssd1325
			+ - solomon,ssd1327
			+
			+required:
			+ - compatible
			+ - reg
			+
			+allOf:
			+ - $ref: solomon,ssd-common.yaml#
			+
			+ - if:
			+ properties:
			+ compatible:
			+ contains:
			+ const: solomon,ssd1322
			+ then:
			+ properties:
			+ width:
			+ default: 480
			+ height:
			+ default: 128
			+
			+ - if:
			+ properties:
			+ compatible:
			+ contains:
			+ const: solomon,ssd1325
			+ then:
			+ properties:
			+ width:
			+ default: 128
			+ height:
			+ default: 80
			+
			+ - if:
			+ properties:
			+ compatible:
			+ contains:
			+ const: solomon,ssd1327
			+ then:
			+ properties:
			+ width:
			+ default: 128
			+ height:
			+ default: 128
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ oled@3c {
			+ compatible = "solomon,ssd1327";
			+ reg = <0x3c>;
			+ reset-gpios = <&gpio2 7>;
			+ };
			+
			+ };
			+ - \|
			+ spi {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ oled@0 {
			+ compatible = "solomon,ssd1327";
			+ reg = <0x0>;
			+ reset-gpios = <&gpio2 7>;
			+ dc-gpios = <&gpio2 8>;
			+ spi-max-frequency = <10000000>;
			+ };
			+ };

    dma-channel-mask:
      maxItems: 1
++  dma-coherent: true
++
  required:
    - compatible
    - reg

  allOf:
    - $ref: /schemas/nvmem/nvmem.yaml
++  - $ref: /schemas/nvmem/nvmem-deprecated-cells.yaml
  select:
    properties:
                    pattern: cs16$
                - items:
                    pattern: c32$
++              - items:
++                  pattern: c32d-wl$
                - items:
                    pattern: cs32$
                - items:
                    pattern: c64$
++              - items:
++                  pattern: c64d-wl$
                - items:
                    pattern: cs64$
                - items:

sys/contrib/device-tree/Bindings/firmware/arm,scmi.yaml
@@ -38,6 +38,9 @@ properties:
	with shmem address(4KB-page, offset) as parameters	with shmem address(4KB-page, offset) as parameters
	items:	items:
	- const: arm,scmi-smc-param	- const: arm,scmi-smc-param
		+ - description: SCMI compliant firmware with Qualcomm SMC/HVC transport
		+ items:
		+ - const: qcom,scmi-smc
	- description: SCMI compliant firmware with SCMI Virtio transport.	- description: SCMI compliant firmware with SCMI Virtio transport.
	The virtio transport only supports a single device.	The virtio transport only supports a single device.
	items:	items:
@@ -149,8 +152,15 @@ properties:
	'#clock-cells':	'#clock-cells':
	const: 1	const: 1

	- required:	+ '#power-domain-cells':
	- - '#clock-cells'	+ const: 1
		+
		+ oneOf:
		+ - required:
		+ - '#clock-cells'
		+
		+ - required:
		+ - '#power-domain-cells'

	protocol@14:	protocol@14:
	$ref: '#/$defs/protocol-node'	$ref: '#/$defs/protocol-node'
@@ -306,6 +316,7 @@ else:
	enum:	enum:
	- arm,scmi-smc	- arm,scmi-smc
	- arm,scmi-smc-param	- arm,scmi-smc-param
		+ - qcom,scmi-smc
	then:	then:
	required:	required:
	- arm,smc-id	- arm,smc-id

            - qcom,scm-apq8064
            - qcom,scm-apq8084
            - qcom,scm-ipq4019
++          - qcom,scm-ipq5018
            - qcom,scm-ipq5332
            - qcom,scm-ipq6018
            - qcom,scm-ipq806x
            - qcom,scm-sm6125
            - qcom,scm-sm6350
            - qcom,scm-sm6375
++          - qcom,scm-sm7150
            - qcom,scm-sm8150
            - qcom,scm-sm8250
            - qcom,scm-sm8350
        protocol to handle sleeping SCM calls.
      maxItems: 1
++  qcom,sdi-enabled:
++    description:
++      Indicates that the SDI (Secure Debug Image) has been enabled by TZ
++      by default and it needs to be disabled.
++      If not disabled WDT assertion or reboot will cause the board to hang
++      in the debug mode.
++    type: boolean
++
    qcom,dload-mode:
      $ref: /schemas/types.yaml#/definitions/phandle-array
      items:

sys/contrib/device-tree/Bindings/gpio/fsl-imx-gpio.yaml
@@ -18,9 +18,17 @@ properties:
	- fsl,imx31-gpio	- fsl,imx31-gpio
	- fsl,imx35-gpio	- fsl,imx35-gpio
	- fsl,imx7d-gpio	- fsl,imx7d-gpio
		+ - items:
		+ - enum:
		+ - fsl,imx27-gpio
		+ - const: fsl,imx21-gpio
	- items:	- items:
	- const: fsl,imx35-gpio	- const: fsl,imx35-gpio
	- const: fsl,imx31-gpio	- const: fsl,imx31-gpio
		+ - items:
		+ - enum:
		+ - fsl,imx25-gpio
		+ - const: fsl,imx35-gpio
	- items:	- items:
	- enum:	- enum:
	- fsl,imx50-gpio	- fsl,imx50-gpio

sys/contrib/device-tree/Bindings/gpio/gpio-vf610.yaml
@@ -20,6 +20,7 @@ description: \|
	properties:	properties:
	compatible:	compatible:
	oneOf:	oneOf:
		+ - const: fsl,imx8ulp-gpio
	- const: fsl,vf610-gpio	- const: fsl,vf610-gpio
	- items:	- items:
	- const: fsl,imx7ulp-gpio	- const: fsl,imx7ulp-gpio
@@ -27,16 +28,18 @@ properties:
	- items:	- items:
	- enum:	- enum:
	- fsl,imx93-gpio	- fsl,imx93-gpio
	- - fsl,~~imx8ulp~~-gpio	+ - fsl,imx95-gpio
	- - const: fsl,~~imx7ulp~~-gpio	+ - const: fsl,imx8ulp-gpio

	reg:	reg:
	- description: The first reg tuple represents the PORT module, the second tuple	+ minItems: 1
	- represents the GPIO module.
	maxItems: 2	maxItems: 2

	interrupts:	interrupts:
	- ~~maxItems: 1~~	+ items:
		+ - description: GPIO Trustzone non-secure interrupt number
		+ - description: GPIO Trustzone secure interrupt number
		+ minItems: 1

	interrupt-controller: true	interrupt-controller: true

@@ -59,7 +62,8 @@ properties:
	- const: port	- const: port

	gpio-ranges:	gpio-ranges:
	- ~~maxItems:~~ 1	+ minItems: 1
		+ maxItems: 4

	patternProperties:	patternProperties:
	"^.+-hog(-[0-9]+)?$":	"^.+-hog(-[0-9]+)?$":
@@ -77,6 +81,30 @@ required:
	- "#gpio-cells"	- "#gpio-cells"
	- gpio-controller	- gpio-controller

		+allOf:
		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ enum:
		+ - fsl,vf610-gpio
		+ - fsl,imx7ulp-gpio
		+ then:
		+ properties:
		+ interrupts:
		+ maxItems: 1
		+ reg:
		+ items:
		+ - description: PORT register base address
		+ - description: GPIO register base address
		+ else:
		+ properties:
		+ interrupts:
		+ minItems: 2
		+ reg:
		+ items:
		+ - description: GPIO register base address
		+
	additionalProperties: false	additionalProperties: false

	examples:	examples:

sys/contrib/device-tree/Bindings/gpio/intel,ixp4xx-gpio.yaml
@@ -0,0 +1,73 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/gpio/intel,ixp4xx-gpio.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Intel IXP4xx XScale Networking Processors GPIO Controller
			+
			+description: \|
			+ This GPIO controller is found in the Intel IXP4xx
			+ processors. It supports 16 GPIO lines.
			+ The interrupt portions of the GPIO controller is hierarchical.
			+ The synchronous edge detector is part of the GPIO block, but the
			+ actual enabling/disabling of the interrupt line is done in the
			+ main IXP4xx interrupt controller which has a 1-to-1 mapping for
			+ the first 12 GPIO lines to 12 system interrupts.
			+ The remaining 4 GPIO lines can not be used for receiving
			+ interrupts.
			+ The interrupt parent of this GPIO controller must be the
			+ IXP4xx interrupt controller.
			+ GPIO 14 and 15 can be used as clock outputs rather than GPIO,
			+ and this can be enabled by a special flag.
			+
			+maintainers:
			+ - Linus Walleij <linus.walleij@linaro.org>
			+
			+properties:
			+ compatible:
			+ const: intel,ixp4xx-gpio
			+
			+ reg:
			+ maxItems: 1
			+
			+ gpio-controller: true
			+
			+ "#gpio-cells":
			+ const: 2
			+
			+ interrupt-controller: true
			+
			+ "#interrupt-cells":
			+ const: 2
			+
			+ intel,ixp4xx-gpio14-clkout:
			+ description: If defined, enables clock output on GPIO 14
			+ instead of GPIO.
			+ type: boolean
			+
			+ intel,ixp4xx-gpio15-clkout:
			+ description: If defined, enables clock output on GPIO 15
			+ instead of GPIO.
			+ type: boolean
			+
			+required:
			+ - compatible
			+ - reg
			+ - "#gpio-cells"
			+ - interrupt-controller
			+ - "#interrupt-cells"
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/interrupt-controller/irq.h>
			+ gpio@c8004000 {
			+ compatible = "intel,ixp4xx-gpio";
			+ reg = <0xc8004000 0x1000>;
			+ gpio-controller;
			+ #gpio-cells = <2>;
			+ interrupt-controller;
			+ #interrupt-cells = <2>;
			+ };

sys/contrib/device-tree/Bindings/gpio/loongson,ls-gpio.yaml
@@ -11,9 +11,22 @@ maintainers:

	properties:	properties:
	compatible:	compatible:
	- ~~enum:~~	+ oneOf:
	- - loongson,ls2k-gpio	+ - enum:
	- - loongson,~~ls7a~~-gpio	+ - loongson,ls2k-gpio
		+ - loongson,ls2k0500-gpio0
		+ - loongson,ls2k0500-gpio1
		+ - loongson,ls2k2000-gpio0
		+ - loongson,ls2k2000-gpio1
		+ - loongson,ls2k2000-gpio2
		+ - loongson,ls3a5000-gpio
		+ - loongson,ls7a-gpio
		+ - items:
		+ - const: loongson,ls2k1000-gpio
		+ - const: loongson,ls2k-gpio
		+ - items:
		+ - const: loongson,ls7a1000-gpio
		+ - const: loongson,ls7a-gpio

	reg:	reg:
	maxItems: 1	maxItems: 1
@@ -49,7 +62,7 @@ examples:
	#include <dt-bindings/interrupt-controller/irq.h>	#include <dt-bindings/interrupt-controller/irq.h>

	gpio0: gpio@1fe00500 {	gpio0: gpio@1fe00500 {
	- compatible = "loongson,ls2k-gpio";	+ compatible = "loongson,ls2k1000-gpio", "loongson,ls2k-gpio";
	reg = <0x1fe00500 0x38>;	reg = <0x1fe00500 0x38>;
	ngpios = <64>;	ngpios = <64>;
	#gpio-cells = <2>;	#gpio-cells = <2>;

sys/contrib/device-tree/Bindings/hwmon/adi,ltc2991.yaml
@@ -0,0 +1,128 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+
			+$id: http://devicetree.org/schemas/hwmon/adi,ltc2991.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Analog Devices LTC2991 Octal I2C Voltage, Current and Temperature Monitor
			+
			+maintainers:
			+ - Antoniu Miclaus <antoniu.miclaus@analog.com>
			+
			+description: \|
			+ The LTC2991 is used to monitor system temperatures, voltages and currents.
			+ Through the I2C serial interface, the eight monitors can individually measure
			+ supply voltages and can be paired for differential measurements of current
			+ sense resistors or temperature sensing transistors.
			+
			+ Datasheet:
			+ https://www.analog.com/en/products/ltc2991.html
			+
			+properties:
			+ compatible:
			+ const: adi,ltc2991
			+
			+ reg:
			+ maxItems: 1
			+
			+ '#address-cells':
			+ const: 1
			+
			+ '#size-cells':
			+ const: 0
			+
			+ vcc-supply: true
			+
			+patternProperties:
			+ "^channel@[0-3]$":
			+ type: object
			+ description:
			+ Represents the differential/temperature channels.
			+
			+ properties:
			+ reg:
			+ description:
			+ The channel number. LTC2991 can monitor 4 currents/temperatures.
			+ items:
			+ minimum: 0
			+ maximum: 3
			+
			+ shunt-resistor-micro-ohms:
			+ description:
			+ The value of curent sense resistor in micro ohms. Pin configuration is
			+ set for differential input pair.
			+
			+ adi,temperature-enable:
			+ description:
			+ Enables temperature readings. Pin configuration is set for remote
			+ diode temperature measurement.
			+ type: boolean
			+
			+ required:
			+ - reg
			+
			+ allOf:
			+ - if:
			+ required:
			+ - shunt-resistor-micro-ohms
			+ then:
			+ properties:
			+ adi,temperature-enable: false
			+
			+ additionalProperties: false
			+
			+required:
			+ - compatible
			+ - reg
			+ - vcc-supply
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ hwmon@48 {
			+ compatible = "adi,ltc2991";
			+ reg = <0x48>;
			+ vcc-supply = <&vcc>;
			+ };
			+ };
			+ - \|
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ hwmon@48 {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ compatible = "adi,ltc2991";
			+ reg = <0x48>;
			+ vcc-supply = <&vcc>;
			+
			+ channel@0 {
			+ reg = <0x0>;
			+ shunt-resistor-micro-ohms = <100000>;
			+ };
			+
			+ channel@1 {
			+ reg = <0x1>;
			+ shunt-resistor-micro-ohms = <100000>;
			+ };
			+
			+ channel@2 {
			+ reg = <0x2>;
			+ adi,temperature-enable;
			+ };
			+
			+ channel@3 {
			+ reg = <0x3>;
			+ adi,temperature-enable;
			+ };
			+ };
			+ };
			+...

sys/contrib/device-tree/Bindings/hwmon/adi,max31827.yaml
@@ -32,6 +32,68 @@ properties:
	Must have values in the interval (1.6V; 3.6V) in order for the device to	Must have values in the interval (1.6V; 3.6V) in order for the device to
	function correctly.	function correctly.

		+ adi,comp-int:
		+ description:
		+ If present interrupt mode is used. If not present comparator mode is used
		+ (default).
		+ type: boolean
		+
		+ adi,alarm-pol:
		+ description:
		+ Sets the alarms active state.
		+ - 0 = active low
		+ - 1 = active high
		+ $ref: /schemas/types.yaml#/definitions/uint32
		+ enum: [0, 1]
		+
		+ adi,fault-q:
		+ description:
		+ Select how many consecutive temperature faults must occur before
		+ overtemperature or undertemperature faults are indicated in the
		+ corresponding status bits.
		+ $ref: /schemas/types.yaml#/definitions/uint32
		+ enum: [1, 2, 4, 8]
		+
		+ adi,timeout-enable:
		+ description:
		+ Enables timeout. Bus timeout resets the I2C-compatible interface when SCL
		+ is low for more than 30ms (nominal).
		+ type: boolean
		+
		+allOf:
		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ const: adi,max31829
		+
		+ then:
		+ properties:
		+ adi,alarm-pol:
		+ default: 1
		+
		+ else:
		+ properties:
		+ adi,alarm-pol:
		+ default: 0
		+
		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ const: adi,max31827
		+
		+ then:
		+ properties:
		+ adi,fault-q:
		+ default: 1
		+
		+ else:
		+ properties:
		+ adi,fault-q:
		+ default: 4
		+
		+
	required:	required:
	- compatible	- compatible
	- reg	- reg
@@ -49,6 +111,10 @@ examples:
	compatible = "adi,max31827";	compatible = "adi,max31827";
	reg = <0x42>;	reg = <0x42>;
	vref-supply = <&reg_vdd>;	vref-supply = <&reg_vdd>;
		+ adi,comp-int;
		+ adi,alarm-pol = <0>;
		+ adi,fault-q = <1>;
		+ adi,timeout-enable;
	};	};
	};	};
	...	...

--Nuvoton NPCM7xx PWM and Fan Tacho controller device
++Nuvoton NPCM PWM and Fan Tacho controller device
  The Nuvoton BMC NPCM7XX supports 8 Pulse-width modulation (PWM)
  controller outputs and 16 Fan tachometer controller inputs.
++The Nuvoton BMC NPCM8XX supports 12 Pulse-width modulation (PWM)
++controller outputs and 16 Fan tachometer controller inputs.
++
  Required properties for pwm-fan node
  - #address-cells : should be 1.
  - #size-cells        : should be 0.
  - compatible        : "nuvoton,npcm750-pwm-fan" for Poleg NPCM7XX.
++                                : "nuvoton,npcm845-pwm-fan" for Arbel NPCM8XX.
  - reg                        : specifies physical base address and size of the registers.
  - reg-names        : must contain:
                                          * "pwm" for the PWM registers.

sys/contrib/device-tree/Bindings/hwmon/pmbus/infineon,tda38640.yaml
@@ -0,0 +1,49 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+
			+$id: http://devicetree.org/schemas/hwmon/pmbus/infineon,tda38640.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Infineon TDA38640 Synchronous Buck Regulator with SVID and I2C
			+
			+maintainers:
			+ - Naresh Solanki <naresh.solanki@9elements.com>
			+
			+description: \|
			+ The Infineon TDA38640 is a 40A Single-voltage Synchronous Buck
			+ Regulator with SVID and I2C designed for Industrial use.
			+
			+ Datasheet: https://www.infineon.com/dgdl/Infineon-TDA38640-0000-DataSheet-v02_04-EN.pdf?fileId=8ac78c8c80027ecd018042f2337f00c9
			+
			+properties:
			+ compatible:
			+ enum:
			+ - infineon,tda38640
			+
			+ reg:
			+ maxItems: 1
			+
			+ infineon,en-pin-fixed-level:
			+ description:
			+ Indicates that the chip EN pin is at fixed level or left
			+ unconnected(has internal pull-down).
			+ type: boolean
			+
			+required:
			+ - compatible
			+ - reg
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ tda38640@40 {
			+ compatible = "infineon,tda38640";
			+ reg = <0x40>;
			+ };
			+ };

        - ti,ina226
        - ti,ina230
        - ti,ina231
++      - ti,ina237
        - ti,ina238
    reg:

sys/contrib/device-tree/Bindings/hwmon/ti,ina3221.yaml
@@ -0,0 +1,121 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/hwmon/ti,ina3221.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Texas Instruments INA3221 Current and Voltage Monitor
			+
			+maintainers:
			+ - Jean Delvare <jdelvare@suse.com>
			+ - Guenter Roeck <linux@roeck-us.net>
			+
			+properties:
			+ compatible:
			+ const: ti,ina3221
			+
			+ reg:
			+ maxItems: 1
			+
			+ ti,single-shot:
			+ description: \|
			+ This chip has two power modes: single-shot (chip takes one measurement
			+ and then shuts itself down) and continuous (chip takes continuous
			+ measurements). The continuous mode is more reliable and suitable for
			+ hardware monitor type device, but the single-shot mode is more power-
			+ friendly and useful for battery-powered device which cares power
			+ consumptions while still needs some measurements occasionally.
			+
			+ If this property is present, the single-shot mode will be used, instead
			+ of the default continuous one for monitoring.
			+ $ref: /schemas/types.yaml#/definitions/flag
			+
			+ "#address-cells":
			+ description: Required only if a child node is present.
			+ const: 1
			+
			+ "#size-cells":
			+ description: Required only if a child node is present.
			+ const: 0
			+
			+patternProperties:
			+ "^input@[0-2]$":
			+ description: The node contains optional child nodes for three channels.
			+ Each child node describes the information of input source. Input channels
			+ default to enabled in the chip. Unless channels are explicitly disabled
			+ in device-tree, input channels will be enabled.
			+ type: object
			+ additionalProperties: false
			+ properties:
			+ reg:
			+ description: Must be 0, 1 and 2, corresponding to the IN1, IN2 or IN3
			+ ports of the INA3221, respectively.
			+ enum: [ 0, 1, 2 ]
			+
			+ label:
			+ description: name of the input source
			+
			+ shunt-resistor-micro-ohms:
			+ description: shunt resistor value in micro-Ohm
			+
			+ ti,summation-disable:
			+ description: \|
			+ The INA3221 has a critical alert pin that can be controlled by the
			+ summation control function. This function adds the single
			+ shunt-voltage conversions for the desired channels in order to
			+ compare the combined sum to the programmed limit. The Shunt-Voltage
			+ Sum Limit register contains the programmed value that is compared
			+ to the value in the Shunt-Voltage Sum register in order to
			+ determine if the total summed limit is exceeded. If the
			+ shunt-voltage sum limit value is exceeded, the critical alert pin
			+ is asserted.
			+
			+ For the summation limit to have a meaningful value, it is necessary
			+ to use the same shunt-resistor value on all enabled channels. If
			+ this is not the case or if a channel should not be used for
			+ triggering the critical alert pin, then this property can be used
			+ exclude specific channels from the summation control function.
			+ type: boolean
			+
			+ required:
			+ - reg
			+
			+required:
			+ - compatible
			+ - reg
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ power-sensor@40 {
			+ compatible = "ti,ina3221";
			+ reg = <0x40>;
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ input@0 {
			+ reg = <0x0>;
			+ /*
			+ * Input channels are enabled by default in the device and so
			+ * to disable, must be explicitly disabled in device-tree.
			+ */
			+ status = "disabled";
			+ };
			+
			+ input@1 {
			+ reg = <0x1>;
			+ shunt-resistor-micro-ohms = <5000>;
			+ };
			+
			+ input@2 {
			+ reg = <0x2>;
			+ label = "VDD_5V";
			+ shunt-resistor-micro-ohms = <5000>;
			+ };
			+ };
			+ };

sys/contrib/device-tree/Bindings/i2c/i2c-demux-pinctrl.yaml
@@ -0,0 +1,172 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/i2c/i2c-demux-pinctrl.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Pinctrl-based I2C Bus Demultiplexer
			+
			+maintainers:
			+ - Wolfram Sang <wsa+renesas@sang-engineering.com>
			+
			+description: \|
			+ This binding describes an I2C bus demultiplexer that uses pin multiplexing to
			+ route the I2C signals, and represents the pin multiplexing configuration
			+ using the pinctrl device tree bindings. This may be used to select one I2C
			+ IP core at runtime which may have a better feature set for a given task than
			+ another I2C IP core on the SoC. The most simple example is to fall back to
			+ GPIO bitbanging if your current runtime configuration hits an errata of the
			+ internal IP core.
			+
			+ +-------------------------------+
			+ \| SoC \|
			+ \| \| +-----+ +-----+
			+ \| +------------+ \| \| dev \| \| dev \|
			+ \| \|I2C IP Core1\|--\ \| +-----+ +-----+
			+ \| +------------+ \-------+ \| \| \|
			+ \| \|Pinctrl\|--\|------+--------+
			+ \| +------------+ +-------+ \|
			+ \| \|I2C IP Core2\|--/ \|
			+ \| +------------+ \|
			+ \| \|
			+ +-------------------------------+
			+
			+allOf:
			+ - $ref: i2c-mux.yaml
			+ - $ref: /schemas/i2c/i2c-controller.yaml#
			+
			+properties:
			+ compatible:
			+ const: i2c-demux-pinctrl
			+
			+ i2c-parent:
			+ $ref: /schemas/types.yaml#/definitions/phandle-array
			+ description:
			+ List of phandles of I2C masters available for selection. The first one
			+ will be used as default.
			+
			+ i2c-bus-name:
			+ $ref: /schemas/types.yaml#/definitions/string
			+ description:
			+ The name of this bus. Also needed as pinctrl-name for the I2C parents.
			+
			+required:
			+ - compatible
			+ - i2c-parent
			+ - i2c-bus-name
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/gpio/gpio.h>
			+ #include <dt-bindings/interrupt-controller/irq.h>
			+
			+ gpioi2c2: i2c-9 {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+ compatible = "i2c-gpio";
			+ scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
			+ sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
			+ i2c-gpio,delay-us = <5>;
			+
			+ // The I2C controller must have its status "disabled". The I2C bus
			+ // demultiplexer will enable it at runtime when needed.
			+ status = "disabled";
			+ };
			+
			+ iic2: i2c@e6520000 {
			+ reg = <0xe6520000 0x425>;
			+ pinctrl-0 = <&iic2_pins>;
			+ // The pinctrl property for the parent I2C controller needs a pinctrl
			+ // state with the same name as i2c-bus-name in the I2C bus demultiplexer
			+ // node, not "default"!
			+ pinctrl-names = "i2c-hdmi";
			+
			+ clock-frequency = <100000>;
			+
			+ // The I2C controller must have its status "disabled". The I2C bus
			+ // demultiplexer will enable it at runtime when needed.
			+ status = "disabled";
			+ };
			+
			+ i2c2: i2c@e6530000 {
			+ reg = <0 0xe6530000 0 0x40>;
			+ pinctrl-0 = <&i2c2_pins>;
			+ // The pinctrl property for the parent I2C controller needs a pinctrl
			+ // state with the same name as i2c-bus-name in the I2C bus demultiplexer
			+ // node, not "default"!
			+ pinctrl-names = "i2c-hdmi";
			+
			+ clock-frequency = <100000>;
			+
			+ // The I2C controller must have its status "disabled". The I2C bus
			+ // demultiplexer will enable it at runtime when needed.
			+ status = "disabled";
			+ };
			+
			+ // Example for a bus to be demuxed. It contains various I2C clients for
			+ // HDMI, so the bus is named "i2c-hdmi":
			+ i2chdmi: i2c-mux3 {
			+ compatible = "i2c-demux-pinctrl";
			+ i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>;
			+ i2c-bus-name = "i2c-hdmi";
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ ak4643: codec@12 {
			+ compatible = "asahi-kasei,ak4643";
			+ #sound-dai-cells = <0>;
			+ reg = <0x12>;
			+ };
			+
			+ composite-in@20 {
			+ compatible = "adi,adv7180";
			+ reg = <0x20>;
			+
			+ port {
			+ adv7180: endpoint {
			+ bus-width = <8>;
			+ remote-endpoint = <&vin1ep0>;
			+ };
			+ };
			+ };
			+
			+ hdmi@39 {
			+ compatible = "adi,adv7511w";
			+ reg = <0x39>;
			+ interrupt-parent = <&gpio1>;
			+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
			+ clocks = <&cec_clock>;
			+ clock-names = "cec";
			+
			+ avdd-supply = <&fixedregulator1v8>;
			+ dvdd-supply = <&fixedregulator1v8>;
			+ pvdd-supply = <&fixedregulator1v8>;
			+ dvdd-3v-supply = <&fixedregulator3v3>;
			+ bgvdd-supply = <&fixedregulator1v8>;
			+
			+ adi,input-depth = <8>;
			+ adi,input-colorspace = "rgb";
			+ adi,input-clock = "1x";
			+
			+ ports {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ port@0 {
			+ reg = <0>;
			+ adv7511_in: endpoint {
			+ remote-endpoint = <&lvds0_out>;
			+ };
			+ };
			+
			+ port@1 {
			+ reg = <1>;
			+ adv7511_out: endpoint {
			+ remote-endpoint = <&hdmi_con_out>;
			+ };
			+ };
			+ };
			+ };
			+ };

        - items:
            - enum:
++              - qcom,sc7280-cci
                - qcom,sdm845-cci
                - qcom,sm6350-cci
                - qcom,sm8250-cci
          compatible:
            contains:
              enum:
++              - qcom,sc7280-cci
                - qcom,sm8250-cci
                - qcom,sm8450-cci
      then:

        May not be supported by all controllers.
++  mctp-controller:
++    type: boolean
++    description: |
++      Indicates that the system is accessible via this bus as an endpoint for
++      MCTP over I3C transport.
++
  required:
    - "#address-cells"
    - "#size-cells"
                  minimum: 0
                  maximum: 0x7f
                - description: |
--                  First half of the Provisional ID (following the PID
++                  First half of the Provisioned ID (following the PID
                    definition provided by the I3C specification).
                    Contains the manufacturer ID left-shifted by 1.
                - description: |
--                  Second half of the Provisional ID (following the PID
++                  Second half of the Provisioned ID (following the PID
                    definition provided by the I3C specification).
                    Contains the ORing of the part ID left-shifted by 16,

sys/contrib/device-tree/Bindings/iio/accel/kionix,kx022a.yaml
@@ -4,19 +4,23 @@
	$id: http://devicetree.org/schemas/iio/accel/kionix,kx022a.yaml#	$id: http://devicetree.org/schemas/iio/accel/kionix,kx022a.yaml#
	$schema: http://devicetree.org/meta-schemas/core.yaml#	$schema: http://devicetree.org/meta-schemas/core.yaml#

	-title: ROHM/Kionix KX022A ~~Accelerometer~~	+title: ROHM/Kionix KX022A, KX132-1211 and KX132ACR-LBZ Accelerometers

	maintainers:	maintainers:
	- Matti Vaittinen <mazziesaccount@gmail.com>	- Matti Vaittinen <mazziesaccount@gmail.com>

	description: \|	description: \|
	- KX022A is a 3-axis accelerometer supporting +/- 2G, 4G, 8G and 16G ranges,	+ KX022A, KX132ACR-LBZ and KX132-1211 are 3-axis accelerometers supporting
	- output data-rates from 0.78Hz to 1600Hz and a hardware-fifo buffering.	+ +/- 2G, 4G, 8G and 16G ranges, variable output data-rates and a
	- KX022A can be accessed either via I2C or SPI.	+ hardware-fifo buffering. These accelerometers can be accessed either
		+ via I2C or SPI.

	properties:	properties:
	compatible:	compatible:
	- const: kionix,kx022a	+ enum:
		+ - kionix,kx022a
		+ - kionix,kx132-1211
		+ - rohm,kx132acr-lbz

	reg:	reg:
	maxItems: 1	maxItems: 1

sys/contrib/device-tree/Bindings/iio/adc/lltc,ltc2497.yaml
@@ -4,21 +4,31 @@
	$id: http://devicetree.org/schemas/iio/adc/lltc,ltc2497.yaml#	$id: http://devicetree.org/schemas/iio/adc/lltc,ltc2497.yaml#
	$schema: http://devicetree.org/meta-schemas/core.yaml#	$schema: http://devicetree.org/meta-schemas/core.yaml#

	-title: Linear Technology / Analog Devices LTC2497 ADC	+title: Linear Technology / Analog Devices LTC2497 and LTC2309 ADC

	maintainers:	maintainers:
	- Michael Hennerich <michael.hennerich@analog.com>	- Michael Hennerich <michael.hennerich@analog.com>
		+ - Liam Beguin <liambeguin@gmail.com>

	description: \|	description: \|
	- 16bit ADC supporting up to 16 single ended or 8 differential inputs.	+ LTC2309:
	- I2C interface.	+ low noise, low power, 8-channel, 12-bit successive approximation ADC with an
		+ I2C compatible serial interface.

	- https://www.analog.com/media/en/technical-documentation/data-sheets/~~2497fb~~.pdf	+ https://www.analog.com/media/en/technical-documentation/data-sheets/2309fd.pdf
	- https://www.analog.com/media/en/technical-documentation/data-sheets/2499fe.pdf	+
		+ LTC2497:
		+ LTC2499:
		+ 16bit ADC supporting up to 16 single ended or 8 differential inputs.
		+ I2C interface.
		+
		+ https://www.analog.com/media/en/technical-documentation/data-sheets/2497fb.pdf
		+ https://www.analog.com/media/en/technical-documentation/data-sheets/2499fe.pdf

	properties:	properties:
	compatible:	compatible:
	enum:	enum:
		+ - lltc,ltc2309
	- lltc,ltc2497	- lltc,ltc2497
	- lltc,ltc2499	- lltc,ltc2499

sys/contrib/device-tree/Bindings/iio/adc/microchip,mcp3564.yaml
@@ -0,0 +1,205 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/iio/adc/microchip,mcp3564.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Microchip MCP346X and MCP356X ADC Family
			+
			+maintainers:
			+ - Marius Cristea <marius.cristea@microchip.com>
			+
			+description: \|
			+ Bindings for the Microchip family of 153.6 ksps, Low-Noise 16/24-Bit
			+ Delta-Sigma ADCs with an SPI interface. Datasheet can be found here:
			+ Datasheet for MCP3561, MCP3562, MCP3564 can be found here:
			+ https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/MCP3561-2-4-Family-Data-Sheet-DS20006181C.pdf
			+ Datasheet for MCP3561R, MCP3562R, MCP3564R can be found here:
			+ https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3561_2_4R-Data-Sheet-DS200006391C.pdf
			+ Datasheet for MCP3461, MCP3462, MCP3464 can be found here:
			+ https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3461-2-4-Two-Four-Eight-Channel-153.6-ksps-Low-Noise-16-Bit-Delta-Sigma-ADC-Data-Sheet-20006180D.pdf
			+ Datasheet for MCP3461R, MCP3462R, MCP3464R can be found here:
			+ https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3461-2-4R-Family-Data-Sheet-DS20006404C.pdf
			+
			+properties:
			+ compatible:
			+ enum:
			+ - microchip,mcp3461
			+ - microchip,mcp3462
			+ - microchip,mcp3464
			+ - microchip,mcp3461r
			+ - microchip,mcp3462r
			+ - microchip,mcp3464r
			+ - microchip,mcp3561
			+ - microchip,mcp3562
			+ - microchip,mcp3564
			+ - microchip,mcp3561r
			+ - microchip,mcp3562r
			+ - microchip,mcp3564r
			+
			+ reg:
			+ maxItems: 1
			+
			+ spi-max-frequency:
			+ maximum: 20000000
			+
			+ spi-cpha: true
			+
			+ spi-cpol: true
			+
			+ vdd-supply: true
			+
			+ avdd-supply: true
			+
			+ clocks:
			+ description:
			+ Phandle and clock identifier for external sampling clock.
			+ If not specified, the internal crystal oscillator will be used.
			+ maxItems: 1
			+
			+ interrupts:
			+ description: IRQ line of the ADC
			+ maxItems: 1
			+
			+ drive-open-drain:
			+ description:
			+ Whether to drive the IRQ signal as push-pull (default) or open-drain. Note
			+ that the device requires this pin to become "high", otherwise it will stop
			+ converting.
			+ type: boolean
			+
			+ vref-supply:
			+ description:
			+ Some devices have a specific reference voltage supplied on a different
			+ pin to the other supplies. Needed to be able to establish channel scaling
			+ unless there is also an internal reference available (e.g. mcp3564r). In
			+ case of "r" devices (e. g. mcp3564r), if it does not exists the internal
			+ reference will be used.
			+
			+ microchip,hw-device-address:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ minimum: 0
			+ maximum: 3
			+ description:
			+ The address is set on a per-device basis by fuses in the factory,
			+ configured on request. If not requested, the fuses are set for 0x1.
			+ The device address is part of the device markings to avoid
			+ potential confusion. This address is coded on two bits, so four possible
			+ addresses are available when multiple devices are present on the same
			+ SPI bus with only one Chip Select line for all devices.
			+ Each device communication starts by a CS falling edge, followed by the
			+ clocking of the device address (BITS[7:6] - top two bits of COMMAND BYTE
			+ which is first one on the wire).
			+
			+ "#io-channel-cells":
			+ const: 1
			+
			+ "#address-cells":
			+ const: 1
			+
			+ "#size-cells":
			+ const: 0
			+
			+patternProperties:
			+ "^channel@([0-9]\|([1-7][0-9]))$":
			+ $ref: adc.yaml
			+ type: object
			+ unevaluatedProperties: false
			+ description: Represents the external channels which are connected to the ADC.
			+
			+ properties:
			+ reg:
			+ description: The channel number in single-ended and differential mode.
			+ minimum: 0
			+ maximum: 79
			+
			+ required:
			+ - reg
			+
			+dependencies:
			+ spi-cpol: [ spi-cpha ]
			+ spi-cpha: [ spi-cpol ]
			+
			+required:
			+ - compatible
			+ - reg
			+ - microchip,hw-device-address
			+ - spi-max-frequency
			+
			+allOf:
			+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
			+ - # External vref, no internal reference
			+ if:
			+ properties:
			+ compatible:
			+ contains:
			+ enum:
			+ - microchip,mcp3461
			+ - microchip,mcp3462
			+ - microchip,mcp3464
			+ - microchip,mcp3561
			+ - microchip,mcp3562
			+ - microchip,mcp3564
			+ then:
			+ required:
			+ - vref-supply
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ spi {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ adc@0 {
			+ compatible = "microchip,mcp3564r";
			+ reg = <0>;
			+ vref-supply = <&vref_reg>;
			+ spi-cpha;
			+ spi-cpol;
			+ spi-max-frequency = <10000000>;
			+ microchip,hw-device-address = <1>;
			+
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ channel@0 {
			+ /* CH0 to AGND */
			+ reg = <0>;
			+ label = "CH0";
			+ };
			+
			+ channel@1 {
			+ /* CH1 to AGND */
			+ reg = <1>;
			+ label = "CH1";
			+ };
			+
			+ /* diff-channels */
			+ channel@11 {
			+ reg = <11>;
			+
			+ /* CN0, CN1 */
			+ diff-channels = <0 1>;
			+ label = "CH0_CH1";
			+ };
			+
			+ channel@22 {
			+ reg = <0x22>;
			+
			+ /* CN1, CN2 */
			+ diff-channels = <1 2>;
			+ label = "CH1_CH3";
			+ };
			+
			+ channel@23 {
			+ reg = <0x23>;
			+
			+ /* CN1, CN3 */
			+ diff-channels = <1 3>;
			+ label = "CH1_CH3";
			+ };
			+ };
			+ };
			+...

sys/contrib/device-tree/Bindings/iio/adc/microchip,mcp3911.yaml
@@ -18,7 +18,13 @@ description: \|
	properties:	properties:
	compatible:	compatible:
	enum:	enum:
		+ - microchip,mcp3910
	- microchip,mcp3911	- microchip,mcp3911
		+ - microchip,mcp3912
		+ - microchip,mcp3913
		+ - microchip,mcp3914
		+ - microchip,mcp3918
		+ - microchip,mcp3919

	reg:	reg:
	maxItems: 1	maxItems: 1

    reg:
      maxItems: 1
++  interrupts:
++    maxItems: 1
++
    "#address-cells":
      const: 1

sys/contrib/device-tree/Bindings/iio/adc/ti,twl6030-gpadc.yaml
@@ -0,0 +1,43 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/iio/adc/ti,twl6030-gpadc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: GPADC subsystem in the TWL6030 power module
			+
			+maintainers:
			+ - Andreas Kemnade <andreas@kemnade.info>
			+
			+description:
			+ The GPADC subsystem in the TWL603X consists of a 10-bit ADC
			+ combined with a 15-input analog multiplexer in the TWL6030 resp. a
			+ 19-input analog muliplexer in the TWL6032.
			+
			+properties:
			+ compatible:
			+ enum:
			+ - ti,twl6030-gpadc
			+ - ti,twl6032-gpadc
			+
			+ interrupts:
			+ maxItems: 1
			+
			+ "#io-channel-cells":
			+ const: 1
			+
			+required:
			+ - compatible
			+ - interrupts
			+ - "#io-channel-cells"
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ gpadc {
			+ compatible = "ti,twl6030-gpadc";
			+ interrupts = <3>;
			+ #io-channel-cells = <1>;
			+ };
			+...

  $id: http://devicetree.org/schemas/iio/amplifiers/adi,hmc425a.yaml#
  $schema: http://devicetree.org/meta-schemas/core.yaml#
--title: HMC425A 6-bit Digital Step Attenuator
++title: Analog Devices HMC425A and similar Digital Step Attenuators
  maintainers:
    - Michael Hennerich <michael.hennerich@analog.com>
  description: |
--  Digital Step Attenuator IIO device with gpio interface.
++  Digital Step Attenuator IIO devices with gpio interface.
++  Offer various frequency and attenuation ranges.
    HMC425A 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL POSITIVE CONTROL ATTENUATOR, 2.2 - 8.0 GHz
--  https://www.analog.com/media/en/technical-documentation/data-sheets/hmc425A.pdf
++    https://www.analog.com/media/en/technical-documentation/data-sheets/hmc425A.pdf
++
++  HMC540S 1 dB LSB Silicon MMIC 4-Bit Digital Positive Control Attenuator, 0.1 - 8 GHz
++    https://www.analog.com/media/en/technical-documentation/data-sheets/hmc540s.pdf
++
  properties:
    compatible:
      enum:
        - adi,hmc425a
++      - adi,hmc540s
    vcc-supply: true

sys/contrib/device-tree/Bindings/iio/imu/invensense,mpu6050.yaml
@@ -48,6 +48,11 @@ properties:

	mount-matrix: true	mount-matrix: true

		+ invensense,level-shifter:
		+ type: boolean
		+ description: \|
		+ From ancient platform data struct: false: VLogic, true: VDD
		+
	i2c-gate:	i2c-gate:
	$ref: /schemas/i2c/i2c-controller.yaml	$ref: /schemas/i2c/i2c-controller.yaml
	unevaluatedProperties: false	unevaluatedProperties: false

    wakeup-source:
      $ref: /schemas/types.yaml#/definitions/flag
++  mount-matrix:
++    description: an optional 3x3 mounting rotation matrix
++
  required:
    - compatible
    - reg

sys/contrib/device-tree/Bindings/iio/pressure/rohm,bm1390.yaml
@@ -0,0 +1,52 @@
			+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/iio/pressure/rohm,bm1390.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: ROHM BM1390 pressure sensor
			+
			+maintainers:
			+ - Matti Vaittinen <mazziesaccount@gmail.com>
			+
			+description:
			+ BM1390GLV-Z is a pressure sensor which performs internal temperature
			+ compensation for the MEMS. Pressure range is from 300 hPa to 1300 hPa
			+ and sample averaging and IIR filtering is built in. Temperature
			+ measurement is also supported.
			+
			+properties:
			+ compatible:
			+ const: rohm,bm1390glv-z
			+
			+ reg:
			+ maxItems: 1
			+
			+ interrupts:
			+ maxItems: 1
			+
			+ vdd-supply: true
			+
			+required:
			+ - compatible
			+ - reg
			+ - vdd-supply
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/interrupt-controller/irq.h>
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+ pressure-sensor@5d {
			+ compatible = "rohm,bm1390glv-z";
			+ reg = <0x5d>;
			+
			+ interrupt-parent = <&gpio1>;
			+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
			+
			+ vdd-supply = <&vdd>;
			+ };
			+ };

sys/contrib/device-tree/Bindings/iio/resolver/adi,ad2s1210.yaml
@@ -0,0 +1,177 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/iio/resolver/adi,ad2s1210.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Analog Devices AD2S1210 Resolver-to-Digital Converter
			+
			+maintainers:
			+ - Michael Hennerich <michael.hennerich@analog.com>
			+
			+description: \|
			+ The AD2S1210 is a complete 10-bit to 16-bit resolution tracking
			+ resolver-to-digital converter, integrating an on-board programmable
			+ sinusoidal oscillator that provides sine wave excitation for
			+ resolvers.
			+
			+ The AD2S1210 allows the user to read the angular position or the
			+ angular velocity data directly from the parallel outputs or through
			+ the serial interface.
			+
			+ The mode of operation of the communication channel (parallel or serial) is
			+ selected by the A0 and A1 input pins. In normal mode, data is latched by
			+ toggling the SAMPLE line and can then be read directly. In configuration mode,
			+ data is read or written using a register access scheme (address byte with
			+ read/write flag and data byte).
			+
			+ A1 A0 Result
			+ 0 0 Normal mode - position output
			+ 0 1 Normal mode - velocity output
			+ 1 0 Reserved
			+ 1 1 Configuration mode
			+
			+ In normal mode, the resolution of the digital output is selected using
			+ the RES0 and RES1 input pins. In configuration mode, the resolution is
			+ selected by setting the RES0 and RES1 bits in the control register.
			+
			+ RES1 RES0 Resolution (Bits)
			+ 0 0 10
			+ 0 1 12
			+ 1 0 14
			+ 1 1 16
			+
			+ Note on SPI connections: The CS line on the AD2S1210 should hard-wired to
			+ logic low and the WR/FSYNC line on the AD2S1210 should be connected to the
			+ SPI CSn output of the SPI controller.
			+
			+ Datasheet:
			+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad2s1210.pdf
			+
			+properties:
			+ compatible:
			+ const: adi,ad2s1210
			+
			+ reg:
			+ maxItems: 1
			+
			+ spi-max-frequency:
			+ maximum: 25000000
			+
			+ spi-cpha: true
			+
			+ avdd-supply:
			+ description:
			+ A 4.75 to 5.25 V regulator that powers the Analog Supply Voltage (AVDD)
			+ pin.
			+
			+ dvdd-supply:
			+ description:
			+ A 4.75 to 5.25 V regulator that powers the Digital Supply Voltage (DVDD)
			+ pin.
			+
			+ vdrive-supply:
			+ description:
			+ A 2.3 to 5.25 V regulator that powers the Logic Power Supply Input
			+ (VDrive) pin.
			+
			+ clocks:
			+ maxItems: 1
			+ description: External oscillator clock (CLKIN).
			+
			+ reset-gpios:
			+ description:
			+ GPIO connected to the /RESET pin. As the line needs to be low for the
			+ reset to be active, it should be configured as GPIO_ACTIVE_LOW.
			+ maxItems: 1
			+
			+ sample-gpios:
			+ description:
			+ GPIO connected to the /SAMPLE pin. As the line needs to be low to trigger
			+ a sample, it should be configured as GPIO_ACTIVE_LOW.
			+ maxItems: 1
			+
			+ mode-gpios:
			+ description:
			+ GPIO lines connected to the A0 and A1 pins. These pins select the data
			+ transfer mode.
			+ minItems: 2
			+ maxItems: 2
			+
			+ resolution-gpios:
			+ description:
			+ GPIO lines connected to the RES0 and RES1 pins. These pins select the
			+ resolution of the digital output. If omitted, it is assumed that the
			+ RES0 and RES1 pins are hard-wired to match the assigned-resolution-bits
			+ property.
			+ minItems: 2
			+ maxItems: 2
			+
			+ fault-gpios:
			+ description:
			+ GPIO lines connected to the LOT and DOS pins. These pins combined indicate
			+ the type of fault present, if any. As these pins a pulled low to indicate
			+ a fault condition, they should be configured as GPIO_ACTIVE_LOW.
			+ minItems: 2
			+ maxItems: 2
			+
			+ adi,fixed-mode:
			+ description:
			+ This is used to indicate the selected mode if A0 and A1 are hard-wired
			+ instead of connected to GPIOS (i.e. mode-gpios is omitted).
			+ $ref: /schemas/types.yaml#/definitions/string
			+ enum: [config, velocity, position]
			+
			+ assigned-resolution-bits:
			+ description:
			+ Resolution of the digital output required by the application. This
			+ determines the precision of the angle and/or the maximum speed that can
			+ be measured. If resolution-gpios is omitted, it is assumed that RES0 and
			+ RES1 are hard-wired to match this value.
			+ enum: [10, 12, 14, 16]
			+
			+required:
			+ - compatible
			+ - reg
			+ - spi-cpha
			+ - avdd-supply
			+ - dvdd-supply
			+ - vdrive-supply
			+ - clocks
			+ - sample-gpios
			+ - assigned-resolution-bits
			+
			+oneOf:
			+ - required:
			+ - mode-gpios
			+ - required:
			+ - adi,fixed-mode
			+
			+allOf:
			+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/gpio/gpio.h>
			+
			+ spi {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ resolver@0 {
			+ compatible = "adi,ad2s1210";
			+ reg = <0>;
			+ spi-max-frequency = <20000000>;
			+ spi-cpha;
			+ avdd-supply = <&avdd_regulator>;
			+ dvdd-supply = <&dvdd_regulator>;
			+ vdrive-supply = <&vdrive_regulator>;
			+ clocks = <&ext_osc>;
			+ sample-gpios = <&gpio0 90 GPIO_ACTIVE_LOW>;
			+ mode-gpios = <&gpio0 86 0>, <&gpio0 87 0>;
			+ resolution-gpios = <&gpio0 88 0>, <&gpio0 89 0>;
			+ assigned-resolution-bits = <16>;
			+ };
			+ };

    linux,keycodes:
      maxItems: 1
++  wakeup-source: true
++
  required:
    - compatible
    - linux,keycodes

sys/contrib/device-tree/Bindings/input/qcom,pm8921-keypad.yaml
@@ -0,0 +1,89 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/input/qcom,pm8921-keypad.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm PM8921 PMIC KeyPad
			+
			+maintainers:
			+ - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
			+
			+allOf:
			+ - $ref: input.yaml#
			+ - $ref: matrix-keymap.yaml#
			+
			+properties:
			+ compatible:
			+ enum:
			+ - qcom,pm8058-keypad
			+ - qcom,pm8921-keypad
			+
			+ reg:
			+ maxItems: 1
			+
			+ interrupts:
			+ items:
			+ - description: key sense
			+ - description: key stuck
			+
			+ wakeup-source:
			+ type: boolean
			+ description: use any event on keypad as wakeup event
			+
			+ linux,keypad-wakeup:
			+ type: boolean
			+ deprecated: true
			+ description: legacy version of the wakeup-source property
			+
			+ debounce:
			+ description:
			+ Time in microseconds that key must be pressed or
			+ released for state change interrupt to trigger.
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+
			+ scan-delay:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ description: time in microseconds to pause between successive scans of the
			+ matrix array
			+
			+ row-hold:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ description: time in nanoseconds to pause between scans of each row in the
			+ matrix array.
			+
			+required:
			+ - compatible
			+ - reg
			+ - interrupts
			+ - linux,keymap
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/input/input.h>
			+ #include <dt-bindings/interrupt-controller/irq.h>
			+ pmic {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ keypad@148 {
			+ compatible = "qcom,pm8921-keypad";
			+ reg = <0x148>;
			+ interrupt-parent = <&pmicintc>;
			+ interrupts = <74 IRQ_TYPE_EDGE_RISING>, <75 IRQ_TYPE_EDGE_RISING>;
			+ linux,keymap = <
			+ MATRIX_KEY(0, 0, KEY_VOLUMEUP)
			+ MATRIX_KEY(0, 1, KEY_VOLUMEDOWN)
			+ MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS)
			+ MATRIX_KEY(0, 3, KEY_CAMERA)
			+ >;
			+ keypad,num-rows = <1>;
			+ keypad,num-columns = <5>;
			+ debounce = <15>;
			+ scan-delay = <32>;
			+ row-hold = <91500>;
			+ };
			+ };
			+...

    "^rmi4-f[0-9a-f]+@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      description:
        Other functions, not documented yet.

    vdd-supply:
      description: Regulator for voltage.
++  vddio-supply:
++    description: Optional Regulator for I/O voltage.
++
    reset-gpios:
      maxItems: 1

  Texas Instruments TWL family (twl4030) pwrbutton module
  This module is part of the TWL4030. For more details about the whole
--chip see Documentation/devicetree/bindings/mfd/twl-family.txt.
++chip see Documentation/devicetree/bindings/mfd/ti,twl.yaml.
  This module provides a simple power button event via an Interrupt.

sys/contrib/device-tree/Bindings/interconnect/qcom,msm8939.yaml
@@ -0,0 +1,74 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/interconnect/qcom,msm8939.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm MSM8939 Network-On-Chip interconnect
			+
			+maintainers:
			+ - Konrad Dybcio <konradybcio@kernel.org>
			+
			+description: \|
			+ The Qualcomm MSM8939 interconnect providers support adjusting the
			+ bandwidth requirements between the various NoC fabrics.
			+
			+allOf:
			+ - $ref: qcom,rpm-common.yaml#
			+
			+properties:
			+ compatible:
			+ enum:
			+ - qcom,msm8939-bimc
			+ - qcom,msm8939-pcnoc
			+ - qcom,msm8939-snoc
			+
			+ reg:
			+ maxItems: 1
			+
			+patternProperties:
			+ '^interconnect-[a-z0-9\-]+$':
			+ type: object
			+ $ref: qcom,rpm-common.yaml#
			+ description:
			+ The interconnect providers do not have a separate QoS register space,
			+ but share parent's space.
			+
			+ allOf:
			+ - $ref: qcom,rpm-common.yaml#
			+
			+ properties:
			+ compatible:
			+ const: qcom,msm8939-snoc-mm
			+
			+ required:
			+ - compatible
			+
			+ unevaluatedProperties: false
			+
			+required:
			+ - compatible
			+ - reg
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/qcom,rpmcc.h>
			+
			+ snoc: interconnect@580000 {
			+ compatible = "qcom,msm8939-snoc";
			+ reg = <0x00580000 0x14000>;
			+ #interconnect-cells = <1>;
			+ };
			+
			+ bimc: interconnect@400000 {
			+ compatible = "qcom,msm8939-bimc";
			+ reg = <0x00400000 0x62000>;
			+ #interconnect-cells = <1>;
			+
			+ snoc_mm: interconnect-snoc {
			+ compatible = "qcom,msm8939-snoc-mm";
			+ #interconnect-cells = <1>;
			+ };
			+ };

sys/contrib/device-tree/Bindings/interconnect/qcom,msm8996.yaml
@@ -0,0 +1,126 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/interconnect/qcom,msm8996.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm MSM8996 Network-On-Chip interconnect
			+
			+maintainers:
			+ - Konrad Dybcio <konradybcio@kernel.org>
			+
			+description: \|
			+ The Qualcomm MSM8996 interconnect providers support adjusting the
			+ bandwidth requirements between the various NoC fabrics.
			+
			+properties:
			+ compatible:
			+ enum:
			+ - qcom,msm8996-a0noc
			+ - qcom,msm8996-a1noc
			+ - qcom,msm8996-a2noc
			+ - qcom,msm8996-bimc
			+ - qcom,msm8996-cnoc
			+ - qcom,msm8996-mnoc
			+ - qcom,msm8996-pnoc
			+ - qcom,msm8996-snoc
			+
			+ reg:
			+ maxItems: 1
			+
			+ clock-names:
			+ minItems: 1
			+ maxItems: 3
			+
			+ clocks:
			+ minItems: 1
			+ maxItems: 3
			+
			+ power-domains:
			+ maxItems: 1
			+
			+required:
			+ - compatible
			+ - reg
			+
			+unevaluatedProperties: false
			+
			+allOf:
			+ - $ref: qcom,rpm-common.yaml#
			+ - if:
			+ properties:
			+ compatible:
			+ const: qcom,msm8996-a0noc
			+
			+ then:
			+ properties:
			+ clocks:
			+ items:
			+ - description: Aggregate0 System NoC AXI Clock.
			+ - description: Aggregate0 Config NoC AHB Clock.
			+ - description: Aggregate0 NoC MPU Clock.
			+
			+ clock-names:
			+ items:
			+ - const: aggre0_snoc_axi
			+ - const: aggre0_cnoc_ahb
			+ - const: aggre0_noc_mpu_cfg
			+
			+ required:
			+ - power-domains
			+
			+ - if:
			+ properties:
			+ compatible:
			+ const: qcom,msm8996-mnoc
			+
			+ then:
			+ properties:
			+ clocks:
			+ items:
			+ - description: CPU-NoC High-performance Bus Clock.
			+
			+ clock-names:
			+ const: iface
			+
			+ - if:
			+ properties:
			+ compatible:
			+ const: qcom,msm8996-a2noc
			+
			+ then:
			+ properties:
			+ clocks:
			+ items:
			+ - description: Aggregate2 NoC UFS AXI Clock
			+ - description: UFS AXI Clock
			+
			+ clock-names:
			+ items:
			+ - const: aggre2_ufs_axi
			+ - const: ufs_axi
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/qcom,gcc-msm8996.h>
			+ #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
			+ #include <dt-bindings/clock/qcom,rpmcc.h>
			+
			+ bimc: interconnect@408000 {
			+ compatible = "qcom,msm8996-bimc";
			+ reg = <0x00408000 0x5a000>;
			+ #interconnect-cells = <1>;
			+ };
			+
			+ a0noc: interconnect@543000 {
			+ compatible = "qcom,msm8996-a0noc";
			+ reg = <0x00543000 0x6000>;
			+ #interconnect-cells = <1>;
			+ clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
			+ <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
			+ <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
			+ clock-names = "aggre0_snoc_axi",
			+ "aggre0_cnoc_ahb",
			+ "aggre0_noc_mpu_cfg";
			+ power-domains = <&gcc AGGRE0_NOC_GDSC>;
			+ };

sys/contrib/device-tree/Bindings/interconnect/qcom,qcm2290.yaml
@@ -13,6 +13,9 @@ description: \|
	The Qualcomm QCM2290 interconnect providers support adjusting the	The Qualcomm QCM2290 interconnect providers support adjusting the
	bandwidth requirements between the various NoC fabrics.	bandwidth requirements between the various NoC fabrics.

		+allOf:
		+ - $ref: qcom,rpm-common.yaml#
		+
	properties:	properties:
	reg:	reg:
	maxItems: 1	maxItems: 1
@@ -23,19 +26,6 @@ properties:
	- qcom,qcm2290-cnoc	- qcom,qcm2290-cnoc
	- qcom,qcm2290-snoc	- qcom,qcm2290-snoc

	- '#interconnect-cells':
	- const: 1
	-
	- clock-names:
	- items:
	- - const: bus
	- - const: bus_a
	-
	- clocks:
	- items:
	- - description: Bus Clock
	- - description: Bus A Clock
	-
	# Child node's properties	# Child node's properties
	patternProperties:	patternProperties:
	'^interconnect-[a-z0-9]+$':	'^interconnect-[a-z0-9]+$':
@@ -44,6 +34,9 @@ patternProperties:
	The interconnect providers do not have a separate QoS register space,	The interconnect providers do not have a separate QoS register space,
	but share parent's space.	but share parent's space.

		+ allOf:
		+ - $ref: qcom,rpm-common.yaml#
		+
	properties:	properties:
	compatible:	compatible:
	enum:	enum:
@@ -51,35 +44,16 @@ patternProperties:
	- qcom,qcm2290-mmrt-virt	- qcom,qcm2290-mmrt-virt
	- qcom,qcm2290-mmnrt-virt	- qcom,qcm2290-mmnrt-virt

	- '#interconnect-cells':
	- const: 1
	-
	- clock-names:
	- items:
	- - const: bus
	- - const: bus_a
	-
	- clocks:
	- items:
	- - description: Bus Clock
	- - description: Bus A Clock
	-
	required:	required:
	- compatible	- compatible
	- - '#interconnect-cells'
	- - clock-names
	- - clocks

	- ~~additionalProperties:~~ false	+ unevaluatedProperties: false

	required:	required:
	- compatible	- compatible
	- reg	- reg
	- - '#interconnect-cells'
	- - clock-names
	- - clocks

	-~~additionalProperties:~~ false	+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|
@@ -89,32 +63,20 @@ examples:
	compatible = "qcom,qcm2290-snoc";	compatible = "qcom,qcm2290-snoc";
	reg = <0x01880000 0x60200>;	reg = <0x01880000 0x60200>;
	#interconnect-cells = <1>;	#interconnect-cells = <1>;
	- clock-names = "bus", "bus_a";
	- clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
	- <&rpmcc RPM_SMD_SNOC_A_CLK>;

	qup_virt: interconnect-qup {	qup_virt: interconnect-qup {
	compatible = "qcom,qcm2290-qup-virt";	compatible = "qcom,qcm2290-qup-virt";
	#interconnect-cells = <1>;	#interconnect-cells = <1>;
	- clock-names = "bus", "bus_a";
	- clocks = <&rpmcc RPM_SMD_QUP_CLK>,
	- <&rpmcc RPM_SMD_QUP_A_CLK>;
	};	};

	mmnrt_virt: interconnect-mmnrt {	mmnrt_virt: interconnect-mmnrt {
	compatible = "qcom,qcm2290-mmnrt-virt";	compatible = "qcom,qcm2290-mmnrt-virt";
	#interconnect-cells = <1>;	#interconnect-cells = <1>;
	- clock-names = "bus", "bus_a";
	- clocks = <&rpmcc RPM_SMD_MMNRT_CLK>,
	- <&rpmcc RPM_SMD_MMNRT_A_CLK>;
	};	};

	mmrt_virt: interconnect-mmrt {	mmrt_virt: interconnect-mmrt {
	compatible = "qcom,qcm2290-mmrt-virt";	compatible = "qcom,qcm2290-mmrt-virt";
	#interconnect-cells = <1>;	#interconnect-cells = <1>;
	- clock-names = "bus", "bus_a";
	- clocks = <&rpmcc RPM_SMD_MMRT_CLK>,
	- <&rpmcc RPM_SMD_MMRT_A_CLK>;
	};	};
	};	};

@@ -122,16 +84,10 @@ examples:
	compatible = "qcom,qcm2290-cnoc";	compatible = "qcom,qcm2290-cnoc";
	reg = <0x01900000 0x8200>;	reg = <0x01900000 0x8200>;
	#interconnect-cells = <1>;	#interconnect-cells = <1>;
	- clock-names = "bus", "bus_a";
	- clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
	- <&rpmcc RPM_SMD_CNOC_A_CLK>;
	};	};

	bimc: interconnect@4480000 {	bimc: interconnect@4480000 {
	compatible = "qcom,qcm2290-bimc";	compatible = "qcom,qcm2290-bimc";
	reg = <0x04480000 0x80000>;	reg = <0x04480000 0x80000>;
	#interconnect-cells = <1>;	#interconnect-cells = <1>;
	- clock-names = "bus", "bus_a";
	- clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
	- <&rpmcc RPM_SMD_BIMC_A_CLK>;
	};	};

sys/contrib/device-tree/Bindings/interconnect/qcom,rpm-common.yaml
@@ -0,0 +1,28 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/interconnect/qcom,rpm-common.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm RPMh Network-On-Chip Interconnect
			+
			+maintainers:
			+ - Konrad Dybcio <konradybcio@kernel.org>
			+
			+description:
			+ RPM interconnect providers support for managing system bandwidth requirements
			+ through manual requests based on either predefined values or as indicated by
			+ the bus monitor hardware. Each provider node represents a NoC bus master,
			+ driven by a dedicated clock source.
			+
			+properties:
			+ '#interconnect-cells':
			+ oneOf:
			+ - const: 2
			+ - const: 1
			+ deprecated: true
			+
			+required:
			+ - '#interconnect-cells'
			+
			+additionalProperties: true

sys/contrib/device-tree/Bindings/interconnect/qcom,rpm.yaml
@@ -7,13 +7,16 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
	title: Qualcomm RPM Network-On-Chip Interconnect	title: Qualcomm RPM Network-On-Chip Interconnect

	maintainers:	maintainers:
	- - Georgi Djakov ~~<georgi~~.~~djakov@linaro.~~org>	+ - Georgi Djakov <djakov@kernel.org>

	description: \|	description: \|
	RPM interconnect providers support system bandwidth requirements through	RPM interconnect providers support system bandwidth requirements through
	RPM processor. The provider is able to communicate with the RPM through	RPM processor. The provider is able to communicate with the RPM through
	the RPM shared memory device.	the RPM shared memory device.

		+allOf:
		+ - $ref: qcom,rpm-common.yaml#
		+
	properties:	properties:
	reg:	reg:
	maxItems: 1	maxItems: 1
@@ -23,259 +26,22 @@ properties:
	- qcom,msm8916-bimc	- qcom,msm8916-bimc
	- qcom,msm8916-pcnoc	- qcom,msm8916-pcnoc
	- qcom,msm8916-snoc	- qcom,msm8916-snoc
	- - qcom,msm8939-bimc
	- - qcom,msm8939-pcnoc
	- - qcom,msm8939-snoc
	- - qcom,msm8996-a0noc
	- - qcom,msm8996-a1noc
	- - qcom,msm8996-a2noc
	- - qcom,msm8996-bimc
	- - qcom,msm8996-cnoc
	- - qcom,msm8996-mnoc
	- - qcom,msm8996-pnoc
	- - qcom,msm8996-snoc
	- qcom,qcs404-bimc	- qcom,qcs404-bimc
	- qcom,qcs404-pcnoc	- qcom,qcs404-pcnoc
	- qcom,qcs404-snoc	- qcom,qcs404-snoc
	- - qcom,sdm660-a2noc
	- - qcom,sdm660-bimc
	- - qcom,sdm660-cnoc
	- - qcom,sdm660-gnoc
	- - qcom,sdm660-mnoc
	- - qcom,sdm660-snoc
	-
	- '#interconnect-cells':
	- description: \|
	- Value: <1> is one cell in an interconnect specifier for the
	- interconnect node id, <2> requires the interconnect node id and an
	- extra path tag.
	- enum: [ 1, 2 ]
	-
	- clocks:
	- minItems: 2
	- maxItems: 7
	-
	- clock-names:
	- minItems: 2
	- maxItems: 7
	-
	- power-domains:
	- maxItems: 1
	-
	-# Child node's properties
	-patternProperties:
	- '^interconnect-[a-z0-9]+$':
	- type: object
	- additionalProperties: false
	- description:
	- snoc-mm is a child of snoc, sharing snoc's register address space.
	-
	- properties:
	- compatible:
	- enum:
	- - qcom,msm8939-snoc-mm
	-
	- '#interconnect-cells':
	- const: 1
	-
	- clock-names:
	- items:
	- - const: bus
	- - const: bus_a
	-
	- clocks:
	- items:
	- - description: Bus Clock
	- - description: Bus A Clock
	-
	- required:
	- - compatible
	- - '#interconnect-cells'
	- - clock-names
	- - clocks

	required:	required:
	- compatible	- compatible
	- reg	- reg
	- - '#interconnect-cells'
	- - clock-names
	- - clocks
	-
	-additionalProperties: false
	-
	-allOf:
	- - if:
	- properties:
	- compatible:
	- contains:
	- enum:
	- - qcom,msm8916-bimc
	- - qcom,msm8916-pcnoc
	- - qcom,msm8916-snoc
	- - qcom,msm8939-bimc
	- - qcom,msm8939-pcnoc
	- - qcom,msm8939-snoc
	- - qcom,msm8996-a1noc
	- - qcom,msm8996-bimc
	- - qcom,msm8996-cnoc
	- - qcom,msm8996-pnoc
	- - qcom,msm8996-snoc
	- - qcom,qcs404-bimc
	- - qcom,qcs404-pcnoc
	- - qcom,qcs404-snoc
	- - qcom,sdm660-bimc
	- - qcom,sdm660-cnoc
	- - qcom,sdm660-gnoc
	- - qcom,sdm660-snoc
	-
	- then:
	- properties:
	- clock-names:
	- items:
	- - const: bus
	- - const: bus_a
	-
	- clocks:
	- items:
	- - description: Bus Clock
	- - description: Bus A Clock

	- - if:	+unevaluatedProperties: false
	- properties:
	- compatible:
	- contains:
	- enum:
	- - qcom,msm8996-mnoc
	- - qcom,sdm660-mnoc
	-
	- then:
	- properties:
	- clock-names:
	- items:
	- - const: bus
	- - const: bus_a
	- - const: iface
	-
	- clocks:
	- items:
	- - description: Bus Clock.
	- - description: Bus A Clock.
	- - description: CPU-NoC High-performance Bus Clock.
	-
	- - if:
	- properties:
	- compatible:
	- contains:
	- enum:
	- - qcom,msm8996-a0noc
	-
	- then:
	- properties:
	- clock-names:
	- items:
	- - const: aggre0_snoc_axi
	- - const: aggre0_cnoc_ahb
	- - const: aggre0_noc_mpu_cfg
	-
	- clocks:
	- items:
	- - description: Aggregate0 System NoC AXI Clock.
	- - description: Aggregate0 Config NoC AHB Clock.
	- - description: Aggregate0 NoC MPU Clock.
	-
	- required:
	- - power-domains
	-
	- - if:
	- properties:
	- compatible:
	- contains:
	- enum:
	- - qcom,msm8996-a2noc
	-
	- then:
	- properties:
	- clock-names:
	- items:
	- - const: bus
	- - const: bus_a
	- - const: aggre2_ufs_axi
	- - const: ufs_axi
	-
	- clocks:
	- items:
	- - description: Bus Clock
	- - description: Bus A Clock
	- - description: Aggregate2 NoC UFS AXI Clock
	- - description: UFS AXI Clock
	-
	- - if:
	- properties:
	- compatible:
	- contains:
	- enum:
	- - qcom,sdm660-a2noc
	-
	- then:
	- properties:
	- clock-names:
	- items:
	- - const: bus
	- - const: bus_a
	- - const: ipa
	- - const: ufs_axi
	- - const: aggre2_ufs_axi
	- - const: aggre2_usb3_axi
	- - const: cfg_noc_usb2_axi
	-
	- clocks:
	- items:
	- - description: Bus Clock.
	- - description: Bus A Clock.
	- - description: IPA Clock.
	- - description: UFS AXI Clock.
	- - description: Aggregate2 UFS AXI Clock.
	- - description: Aggregate2 USB3 AXI Clock.
	- - description: Config NoC USB2 AXI Clock.
	-
	- - if:
	- not:
	- properties:
	- compatible:
	- contains:
	- enum:
	- - qcom,msm8939-snoc
	- then:
	- patternProperties:
	- '^interconnect-[a-z0-9]+$': false

	examples:	examples:
	- \|	- \|
	#include <dt-bindings/clock/qcom,rpmcc.h>	#include <dt-bindings/clock/qcom,rpmcc.h>

	bimc: interconnect@400000 {	bimc: interconnect@400000 {
	- compatible = "qcom,msm8916-bimc";	+ compatible = "qcom,msm8916-bimc";
	- reg = <0x00400000 0x62000>;	+ reg = <0x00400000 0x62000>;
	- #interconnect-cells = <1>;	+ #interconnect-cells = <1>;
	- clock-names = "bus", "bus_a";
	- clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
	- <&rpmcc RPM_SMD_BIMC_A_CLK>;
	- };
	-
	- pcnoc: interconnect@500000 {
	- compatible = "qcom,msm8916-pcnoc";
	- reg = <0x00500000 0x11000>;
	- #interconnect-cells = <1>;
	- clock-names = "bus", "bus_a";
	- clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
	- <&rpmcc RPM_SMD_PCNOC_A_CLK>;
	- };
	-
	- snoc: interconnect@580000 {
	- compatible = "qcom,msm8916-snoc";
	- reg = <0x00580000 0x14000>;
	- #interconnect-cells = <1>;
	- clock-names = "bus", "bus_a";
	- clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
	- <&rpmcc RPM_SMD_SNOC_A_CLK>;
	};	};

          properties:
            compatible:
              enum:
++              - qcom,sdx65-mc-virt
                - qcom,sm8250-qup-virt
      then:
        required:

sys/contrib/device-tree/Bindings/interconnect/qcom,sdm660.yaml
@@ -7,16 +7,13 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
	title: Qualcomm SDM660 Network-On-Chip interconnect	title: Qualcomm SDM660 Network-On-Chip interconnect

	maintainers:	maintainers:
	- - AngeloGioacchino Del Regno <kholk11@gmail.com>	+ - Konrad Dybcio <konradybcio@kernel.org>

	description: \|	description: \|
	The Qualcomm SDM660 interconnect providers support adjusting the	The Qualcomm SDM660 interconnect providers support adjusting the
	bandwidth requirements between the various NoC fabrics.	bandwidth requirements between the various NoC fabrics.

	properties:	properties:
	- reg:
	- maxItems: 1
	-
	compatible:	compatible:
	enum:	enum:
	- qcom,sdm660-a2noc	- qcom,sdm660-a2noc
@@ -26,160 +23,86 @@ properties:
	- qcom,sdm660-mnoc	- qcom,sdm660-mnoc
	- qcom,sdm660-snoc	- qcom,sdm660-snoc

	- '#interconnect-cells':	+ reg:
	- ~~const:~~ 1	+ maxItems: 1

	- ~~clocks:~~	+ clock-names:
	minItems: 1	minItems: 1
	- maxItems: 7	+ maxItems: 5

	- ~~clock-names:~~	+ clocks:
	minItems: 1	minItems: 1
	- maxItems: 7	+ maxItems: 5

	required:	required:
	- compatible	- compatible
	- reg	- reg
	- - '#interconnect-cells'
	- - clock-names
	- - clocks

	-~~additionalProperties:~~ false	+unevaluatedProperties: false

	allOf:	allOf:
		+ - $ref: qcom,rpm-common.yaml#
	- if:	- if:
	properties:	properties:
	compatible:	compatible:
	- ~~contains:~~	+ const: qcom,sdm660-mnoc
	- enum:	+
	- - qcom,sdm660-mnoc
	then:	then:
	properties:	properties:
	clocks:	clocks:
	items:	items:
	- - description: Bus Clock.
	- - description: Bus A Clock.
	- description: CPU-NoC High-performance Bus Clock.	- description: CPU-NoC High-performance Bus Clock.
		+
	clock-names:	clock-names:
	- ~~items:~~	+ const: iface
	- - const: bus
	- - const: bus_a
	- - const: iface

	- if:	- if:
	properties:	properties:
	compatible:	compatible:
	- ~~contains:~~	+ const: qcom,sdm660-a2noc
	- enum:	+
	- - qcom,sdm660-a2noc
	then:	then:
	properties:	properties:
	clocks:	clocks:
	items:	items:
	- - description: Bus Clock.
	- - description: Bus A Clock.
	- description: IPA Clock.	- description: IPA Clock.
	- description: UFS AXI Clock.	- description: UFS AXI Clock.
	- description: Aggregate2 UFS AXI Clock.	- description: Aggregate2 UFS AXI Clock.
	- description: Aggregate2 USB3 AXI Clock.	- description: Aggregate2 USB3 AXI Clock.
	- description: Config NoC USB2 AXI Clock.	- description: Config NoC USB2 AXI Clock.
		+
	clock-names:	clock-names:
	items:	items:
	- - const: bus
	- - const: bus_a
	- const: ipa	- const: ipa
	- const: ufs_axi	- const: ufs_axi
	- const: aggre2_ufs_axi	- const: aggre2_ufs_axi
	- const: aggre2_usb3_axi	- const: aggre2_usb3_axi
	- const: cfg_noc_usb2_axi	- const: cfg_noc_usb2_axi

	- - if:
	- properties:
	- compatible:
	- contains:
	- enum:
	- - qcom,sdm660-bimc
	- - qcom,sdm660-cnoc
	- - qcom,sdm660-gnoc
	- - qcom,sdm660-snoc
	- then:
	- properties:
	- clocks:
	- items:
	- - description: Bus Clock.
	- - description: Bus A Clock.
	- clock-names:
	- items:
	- - const: bus
	- - const: bus_a
	-
	examples:	examples:
	- \|	- \|
	- #include <dt-bindings/clock/qcom,~~rpmcc~~.h>	+ #include <dt-bindings/clock/qcom,gcc-sdm660.h>
	- #include <dt-bindings/clock/qcom,mmcc-sdm660.h>	+ #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
	- #include <dt-bindings/clock/qcom,~~gcc-sdm660~~.h>	+ #include <dt-bindings/clock/qcom,rpmcc.h>
	-	+
	- bimc: interconnect@1008000 {	+ bimc: interconnect@1008000 {
	- compatible = "qcom,sdm660-bimc";	+ compatible = "qcom,sdm660-bimc";
	- reg = <0x01008000 0x78000>;	+ reg = <0x01008000 0x78000>;
	- #interconnect-cells = <1>;	+ #interconnect-cells = <1>;
	- clock-names = "bus", "bus_a";	+ };
	- clocks = <&rpmcc RPM_SMD_BIMC_CLK>,	+
	- <&rpmcc RPM_SMD_BIMC_A_CLK>;	+ a2noc: interconnect@1704000 {
	- };	+ compatible = "qcom,sdm660-a2noc";
	-	+ reg = <0x01704000 0xc100>;
	- cnoc: interconnect@1500000 {	+ #interconnect-cells = <1>;
	- compatible = "qcom,sdm660-cnoc";	+ clocks = <&rpmcc RPM_SMD_IPA_CLK>,
	- reg = <0x01500000 0x10000>;	+ <&gcc GCC_UFS_AXI_CLK>,
	- #interconnect-cells = <1>;	+ <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
	- clock-names = "bus", "bus_a";	+ <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
	- ~~clocks~~ ~~= <&rpmcc RPM_SMD_CNOC_CLK>,~~	+ <&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
	- <&rpmcc RPM_SMD_CNOC_A_CLK>;	+ clock-names = "ipa",
	- };	+ "ufs_axi",
	-	+ "aggre2_ufs_axi",
	- snoc: interconnect@1626000 {	+ "aggre2_usb3_axi",
	- compatible = "qcom,sdm660-snoc";	+ "cfg_noc_usb2_axi";
	- reg = <0x01626000 0x7090>;	+ };
	- #interconnect-cells = <1>;
	- clock-names = "bus", "bus_a";
	- clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
	- <&rpmcc RPM_SMD_SNOC_A_CLK>;
	- };
	-
	- a2noc: interconnect@1704000 {
	- compatible = "qcom,sdm660-a2noc";
	- reg = <0x01704000 0xc100>;
	- #interconnect-cells = <1>;
	- clock-names = "bus",
	- "bus_a",
	- "ipa",
	- "ufs_axi",
	- "aggre2_ufs_axi",
	- "aggre2_usb3_axi",
	- "cfg_noc_usb2_axi";
	- clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
	- <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
	- <&rpmcc RPM_SMD_IPA_CLK>,
	- <&gcc GCC_UFS_AXI_CLK>,
	- <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
	- <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
	- <&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
	- };
	-
	- mnoc: interconnect@1745000 {
	- compatible = "qcom,sdm660-mnoc";
	- reg = <0x01745000 0xa010>;
	- #interconnect-cells = <1>;
	- clock-names = "bus", "bus_a", "iface";
	- clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
	- <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
	- <&mmcc AHB_CLK_SRC>;
	- };
	-
	- gnoc: interconnect@17900000 {
	- compatible = "qcom,sdm660-gnoc";
	- reg = <0x17900000 0xe000>;
	- #interconnect-cells = <1>;
	- clock-names = "bus", "bus_a";
	- clocks = <&xo_board>, <&xo_board>;
	- };

sys/contrib/device-tree/Bindings/interconnect/qcom,sdx75-rpmh.yaml
@@ -0,0 +1,92 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/interconnect/qcom,sdx75-rpmh.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm RPMh Network-On-Chip Interconnect on SDX75
			+
			+maintainers:
			+ - Rohit Agarwal <quic_rohiagar@quicinc.com>
			+
			+description:
			+ RPMh interconnect providers support system bandwidth requirements through
			+ RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
			+ able to communicate with the BCM through the Resource State Coordinator (RSC)
			+ associated with each execution environment. Provider nodes must point to at
			+ least one RPMh device child node pertaining to their RSC and each provider
			+ can map to multiple RPMh resources.
			+
			+properties:
			+ compatible:
			+ enum:
			+ - qcom,sdx75-clk-virt
			+ - qcom,sdx75-dc-noc
			+ - qcom,sdx75-gem-noc
			+ - qcom,sdx75-mc-virt
			+ - qcom,sdx75-pcie-anoc
			+ - qcom,sdx75-system-noc
			+
			+ '#interconnect-cells': true
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ maxItems: 1
			+
			+required:
			+ - compatible
			+
			+allOf:
			+ - $ref: qcom,rpmh-common.yaml#
			+ - if:
			+ properties:
			+ compatible:
			+ contains:
			+ enum:
			+ - qcom,sdx75-clk-virt
			+ - qcom,sdx75-mc-virt
			+ then:
			+ properties:
			+ reg: false
			+ else:
			+ required:
			+ - reg
			+
			+ - if:
			+ properties:
			+ compatible:
			+ contains:
			+ enum:
			+ - qcom,sdx75-clk-virt
			+ then:
			+ properties:
			+ clocks:
			+ items:
			+ - description: RPMH CC QPIC Clock
			+ required:
			+ - clocks
			+ else:
			+ properties:
			+ clocks: false
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/qcom,rpmh.h>
			+
			+ clk_virt: interconnect-0 {
			+ compatible = "qcom,sdx75-clk-virt";
			+ #interconnect-cells = <2>;
			+ qcom,bcm-voters = <&apps_bcm_voter>;
			+ clocks = <&rpmhcc RPMH_QPIC_CLK>;
			+ };
			+
			+ system_noc: interconnect@1640000 {
			+ compatible = "qcom,sdx75-system-noc";
			+ reg = <0x1640000 0x4b400>;
			+ #interconnect-cells = <2>;
			+ qcom,bcm-voters = <&apps_bcm_voter>;
			+ };

          - description: MPM pin number
          - description: GIC SPI number for the MPM pin
++  '#power-domain-cells':
++    const: 0
++
  required:
    - compatible
    - reg
                             <86 183>,
                             <90 260>,
                             <91 260>;
++        #power-domain-cells = <0>;
      };

            - qcom,sdm845-pdc
            - qcom,sdx55-pdc
            - qcom,sdx65-pdc
++          - qcom,sm4450-pdc
            - qcom,sm6350-pdc
            - qcom,sm8150-pdc
            - qcom,sm8250-pdc

        - items:
            - enum:
                - allwinner,sun20i-d1-plic
++              - sophgo,cv1800b-plic
++              - sophgo,sg2042-plic
                - thead,th1520-plic
            - const: thead,c900-plic
        - items:

sys/contrib/device-tree/Bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
@@ -0,0 +1,43 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
			+
			+maintainers:
			+ - Inochi Amaoto <inochiama@outlook.com>
			+
			+properties:
			+ compatible:
			+ items:
			+ - enum:
			+ - sophgo,sg2042-aclint-mswi
			+ - const: thead,c900-aclint-mswi
			+
			+ reg:
			+ maxItems: 1
			+
			+ interrupts-extended:
			+ minItems: 1
			+ maxItems: 4095
			+
			+additionalProperties: false
			+
			+required:
			+ - compatible
			+ - reg
			+ - interrupts-extended
			+
			+examples:
			+ - \|
			+ interrupt-controller@94000000 {
			+ compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
			+ interrupts-extended = <&cpu1intc 3>,
			+ <&cpu2intc 3>,
			+ <&cpu3intc 3>,
			+ <&cpu4intc 3>;
			+ reg = <0x94000000 0x00010000>;
			+ };
			+...

                - qcom,sdm630-smmu-v2
                - qcom,sdm845-smmu-v2
                - qcom,sm6350-smmu-v2
++              - qcom,sm7150-smmu-v2
            - const: qcom,adreno-smmu
            - const: qcom,smmu-v2
        - description: Qcom Adreno GPUs on Google Cheza platform
            contains:
              enum:
                - qcom,sm6350-smmu-v2
++              - qcom,sm7150-smmu-v2
                - qcom,sm8150-smmu-500
                - qcom,sm8250-smmu-500
      then:

sys/contrib/device-tree/Bindings/leds/backlight/common.yaml
@@ -33,4 +33,21 @@ properties:
	due to restrictions in a specific system, such as mounting conditions.	due to restrictions in a specific system, such as mounting conditions.
	$ref: /schemas/types.yaml#/definitions/uint32	$ref: /schemas/types.yaml#/definitions/uint32

		+ brightness-levels:
		+ description:
		+ Array of distinct brightness levels. The levels must be in the range
		+ accepted by the underlying LED device. Typically these are in the range
		+ from 0 to 255, but any range starting at 0 will do, as long as they are
		+ accepted by the LED.
		+ The 0 value means a 0% of brightness (darkest/off), while the last value
		+ in the array represents a full 100% brightness (brightest).
		+ If this array is not provided, the driver default mapping is used.
		+ $ref: /schemas/types.yaml#/definitions/uint32-array
		+
		+ default-brightness-level:
		+ description:
		+ The default brightness level (index into the array defined by the
		+ "brightness-levels" property).
		+ $ref: /schemas/types.yaml#/definitions/uint32
		+
	additionalProperties: true	additionalProperties: true

sys/contrib/device-tree/Bindings/leds/backlight/led-backlight.yaml
@@ -16,6 +16,9 @@ description:
	can also be used to describe a backlight device controlled by the output of	can also be used to describe a backlight device controlled by the output of
	a LED driver.	a LED driver.

		+allOf:
		+ - $ref: common.yaml#
		+
	properties:	properties:
	compatible:	compatible:
	const: led-backlight	const: led-backlight
@@ -26,25 +29,11 @@ properties:
	items:	items:
	maxItems: 1	maxItems: 1

	- brightness-levels:
	- description:
	- Array of distinct brightness levels. The levels must be in the range
	- accepted by the underlying LED devices. This is used to translate a
	- backlight brightness level into a LED brightness level. If it is not
	- provided, the identity mapping is used.
	- $ref: /schemas/types.yaml#/definitions/uint32-array
	-
	- default-brightness-level:
	- description:
	- The default brightness level (index into the array defined by the
	- "brightness-levels" property).
	- $ref: /schemas/types.yaml#/definitions/uint32
	-
	required:	required:
	- compatible	- compatible
	- leds	- leds

	-~~additionalProperties:~~ false	+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

sys/contrib/device-tree/Bindings/leds/backlight/mps,mp3309c.yaml
@@ -0,0 +1,73 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/leds/backlight/mps,mp3309c.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MPS MP3309C backlight
			+
			+maintainers:
			+ - Flavio Suligoi <f.suligoi@asem.it>
			+
			+description: \|
			+ The Monolithic Power (MPS) MP3309C is a WLED step-up converter, featuring a
			+ programmable switching frequency to optimize efficiency.
			+ It supports two different dimming modes:
			+
			+ - analog mode, via I2C commands (default)
			+ - PWM controlled mode.
			+
			+ The datasheet is available at:
			+ https://www.monolithicpower.com/en/mp3309c.html
			+
			+allOf:
			+ - $ref: common.yaml#
			+
			+properties:
			+ compatible:
			+ const: mps,mp3309c
			+
			+ reg:
			+ maxItems: 1
			+
			+ pwms:
			+ description: if present, the backlight is controlled in PWM mode.
			+ maxItems: 1
			+
			+ enable-gpios:
			+ description: GPIO used to enable the backlight in "analog-i2c" dimming mode.
			+ maxItems: 1
			+
			+ mps,overvoltage-protection-microvolt:
			+ description: Overvoltage protection (13.5V, 24V or 35.5V).
			+ enum: [ 13500000, 24000000, 35500000 ]
			+ default: 35500000
			+
			+ mps,no-sync-mode:
			+ description: disable synchronous rectification mode
			+ type: boolean
			+
			+required:
			+ - compatible
			+ - reg
			+ - max-brightness
			+ - default-brightness
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ /* Backlight with PWM control */
			+ backlight_pwm: backlight@17 {
			+ compatible = "mps,mp3309c";
			+ reg = <0x17>;
			+ pwms = <&pwm1 0 3333333 0>; /* 300 Hz --> (1/f) * 110^9 /
			+ max-brightness = <100>;
			+ default-brightness = <80>;
			+ mps,overvoltage-protection-microvolt = <24000000>;
			+ };
			+ };

sys/contrib/device-tree/Bindings/leds/backlight/pwm-backlight.yaml
@@ -11,6 +11,9 @@ maintainers:
	- Daniel Thompson <daniel.thompson@linaro.org>	- Daniel Thompson <daniel.thompson@linaro.org>
	- Jingoo Han <jingoohan1@gmail.com>	- Jingoo Han <jingoohan1@gmail.com>

		+allOf:
		+ - $ref: common.yaml#
		+
	properties:	properties:
	compatible:	compatible:
	const: pwm-backlight	const: pwm-backlight
@@ -39,21 +42,6 @@ properties:
	Delay in ms between disabling the backlight using GPIO and setting PWM	Delay in ms between disabling the backlight using GPIO and setting PWM
	value to 0.	value to 0.

	- brightness-levels:
	- description:
	- Array of distinct brightness levels. Typically these are in the range
	- from 0 to 255, but any range starting at 0 will do. The actual brightness
	- level (PWM duty cycle) will be interpolated from these values. 0 means a
	- 0% duty cycle (darkest/off), while the last value in the array represents
	- a 100% duty cycle (brightest).
	- $ref: /schemas/types.yaml#/definitions/uint32-array
	-
	- default-brightness-level:
	- description:
	- The default brightness level (index into the array defined by the
	- "brightness-levels" property).
	- $ref: /schemas/types.yaml#/definitions/uint32
	-
	num-interpolated-steps:	num-interpolated-steps:
	description:	description:
	Number of interpolated steps between each value of brightness-levels	Number of interpolated steps between each value of brightness-levels
@@ -69,7 +57,7 @@ required:
	- compatible	- compatible
	- pwms	- pwms

	-~~additionalProperties:~~ false	+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

        LED_COLOR_ID available, add a new one.
      $ref: /schemas/types.yaml#/definitions/uint32
      minimum: 0
--    maximum: 9
++    maximum: 14
    function-enumerator:
      description:
        each of them having its own LED assigned (assuming they are not
        hardwired). In such cases this property should contain phandle(s) of
        related source device(s).
++      Another example is a GPIO line that will be monitored and mirror the
++      state of the line (with or without inversion flags) to the LED.
        In many cases LED can be related to more than one device (e.g. one USB LED
        vs. multiple USB ports). Each source should be represented by a node in
        the device tree and be referenced by a phandle and a set of phandle

sys/contrib/device-tree/Bindings/leds/irled/pwm-ir-tx.yaml
@@ -15,7 +15,10 @@ description:

	properties:	properties:
	compatible:	compatible:
	- const: pwm-ir-tx	+ oneOf:
		+ - const: pwm-ir-tx
		+ - const: nokia,n900-ir
		+ deprecated: true

	pwms:	pwms:
	maxItems: 1	maxItems: 1

sys/contrib/device-tree/Bindings/leds/kinetic,ktd202x.yaml
@@ -0,0 +1,171 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/leds/kinetic,ktd202x.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Kinetic KTD2026/7 RGB/White LED Driver
			+
			+maintainers:
			+ - André Apitzsch <git@apitzsch.eu>
			+
			+description: \|
			+ The KTD2026/7 is a RGB/White LED driver with I2C interface.
			+
			+ The data sheet can be found at:
			+ https://www.kinet-ic.com/uploads/KTD2026-7-04h.pdf
			+
			+properties:
			+ compatible:
			+ enum:
			+ - kinetic,ktd2026
			+ - kinetic,ktd2027
			+
			+ reg:
			+ maxItems: 1
			+
			+ vin-supply:
			+ description: Regulator providing power to the "VIN" pin.
			+
			+ vio-supply:
			+ description: Regulator providing power for pull-up of the I/O lines.
			+ Note that this regulator does not directly connect to KTD2026, but is
			+ needed for the correct operation of the status ("ST") and I2C lines.
			+
			+ "#address-cells":
			+ const: 1
			+
			+ "#size-cells":
			+ const: 0
			+
			+ multi-led:
			+ type: object
			+ $ref: leds-class-multicolor.yaml#
			+ unevaluatedProperties: false
			+
			+ properties:
			+ "#address-cells":
			+ const: 1
			+
			+ "#size-cells":
			+ const: 0
			+
			+ patternProperties:
			+ "^led@[0-3]$":
			+ type: object
			+ $ref: common.yaml#
			+ unevaluatedProperties: false
			+
			+ properties:
			+ reg:
			+ description: Index of the LED.
			+ minimum: 0
			+ maximum: 3
			+
			+ required:
			+ - reg
			+ - color
			+
			+ required:
			+ - "#address-cells"
			+ - "#size-cells"
			+
			+patternProperties:
			+ "^led@[0-3]$":
			+ type: object
			+ $ref: common.yaml#
			+ unevaluatedProperties: false
			+
			+ properties:
			+ reg:
			+ description: Index of the LED.
			+ minimum: 0
			+ maximum: 3
			+
			+ required:
			+ - reg
			+
			+required:
			+ - compatible
			+ - reg
			+ - "#address-cells"
			+ - "#size-cells"
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/leds/common.h>
			+
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ led-controller@30 {
			+ compatible = "kinetic,ktd2026";
			+ reg = <0x30>;
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ vin-supply = <&pm8916_l17>;
			+ vio-supply = <&pm8916_l6>;
			+
			+ led@0 {
			+ reg = <0>;
			+ function = LED_FUNCTION_STATUS;
			+ color = <LED_COLOR_ID_RED>;
			+ };
			+
			+ led@1 {
			+ reg = <1>;
			+ function = LED_FUNCTION_STATUS;
			+ color = <LED_COLOR_ID_GREEN>;
			+ };
			+
			+ led@2 {
			+ reg = <2>;
			+ function = LED_FUNCTION_STATUS;
			+ color = <LED_COLOR_ID_BLUE>;
			+ };
			+ };
			+ };
			+ - \|
			+ #include <dt-bindings/leds/common.h>
			+
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ led-controller@30 {
			+ compatible = "kinetic,ktd2026";
			+ reg = <0x30>;
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ vin-supply = <&pm8916_l17>;
			+ vio-supply = <&pm8916_l6>;
			+
			+ multi-led {
			+ color = <LED_COLOR_ID_RGB>;
			+ function = LED_FUNCTION_STATUS;
			+
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ led@0 {
			+ reg = <0>;
			+ color = <LED_COLOR_ID_RED>;
			+ };
			+
			+ led@1 {
			+ reg = <1>;
			+ color = <LED_COLOR_ID_GREEN>;
			+ };
			+
			+ led@2 {
			+ reg = <2>;
			+ color = <LED_COLOR_ID_BLUE>;
			+ };
			+ };
			+ };
			+ };

    - |
      syscon@10000000 {
--        compatible = "arm,realview-pb1176-syscon", "syscon";
++        compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd";
          reg = <0x10000000 0x1000>;
          #address-cells = <1>;
          #size-cells = <1>;

        type      : Channel type
        channel   : Channel number
--      This MU support 5 type of unidirectional channels, each type
++      This MU support 6 type of unidirectional channels, each type
        has 4 channels except RST channel which only has 1 channel.
--      A total of 17 channels.  Following types are
++      A total of 21 channels.  Following types are
        supported:
 - TX channel with 32bit transmit register and IRQ transmit
            acknowledgment support.
 - TX doorbell channel. Without own register and no ACK support.
 - RX doorbell channel.
 - RST channel
++      5 - Tx doorbell channel. With S/W ACK from the other side.
      const: 2
    clocks:

            items:
              - description: primary pll parent of the clock driver
              - description: XO clock
++            - description: GCC GPLL0 clock source
          clock-names:
            items:
              - const: pll
              - const: xo
++            - const: gpll0
    - if:
        properties:

            - qcom,sm8350-ipcc
            - qcom,sm8450-ipcc
            - qcom,sm8550-ipcc
++          - qcom,sm8650-ipcc
        - const: qcom,ipcc
    reg:

      type: object  # DT nodes are json objects
      additionalProperties: false
      properties:
++
++      compatible:
++        const: xlnx,zynqmp-ipi-dest-mailbox
++
        xlnx,ipi-id:
          description:
            Remote Xilinx IPI agent ID of which the mailbox is connected to.
            - const: remote_response_region
      required:
++      - compatible
        - reg
        - reg-names
        - "#mbox-cells"
          ranges;
          mailbox: mailbox@ff9905c0 {
++          compatible = "xlnx,zynqmp-ipi-dest-mailbox";
            reg = <0x0 0xff9905c0 0x0 0x20>,
                  <0x0 0xff9905e0 0x0 0x20>,
                  <0x0 0xff990e80 0x0 0x20>,

            - amlogic,meson6-ir
            - amlogic,meson8b-ir
            - amlogic,meson-gxbb-ir
++          - amlogic,meson-s4-ir
        - items:
            - const: amlogic,meson-gx-ir
            - const: amlogic,meson-gxbb-ir

      items:
        - enum:
            - starfive,jh7110-csi2rx
++          - ti,j721e-csi2rx
        - const: cdns,csi2rx
    reg:

    interface and CCI (I2C compatible) control bus. The output format
    is raw Bayer.
++allOf:
++  - $ref: /schemas/media/video-interface-devices.yaml#
++
  properties:
    compatible:
      const: hynix,hi846
    - vddd-supply
    - port
--additionalProperties: false
++unevaluatedProperties: false
  examples:
    - |
              vddio-supply = <&reg_camera_vddio>;
              reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
              shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
++            orientation = <0>;
++            rotation = <0>;
              port {
                  camera_out: endpoint {

sys/contrib/device-tree/Bindings/media/i2c/onnn,mt9m114.yaml
@@ -0,0 +1,114 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/media/i2c/onnn,mt9m114.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: onsemi 1/6-inch 720p CMOS Digital Image Sensor
			+
			+maintainers:
			+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
			+
			+description: \|-
			+ The onsemi MT9M114 is a 1/6-inch 720p (1.26 Mp) CMOS digital image sensor
			+ with an active pixel-array size of 1296H x 976V. It is programmable through
			+ an I2C interface and outputs image data over a 8-bit parallel or 1-lane MIPI
			+ CSI-2 connection.
			+
			+properties:
			+ compatible:
			+ const: onnn,mt9m114
			+
			+ reg:
			+ description: I2C device address
			+ enum:
			+ - 0x48
			+ - 0x5d
			+
			+ clocks:
			+ description: EXTCLK clock signal
			+ maxItems: 1
			+
			+ vdd-supply:
			+ description:
			+ Core digital voltage supply, 1.8V
			+
			+ vddio-supply:
			+ description:
			+ I/O digital voltage supply, 1.8V or 2.8V
			+
			+ vaa-supply:
			+ description:
			+ Analog voltage supply, 2.8V
			+
			+ reset-gpios:
			+ description: \|-
			+ Reference to the GPIO connected to the RESET_BAR pin, if any (active
			+ low).
			+
			+ port:
			+ $ref: /schemas/graph.yaml#/$defs/port-base
			+ additionalProperties: false
			+
			+ properties:
			+ endpoint:
			+ $ref: /schemas/media/video-interfaces.yaml#
			+ additionalProperties: false
			+
			+ properties:
			+ bus-type:
			+ enum: [4, 5, 6]
			+
			+ link-frequencies: true
			+ remote-endpoint: true
			+
			+ # The number and mapping of lanes (for CSI-2), and the bus width and
			+ # signal polarities (for parallel and BT.656) are fixed and must not
			+ # be specified.
			+
			+ required:
			+ - bus-type
			+ - link-frequencies
			+
			+required:
			+ - compatible
			+ - reg
			+ - clocks
			+ - vdd-supply
			+ - vddio-supply
			+ - vaa-supply
			+ - port
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/gpio/gpio.h>
			+ #include <dt-bindings/media/video-interfaces.h>
			+
			+ i2c0 {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ sensor@48 {
			+ compatible = "onnn,mt9m114";
			+ reg = <0x48>;
			+
			+ clocks = <&clk24m 0>;
			+
			+ reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
			+
			+ vddio-supply = <&reg_cam_1v8>;
			+ vdd-supply = <&reg_cam_1v8>;
			+ vaa-supply = <&reg_2p8v>;
			+
			+ port {
			+ endpoint {
			+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
			+ link-frequencies = /bits/ 64 <384000000>;
			+ remote-endpoint = <&mipi_csi_in>;
			+ };
			+ };
			+ };
			+ };
			+...

        marked GPIO_ACTIVE_LOW.
      maxItems: 1
--  rotation:
--    enum:
--      - 0    # Sensor Mounted Upright
--      - 180  # Sensor Mounted Upside Down
--    default: 0
    port:
      $ref: /schemas/graph.yaml#/$defs/port-base
      additionalProperties: false
    - reset-gpios
    - port
--additionalProperties: false
++unevaluatedProperties: false
  examples:
    - |

      description:
        GPIO connected to the reset pin (active low)
--  orientation: true
--  rotation: true
    port:
      $ref: /schemas/graph.yaml#/$defs/port-base
      additionalProperties: false
    - dvdd-supply
    - port
--additionalProperties: false
++unevaluatedProperties: false
  examples:
    - |

      description: >
        Reference to the GPIO connected to the reset pin, if any.
--  rotation:
--    enum:
--      - 0
--      - 180
    port:
      description: Digital Output Port
      $ref: /schemas/graph.yaml#/$defs/port-base
    - DOVDD-supply
    - port
--additionalProperties: false
++unevaluatedProperties: false
  examples:
    - |

sys/contrib/device-tree/Bindings/media/i2c/ovti,ov5642.yaml
@@ -0,0 +1,141 @@
			+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/media/i2c/ovti,ov5642.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: OmniVision OV5642 Image Sensor
			+
			+maintainers:
			+ - Fabio Estevam <festevam@gmail.com>
			+
			+allOf:
			+ - $ref: /schemas/media/video-interface-devices.yaml#
			+
			+properties:
			+ compatible:
			+ const: ovti,ov5642
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ description: XCLK Input Clock
			+
			+ AVDD-supply:
			+ description: Analog voltage supply, 2.8V.
			+
			+ DVDD-supply:
			+ description: Digital core voltage supply, 1.5V.
			+
			+ DOVDD-supply:
			+ description: Digital I/O voltage supply, 1.8V.
			+
			+ powerdown-gpios:
			+ maxItems: 1
			+ description: Reference to the GPIO connected to the powerdown pin, if any.
			+
			+ reset-gpios:
			+ maxItems: 1
			+ description: Reference to the GPIO connected to the reset pin, if any.
			+
			+ port:
			+ $ref: /schemas/graph.yaml#/$defs/port-base
			+ description: \|
			+ Video output port.
			+
			+ properties:
			+ endpoint:
			+ $ref: /schemas/media/video-interfaces.yaml#
			+ unevaluatedProperties: false
			+
			+ properties:
			+ bus-type:
			+ enum: [5, 6]
			+
			+ bus-width:
			+ enum: [8, 10]
			+ default: 10
			+
			+ data-shift:
			+ enum: [0, 2]
			+ default: 0
			+
			+ hsync-active:
			+ enum: [0, 1]
			+ default: 1
			+
			+ vsync-active:
			+ enum: [0, 1]
			+ default: 1
			+
			+ pclk-sample:
			+ enum: [0, 1]
			+ default: 1
			+
			+ allOf:
			+ - if:
			+ properties:
			+ bus-type:
			+ const: 6
			+ then:
			+ properties:
			+ hsync-active: false
			+ vsync-active: false
			+
			+ - if:
			+ properties:
			+ bus-width:
			+ const: 10
			+ then:
			+ properties:
			+ data-shift:
			+ const: 0
			+
			+ required:
			+ - bus-type
			+
			+ additionalProperties: false
			+
			+required:
			+ - compatible
			+ - reg
			+ - clocks
			+ - port
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/gpio/gpio.h>
			+ #include <dt-bindings/media/video-interfaces.h>
			+
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ camera@3c {
			+ compatible = "ovti,ov5642";
			+ reg = <0x3c>;
			+ pinctrl-names = "default";
			+ pinctrl-0 = <&pinctrl_ov5642>;
			+ clocks = <&clk_ext_camera>;
			+ DOVDD-supply = <&vgen4_reg>;
			+ AVDD-supply = <&vgen3_reg>;
			+ DVDD-supply = <&vgen2_reg>;
			+ powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
			+ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
			+
			+ port {
			+ ov5642_to_parallel: endpoint {
			+ bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
			+ remote-endpoint = <&parallel_from_ov5642>;
			+ bus-width = <8>;
			+ data-shift = <2>; /* lines 9:2 are used */
			+ hsync-active = <0>;
			+ vsync-active = <0>;
			+ pclk-sample = <1>;
			+ };
			+ };
			+ };
			+ };

  title: Omnivision OV5693/OV5695 CMOS Sensors
  maintainers:
--  - Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
++  - Tommaso Merciai <tomm.merciai@gmail.com>
  description: |
    The Omnivision OV5693/OV5695 are high performance, 1/4-inch, 5 megapixel, CMOS

    - vddd-supply
    - port
--additionalProperties: false
++unevaluatedProperties: false
  examples:
    - |

sys/contrib/device-tree/Bindings/media/i2c/sony,imx415.yaml
@@ -44,14 +44,6 @@ properties:
	description: Sensor reset (XCLR) GPIO	description: Sensor reset (XCLR) GPIO
	maxItems: 1	maxItems: 1

	- flash-leds: true
	-
	- lens-focus: true
	-
	- orientation: true
	-
	- rotation: true
	-
	port:	port:
	$ref: /schemas/graph.yaml#/$defs/port-base	$ref: /schemas/graph.yaml#/$defs/port-base
	unevaluatedProperties: false	unevaluatedProperties: false
@@ -89,7 +81,7 @@ required:
	- ovdd-supply	- ovdd-supply
	- port	- port

	-~~additionalProperties:~~ false	+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

              maxItems: 1
            i2c-alias:
++            $ref: /schemas/types.yaml#/definitions/uint32
              description:
                The I2C address used for the serializer. Transactions to this
                address on the I2C bus where the deserializer resides are

sys/contrib/device-tree/Bindings/media/nuvoton,npcm-ece.yaml
@@ -0,0 +1,43 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/media/nuvoton,npcm-ece.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Nuvoton NPCM Encoding Compression Engine
			+
			+maintainers:
			+ - Joseph Liu <kwliu@nuvoton.com>
			+ - Marvin Lin <kflin@nuvoton.com>
			+
			+description: \|
			+ Video Encoding Compression Engine (ECE) present on Nuvoton NPCM SoCs.
			+
			+properties:
			+ compatible:
			+ enum:
			+ - nuvoton,npcm750-ece
			+ - nuvoton,npcm845-ece
			+
			+ reg:
			+ maxItems: 1
			+
			+ resets:
			+ maxItems: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - resets
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
			+
			+ ece: video-codec@f0820000 {
			+ compatible = "nuvoton,npcm750-ece";
			+ reg = <0xf0820000 0x2000>;
			+ resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_ECE>;
			+ };

sys/contrib/device-tree/Bindings/media/nuvoton,npcm-vcd.yaml
@@ -0,0 +1,72 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/media/nuvoton,npcm-vcd.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Nuvoton NPCM Video Capture/Differentiation Engine
			+
			+maintainers:
			+ - Joseph Liu <kwliu@nuvoton.com>
			+ - Marvin Lin <kflin@nuvoton.com>
			+
			+description: \|
			+ Video Capture/Differentiation Engine (VCD) present on Nuvoton NPCM SoCs.
			+
			+properties:
			+ compatible:
			+ enum:
			+ - nuvoton,npcm750-vcd
			+ - nuvoton,npcm845-vcd
			+
			+ reg:
			+ maxItems: 1
			+
			+ interrupts:
			+ maxItems: 1
			+
			+ resets:
			+ maxItems: 1
			+
			+ nuvoton,sysgcr:
			+ $ref: /schemas/types.yaml#/definitions/phandle
			+ description: phandle to access GCR (Global Control Register) registers.
			+
			+ nuvoton,sysgfxi:
			+ $ref: /schemas/types.yaml#/definitions/phandle
			+ description: phandle to access GFXI (Graphics Core Information) registers.
			+
			+ nuvoton,ece:
			+ $ref: /schemas/types.yaml#/definitions/phandle
			+ description: phandle to access ECE (Encoding Compression Engine) registers.
			+
			+ memory-region:
			+ maxItems: 1
			+ description:
			+ CMA pool to use for buffers allocation instead of the default CMA pool.
			+
			+required:
			+ - compatible
			+ - reg
			+ - interrupts
			+ - resets
			+ - nuvoton,sysgcr
			+ - nuvoton,sysgfxi
			+ - nuvoton,ece
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/interrupt-controller/arm-gic.h>
			+ #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
			+
			+ vcd: vcd@f0810000 {
			+ compatible = "nuvoton,npcm750-vcd";
			+ reg = <0xf0810000 0x10000>;
			+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
			+ resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_VCD>;
			+ nuvoton,sysgcr = <&gcr>;
			+ nuvoton,sysgfxi = <&gfxi>;
			+ nuvoton,ece = <&ece>;
			+ };

sys/contrib/device-tree/Bindings/media/qcom,sdm845-venus-v2.yaml
@@ -48,6 +48,14 @@ properties:
	iommus:	iommus:
	maxItems: 2	maxItems: 2

		+ interconnects:
		+ maxItems: 2
		+
		+ interconnect-names:
		+ items:
		+ - const: video-mem
		+ - const: cpu-cfg
		+
	operating-points-v2: true	operating-points-v2: true
	opp-table:	opp-table:
	type: object	type: object

sys/contrib/device-tree/Bindings/media/rockchip-vpu.yaml
@@ -68,6 +68,13 @@ properties:
	iommus:	iommus:
	maxItems: 1	maxItems: 1

		+ resets:
		+ items:
		+ - description: AXI reset line
		+ - description: AXI bus interface unit reset line
		+ - description: APB reset line
		+ - description: APB bus interface unit reset line
		+
	required:	required:
	- compatible	- compatible
	- reg	- reg

    power-domains:
      maxItems: 1
++  samsung,pmu-syscon:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      Power Management Unit (PMU) system controller interface, used to
++      power/start the ISP.
++
  patternProperties:
    "^pmu@[0-9a-f]+$":
      type: object
      additionalProperties: false
++    deprecated: true
      description:
        Node representing the SoC's Power Management Unit (duplicated with the
--      correct PMU node in the SoC).
++      correct PMU node in the SoC). Deprecated, use samsung,pmu-syscon.
      properties:
        reg:
    - clock-names
    - interrupts
    - ranges
++  - samsung,pmu-syscon
    - '#size-cells'
  additionalProperties: false
                   <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
          iommu-names = "isp", "drc", "fd", "mcuctl";
          power-domains = <&pd_isp>;
++        samsung,pmu-syscon = <&pmu_system_controller>;
          #address-cells = <1>;
          #size-cells = <1>;
          ranges;
--        pmu@10020000 {
--            reg = <0x10020000 0x3000>;
--        };
          i2c-isp@12140000 {
              compatible = "samsung,exynos4212-i2c-isp";
              reg = <0x12140000 0x100>;

          #clock-cells = <1>;
          #address-cells = <1>;
          #size-cells = <1>;
--        ranges = <0x0 0x0 0x18000000>;
++        ranges = <0x0 0x0 0xba1000>;
          clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
                   <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
          pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
          pinctrl-names = "default";
--        fimc@11800000 {
++        fimc@0 {
              compatible = "samsung,exynos4212-fimc";
--            reg = <0x11800000 0x1000>;
++            reg = <0x00000000 0x1000>;
              interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
              clocks = <&clock CLK_FIMC0>,
                       <&clock CLK_SCLK_FIMC0>;
          /* ... FIMC 1-3 */
--        csis@11880000 {
++        csis@80000 {
              compatible = "samsung,exynos4210-csis";
--            reg = <0x11880000 0x4000>;
++            reg = <0x00080000 0x4000>;
              interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
              clocks = <&clock CLK_CSIS0>,
                       <&clock CLK_SCLK_CSIS0>;
          /* ... CSIS 1 */
--        fimc-lite@12390000 {
++        fimc-lite@b90000 {
                compatible = "samsung,exynos4212-fimc-lite";
--              reg = <0x12390000 0x1000>;
++              reg = <0xb90000 0x1000>;
                interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                power-domains = <&pd_isp>;
                clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
          /* ... FIMC-LITE 1 */
--        fimc-is@12000000 {
++        fimc-is@800000 {
              compatible = "samsung,exynos4212-fimc-is";
--            reg = <0x12000000 0x260000>;
++            reg = <0x00800000 0x260000>;
              interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
                           <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
              clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
                       <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
              iommu-names = "isp", "drc", "fd", "mcuctl";
              power-domains = <&pd_isp>;
++            samsung,pmu-syscon = <&pmu_system_controller>;
              #address-cells = <1>;
              #size-cells = <1>;
              ranges;
--            pmu@10020000 {
++            i2c-isp@940000 {
--                reg = <0x10020000 0x3000>;
--            };
--            i2c-isp@12140000 {
                  compatible = "samsung,exynos4212-i2c-isp";
--                reg = <0x12140000 0x100>;
++                reg = <0x00940000 0x100>;
                  clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
                  clock-names = "i2c_isp";
                  pinctrl-0 = <&fimc_is_i2c1>;

sys/contrib/device-tree/Bindings/media/ti,j721e-csi2rx-shim.yaml
@@ -0,0 +1,100 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/media/ti,j721e-csi2rx-shim.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: TI J721E CSI2RX Shim
			+
			+description: \|
			+ The TI J721E CSI2RX Shim is a wrapper around Cadence CSI2RX bridge that
			+ enables sending captured frames to memory over PSI-L DMA. In the J721E
			+ Technical Reference Manual (SPRUIL1B) it is referred to as "SHIM" under the
			+ CSI_RX_IF section.
			+
			+maintainers:
			+ - Jai Luthra <j-luthra@ti.com>
			+
			+properties:
			+ compatible:
			+ const: ti,j721e-csi2rx-shim
			+
			+ dmas:
			+ maxItems: 1
			+
			+ dma-names:
			+ items:
			+ - const: rx0
			+
			+ reg:
			+ maxItems: 1
			+
			+ power-domains:
			+ maxItems: 1
			+
			+ ranges: true
			+
			+ "#address-cells": true
			+
			+ "#size-cells": true
			+
			+patternProperties:
			+ "^csi-bridge@":
			+ type: object
			+ description: CSI2 bridge node.
			+ $ref: cdns,csi2rx.yaml#
			+
			+required:
			+ - compatible
			+ - reg
			+ - dmas
			+ - dma-names
			+ - power-domains
			+ - ranges
			+ - "#address-cells"
			+ - "#size-cells"
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
			+
			+ ti_csi2rx0: ticsi2rx@4500000 {
			+ compatible = "ti,j721e-csi2rx-shim";
			+ dmas = <&main_udmap 0x4940>;
			+ dma-names = "rx0";
			+ reg = <0x4500000 0x1000>;
			+ power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
			+ #address-cells = <1>;
			+ #size-cells = <1>;
			+ ranges;
			+
			+ cdns_csi2rx: csi-bridge@4504000 {
			+ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
			+ reg = <0x4504000 0x1000>;
			+ clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
			+ <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
			+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
			+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			+ phys = <&dphy0>;
			+ phy-names = "dphy";
			+
			+ ports {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ csi2_0: port@0 {
			+
			+ reg = <0>;
			+
			+ csi2rx0_in_sensor: endpoint {
			+ remote-endpoint = <&csi2_cam0>;
			+ bus-type = <4>; /* CSI2 DPHY. */
			+ clock-lanes = <0>;
			+ data-lanes = <1 2>;
			+ };
			+ };
			+ };
			+ };
			+ };

      $ref: /schemas/types.yaml#/definitions/uint32-array
      minItems: 1
      maxItems: 8
++    uniqueItems: true
      items:
        # Assume up to 9 physical lane indices
        maximum: 8

    ".*@[0-9]+$":
      type: object
      $ref: mc-peripheral-props.yaml#
++    additionalProperties: true
  required:
    - compatible

  patternProperties:
    "flash@[0-9a-f]+$":
      type: object
++    additionalProperties: true
++
      properties:
        compatible:
          contains:

      $ref: /schemas/types.yaml#/definitions/phandle
      description:
        Node to get DDR loading. Refer to
--      Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
++      Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml.
    clocks:
      maxItems: 1

        bus. The device can be a NAND chip, SRAM device, NOR device
        or an ASIC.
      $ref: ti,gpmc-child.yaml
++    additionalProperties: true
  required:
    - compatible

sys/contrib/device-tree/Bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
@@ -0,0 +1,57 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
			+
			+maintainers:
			+ - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
			+ - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
			+
			+description:
			+ The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
			+ 4X memory interfaces. Versal DDR memory controller has an optional ECC support
			+ which correct single bit ECC errors and detect double bit ECC errors.
			+
			+properties:
			+ compatible:
			+ const: xlnx,versal-ddrmc
			+
			+ reg:
			+ items:
			+ - description: DDR Memory Controller registers
			+ - description: NOC registers corresponding to DDR Memory Controller
			+
			+ reg-names:
			+ items:
			+ - const: base
			+ - const: noc
			+
			+ interrupts:
			+ maxItems: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - reg-names
			+ - interrupts
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/interrupt-controller/arm-gic.h>
			+
			+ bus {
			+ #address-cells = <2>;
			+ #size-cells = <2>;
			+ memory-controller@f6150000 {
			+ compatible = "xlnx,versal-ddrmc";
			+ reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;
			+ reg-names = "base", "noc";
			+ interrupt-parent = <&gic>;
			+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
			+ };
			+ };

sys/contrib/device-tree/Bindings/mfd/arm,dev-platforms-syscon.yaml
@@ -0,0 +1,67 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/mfd/arm,dev-platforms-syscon.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Arm Ltd Developer Platforms System Controllers
			+
			+maintainers:
			+ - Linus Walleij <linus.walleij@linaro.org>
			+
			+description:
			+ The Arm Ltd Integrator, Realview, and Versatile families of developer
			+ platforms are contain various system controller blocks. Often these blocks
			+ are part of a daughterboard or motherboard module.
			+
			+properties:
			+ compatible:
			+ oneOf:
			+ - items:
			+ - enum:
			+ - arm,integrator-ap-syscon
			+ - arm,integrator-cp-syscon
			+ - arm,integrator-sp-syscon
			+ - arm,im-pd1-syscon
			+ - const: syscon
			+ - items:
			+ - enum:
			+ - arm,core-module-integrator
			+ - arm,integrator-ap-syscon
			+ - arm,integrator-cp-syscon
			+ - arm,integrator-sp-syscon
			+ - arm,realview-eb-syscon
			+ - arm,realview-pb1176-syscon
			+ - arm,realview-pb11mp-syscon
			+ - arm,realview-pba8-syscon
			+ - arm,realview-pbx-syscon
			+ - arm,versatile-ib2-syscon
			+ - const: syscon
			+ - const: simple-mfd
			+ - items:
			+ - enum:
			+ - arm,realview-eb11mp-revb-syscon
			+ - arm,realview-eb11mp-revc-syscon
			+ - const: arm,realview-eb-syscon
			+ - const: syscon
			+ - const: simple-mfd
			+
			+ reg:
			+ maxItems: 1
			+
			+ ranges: true
			+
			+ '#address-cells':
			+ const: 1
			+
			+ '#size-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+
			+additionalProperties:
			+ type: object
			+
			+...

          pinctrl_nand: nand-pins {
            function = "nand";
--          group = "nand_grp";
++          pins = "nand_grp";
          };
          pinctrl_gpio35_alt: gpio35_alt-pins {
            function = "gpio35_alt";
--          pin = "gpio35";
++          pins = "gpio35";
          };
          pinctrl_dectpd: dectpd-pins {
            function = "dectpd";
--          group = "dectpd_grp";
++          pins = "dectpd_grp";
          };
          pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
            function = "vdsl_phy_override_0";
--          group = "vdsl_phy_override_0_grp";
++          pins = "vdsl_phy_override_0_grp";
          };
          pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
            function = "vdsl_phy_override_1";
--          group = "vdsl_phy_override_1_grp";
++          pins = "vdsl_phy_override_1_grp";
          };
          pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
            function = "vdsl_phy_override_2";
--          group = "vdsl_phy_override_2_grp";
++          pins = "vdsl_phy_override_2_grp";
          };
          pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
            function = "vdsl_phy_override_3";
--          group = "vdsl_phy_override_3_grp";
++          pins = "vdsl_phy_override_3_grp";
          };
          pinctrl_dsl_gpio8: dsl_gpio8-pins {
            function = "dsl_gpio8";
--          group = "dsl_gpio8";
++          pins = "dsl_gpio8";
          };
          pinctrl_dsl_gpio9: dsl_gpio9-pins {
            function = "dsl_gpio9";
--          group = "dsl_gpio9";
++          pins = "dsl_gpio9";
          };
        };
      };

          pinctrl_nand: nand-pins {
            function = "nand";
--          group = "nand_grp";
++          pins = "nand_grp";
          };
        };
      };

          pinctrl_uart1: uart1-pins {
            function = "uart1";
--          group = "uart1_grp";
++          pins = "uart1_grp";
          };
        };
      };

sys/contrib/device-tree/Bindings/mfd/maxim,max5970.yaml
@@ -45,8 +45,13 @@ properties:
	patternProperties:	patternProperties:
	"^led@[0-3]$":	"^led@[0-3]$":
	$ref: /schemas/leds/common.yaml#	$ref: /schemas/leds/common.yaml#
		+ unevaluatedProperties: false
	type: object	type: object

		+ properties:
		+ reg:
		+ maximum: 3
		+
	additionalProperties: false	additionalProperties: false

	vss1-supply:	vss1-supply:

sys/contrib/device-tree/Bindings/mfd/maxim,max8925.yaml
@@ -0,0 +1,145 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/mfd/maxim,max8925.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MAX8925 PMIC from Maxim Integrated.
			+
			+maintainers:
			+ - Lee Jones <lee@kernel.org>
			+
			+properties:
			+ compatible:
			+ const: maxim,max8925
			+
			+ reg:
			+ maxItems: 1
			+
			+ interrupts:
			+ maxItems: 1
			+
			+ interrupt-controller: true
			+
			+ "#interrupt-cells":
			+ const: 1
			+ description:
			+ The cell is the IRQ number
			+
			+ maxim,tsc-irq:
			+ description: second interrupt from max8925
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+
			+ regulators:
			+ type: object
			+
			+ patternProperties:
			+ "^SDV[1-3]$\|^LDO[1-9]$\|^LDO1[0-9]$\|^LDO20$":
			+ description: regulator configuration for SDV1-3 and LDO1-20
			+ $ref: /schemas/regulator/regulator.yaml
			+ unevaluatedProperties: false
			+
			+ additionalProperties: false
			+
			+ backlight:
			+ type: object
			+ properties:
			+ maxim,max8925-dual-string:
			+ description: set to 1 to support dual string
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ enum: [0, 1]
			+ default: 0
			+
			+ additionalProperties: false
			+
			+ charger:
			+ type: object
			+ properties:
			+ batt-detect:
			+ description: set to 1 if battery detection via ID pin is supported
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ enum: [0, 1]
			+ default: 0
			+
			+ topoff-threshold:
			+ description: charging current in topoff mode, configures bits 5-6 in CHG_CNTL1
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ minimum: 0
			+ maximum: 3
			+ default: 0
			+
			+ fast-charge:
			+ description: set charging current in fast mode, configures bits 0-3 in CHG_CNTL1
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ minimum: 0
			+ maximum: 7
			+ default: 0
			+
			+ no-temp-support:
			+ description: set to 1 if temperature sensing is not supported
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ enum: [0, 1]
			+ default: 0
			+
			+ no-insert-detect:
			+ description: set to 1 if AC detection is not supported
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ enum: [0, 1]
			+ default: 0
			+
			+ additionalProperties: false
			+
			+required:
			+ - compatible
			+ - reg
			+ - interrupts
			+ - interrupt-controller
			+ - "#interrupt-cells"
			+ - regulators
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ pmic@3c {
			+ compatible = "maxim,max8925";
			+ reg = <0x3c>;
			+ interrupts = <1>;
			+ interrupt-parent = <&intcmux4>;
			+ interrupt-controller;
			+ #interrupt-cells = <1>;
			+ maxim,tsc-irq = <0>;
			+
			+ regulators {
			+ SDV1 {
			+ regulator-min-microvolt = <637500>;
			+ regulator-max-microvolt = <1425000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ LDO1 {
			+ regulator-min-microvolt = <750000>;
			+ regulator-max-microvolt = <3900000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ };
			+
			+ backlight {
			+ maxim,max8925-dual-string = <0>;
			+ };
			+
			+ charger {
			+ batt-detect = <0>;
			+ topoff-threshold = <1>;
			+ fast-charge = <7>;
			+ no-temp-support = <0>;
			+ no-insert-detect = <0>;
			+ };
			+ };
			+ };

sys/contrib/device-tree/Bindings/mfd/maxim,max8998.yaml
@@ -0,0 +1,324 @@
			+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/mfd/maxim,max8998.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Maxim MAX8998, National/TI LP3974 Power Management IC
			+
			+maintainers:
			+ - Krzysztof Kozlowski <krzk@kernel.org>
			+
			+description:
			+ The Maxim MAX8998 is a Power Management IC which includes voltage/current
			+ regulators, real time clock, battery charging controller and several other
			+ sub-blocks. It is interfaced using an I2C interface. Each sub-block is
			+ addressed by the host system using different i2c slave address.
			+
			+properties:
			+ compatible:
			+ enum:
			+ - maxim,max8998
			+ - national,lp3974
			+ - ti,lp3974
			+
			+ reg:
			+ maxItems: 1
			+
			+ interrupts:
			+ minItems: 1
			+ items:
			+ - description: Main interrupt
			+ - description: Power-on/-off interrupt
			+
			+ max8998,pmic-buck1-dvs-gpios:
			+ maxItems: 2
			+ description:
			+ Two host gpios used for buck1 DVS.
			+
			+ max8998,pmic-buck2-dvs-gpio:
			+ maxItems: 1
			+ description:
			+ Host gpio used for buck2 DVS.
			+
			+ max8998,pmic-buck1-default-dvs-idx:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ enum: [0, 1, 2, 3]
			+ default: 0
			+ description:
			+ Default voltage setting selected from the possible 4 options selectable
			+ by the DVS gpios.
			+
			+ max8998,pmic-buck2-default-dvs-idx:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ enum: [0, 1]
			+ default: 0
			+ description:
			+ Default voltage setting selected from the possible 2 options selectable
			+ by the DVS GPIOs.
			+
			+ max8998,pmic-buck-voltage-lock:
			+ type: boolean
			+ description:
			+ If present, disallows changing of preprogrammed buck DVS voltages.
			+
			+ max8998,pmic-buck1-dvs-voltage:
			+ $ref: /schemas/types.yaml#/definitions/uint32-array
			+ maxItems: 4
			+ description:
			+ Four voltage values in microvolts for buck1 regulator that can be
			+ selected using DVS GPIO.
			+
			+ max8998,pmic-buck2-dvs-voltage:
			+ $ref: /schemas/types.yaml#/definitions/uint32-array
			+ maxItems: 2
			+ description:
			+ Two voltage values in microvolts for buck2 regulator that can be
			+ selected using DVS GPIO.
			+
			+ regulators:
			+ type: object
			+ additionalProperties: false
			+
			+ properties:
			+ CHARGER:
			+ type: object
			+ $ref: /schemas/regulator/regulator.yaml#
			+ unevaluatedProperties: false
			+ description:
			+ CHARGER is main battery charger current control, wrongly represented
			+ as regulator.
			+
			+ properties:
			+ regulator-min-microamp:
			+ minimum: 90000
			+ maximum: 800000
			+
			+ regulator-max-microamp:
			+ minimum: 90000
			+ maximum: 800000
			+
			+ regulator-min-microvolt: false
			+ regulator-max-microvolt: false
			+
			+ required:
			+ - regulator-name
			+
			+ patternProperties:
			+ "^(LDO([2-9]\|1[0-7])\|BUCK[1-4])$":
			+ type: object
			+ $ref: /schemas/regulator/regulator.yaml#
			+ unevaluatedProperties: false
			+
			+ required:
			+ - regulator-name
			+
			+ "^(EN32KHz-AP\|EN32KHz-CP\|ENVICHG\|ESAFEOUT[12])$":
			+ type: object
			+ $ref: /schemas/regulator/regulator.yaml#
			+ unevaluatedProperties: false
			+ description: \|
			+ EN32KHz-AP and EN32KHz-CP are 32768 Hz clocks, wrongly represented as
			+ regulators.
			+ ENVICHG is a Battery Charging Current Monitor Output.
			+
			+ properties:
			+ regulator-min-microvolt: false
			+ regulator-max-microvolt: false
			+
			+ required:
			+ - regulator-name
			+
			+dependencies:
			+ max8998,pmic-buck1-dvs-gpios: [ "max8998,pmic-buck1-dvs-voltage" ]
			+ max8998,pmic-buck2-dvs-gpio: [ "max8998,pmic-buck2-dvs-voltage" ]
			+
			+required:
			+ - compatible
			+ - reg
			+ - regulators
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/gpio/gpio.h>
			+ #include <dt-bindings/interrupt-controller/irq.h>
			+
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ pmic@66 {
			+ compatible = "national,lp3974";
			+ reg = <0x66>;
			+ interrupts-extended = <&gpx0 7 IRQ_TYPE_LEVEL_LOW>,
			+ <&gpx2 7 IRQ_TYPE_LEVEL_LOW>;
			+ pinctrl-names = "default";
			+ pinctrl-0 = <&lp3974_irq>;
			+
			+ max8998,pmic-buck1-default-dvs-idx = <0>;
			+ max8998,pmic-buck1-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>,
			+ <&gpx0 6 GPIO_ACTIVE_HIGH>;
			+ max8998,pmic-buck1-dvs-voltage = <1100000>, <1000000>,
			+ <1100000>, <1000000>;
			+ max8998,pmic-buck2-default-dvs-idx = <0>;
			+ max8998,pmic-buck2-dvs-gpio = <&gpe2 0 GPIO_ACTIVE_HIGH>;
			+ max8998,pmic-buck2-dvs-voltage = <1200000>, <1100000>;
			+
			+ regulators {
			+ LDO2 {
			+ regulator-name = "VALIVE_1.2V";
			+ regulator-min-microvolt = <1200000>;
			+ regulator-max-microvolt = <1200000>;
			+ regulator-always-on;
			+ };
			+
			+ LDO3 {
			+ regulator-name = "VUSB+MIPI_1.1V";
			+ regulator-min-microvolt = <1100000>;
			+ regulator-max-microvolt = <1100000>;
			+ regulator-always-on;
			+ };
			+
			+ LDO4 {
			+ regulator-name = "VADC_3.3V";
			+ regulator-min-microvolt = <3300000>;
			+ regulator-max-microvolt = <3300000>;
			+ };
			+
			+ LDO5 {
			+ regulator-name = "VTF_2.8V";
			+ regulator-min-microvolt = <2800000>;
			+ regulator-max-microvolt = <2800000>;
			+ };
			+
			+ LDO6 {
			+ regulator-name = "LDO6";
			+ regulator-min-microvolt = <2000000>;
			+ regulator-max-microvolt = <2000000>;
			+ };
			+
			+ LDO7 {
			+ regulator-name = "VLCD+VMIPI_1.8V";
			+ regulator-min-microvolt = <1800000>;
			+ regulator-max-microvolt = <1800000>;
			+ };
			+
			+ LDO8 {
			+ regulator-name = "VUSB+VDAC_3.3V";
			+ regulator-min-microvolt = <3300000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-always-on;
			+ };
			+
			+ LDO9 {
			+ regulator-name = "VCC_2.8V";
			+ regulator-min-microvolt = <2800000>;
			+ regulator-max-microvolt = <2800000>;
			+ regulator-always-on;
			+ };
			+
			+ LDO10 {
			+ regulator-name = "VPLL_1.1V";
			+ regulator-min-microvolt = <1100000>;
			+ regulator-max-microvolt = <1100000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ LDO11 {
			+ regulator-name = "CAM_AF_3.3V";
			+ regulator-min-microvolt = <3300000>;
			+ regulator-max-microvolt = <3300000>;
			+ };
			+
			+ LDO12 {
			+ regulator-name = "PS_2.8V";
			+ regulator-min-microvolt = <2800000>;
			+ regulator-max-microvolt = <2800000>;
			+ };
			+
			+ LDO13 {
			+ regulator-name = "VHIC_1.2V";
			+ regulator-min-microvolt = <1200000>;
			+ regulator-max-microvolt = <1200000>;
			+ };
			+
			+ LDO14 {
			+ regulator-name = "CAM_I_HOST_1.8V";
			+ regulator-min-microvolt = <1800000>;
			+ regulator-max-microvolt = <1800000>;
			+ };
			+
			+ LDO15 {
			+ regulator-name = "CAM_S_DIG+FM33_CORE_1.2V";
			+ regulator-min-microvolt = <1200000>;
			+ regulator-max-microvolt = <1200000>;
			+ };
			+
			+ LDO16 {
			+ regulator-name = "CAM_S_ANA_2.8V";
			+ regulator-min-microvolt = <2800000>;
			+ regulator-max-microvolt = <2800000>;
			+ };
			+
			+ LDO17 {
			+ regulator-name = "VCC_3.0V_LCD";
			+ regulator-min-microvolt = <3000000>;
			+ regulator-max-microvolt = <3000000>;
			+ };
			+
			+ BUCK1 {
			+ regulator-name = "VINT_1.1V";
			+ regulator-min-microvolt = <750000>;
			+ regulator-max-microvolt = <1500000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ BUCK2 {
			+ regulator-name = "VG3D_1.1V";
			+ regulator-min-microvolt = <750000>;
			+ regulator-max-microvolt = <1500000>;
			+ regulator-boot-on;
			+ };
			+
			+ BUCK3 {
			+ regulator-name = "VCC_1.8V";
			+ regulator-min-microvolt = <1800000>;
			+ regulator-max-microvolt = <1800000>;
			+ regulator-always-on;
			+ };
			+
			+ BUCK4 {
			+ regulator-name = "VMEM_1.2V";
			+ regulator-min-microvolt = <1200000>;
			+ regulator-max-microvolt = <1200000>;
			+ regulator-always-on;
			+ };
			+
			+ EN32KHz-AP {
			+ regulator-name = "32KHz AP";
			+ regulator-always-on;
			+ };
			+
			+ EN32KHz-CP {
			+ regulator-name = "32KHz CP";
			+ };
			+
			+ ENVICHG {
			+ regulator-name = "VICHG";
			+ };
			+
			+ ESAFEOUT1 {
			+ regulator-name = "SAFEOUT1";
			+ };
			+
			+ ESAFEOUT2 {
			+ regulator-name = "SAFEOUT2";
			+ regulator-boot-on;
			+ };
			+ };
			+ };
			+ };

    regulators:
      type: object
      $ref: /schemas/regulator/mediatek,mt6357-regulator.yaml
++    unevaluatedProperties: false
      description:
        List of MT6357 BUCKs and LDOs regulators.
    keys:
      type: object
      $ref: /schemas/input/mediatek,pmic-keys.yaml
++    unevaluatedProperties: false
      description:
        MT6357 power and home keys.

          "mediatek,mt6323" for PMIC MT6323
          "mediatek,mt6331" for PMIC MT6331 and MT6332
          "mediatek,mt6357" for PMIC MT6357
--        "mediatek,mt6358" for PMIC MT6358 and MT6366
++        "mediatek,mt6358" for PMIC MT6358
          "mediatek,mt6359" for PMIC MT6359
++        "mediatek,mt6366", "mediatek,mt6358" for PMIC MT6366
          "mediatek,mt6397" for PMIC MT6397
  Optional subnodes:
                  - compatible: "mediatek,mt6323-regulator"
          see ../regulator/mt6323-regulator.txt
                  - compatible: "mediatek,mt6358-regulator"
++                - compatible: "mediatek,mt6366-regulator", "mediatek-mt6358-regulator"
          see ../regulator/mt6358-regulator.txt
                  - compatible: "mediatek,mt6397-regulator"
          see ../regulator/mt6397-regulator.txt

            - qcom,pm8350
            - qcom,pm8350b
            - qcom,pm8350c
++          - qcom,pm8450
            - qcom,pm8550
            - qcom,pm8550b
            - qcom,pm8550ve
      type: object
      $ref: /schemas/thermal/qcom,spmi-temp-alarm.yaml#
++  "^typec@[0-9a-f]+$":
++    type: object
++    $ref: /schemas/usb/qcom,pmic-typec.yaml#
++
    "^usb-detect@[0-9a-f]+$":
      type: object
      $ref: /schemas/extcon/qcom,pm8941-misc.yaml#
          interrupt-controller;
          #interrupt-cells = <4>;
--        pmi8998_lsid0: pmic@2 {
++        pmic@2 {
              compatible = "qcom,pmi8998", "qcom,spmi-pmic";
              reg = <0x2 SPMI_USID>;
              #address-cells = <1>;
              #size-cells = <0>;
--            pmi8998_gpio: gpio@c000 {
++            gpio@c000 {
                  compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio";
                  reg = <0xc000>;
                  gpio-controller;
              };
          };
--        pm6150_gpio: gpio@c000 {
++        gpio@c000 {
              compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio";
              reg = <0xc000>;
              gpio-controller;

            - qcom,sdm845-tcsr
            - qcom,sdx55-tcsr
            - qcom,sdx65-tcsr
++          - qcom,sm4450-tcsr
            - qcom,sm8150-tcsr
            - qcom,sm8450-tcsr
            - qcom,tcsr-apq8064

sys/contrib/device-tree/Bindings/mfd/qcom-pm8xxx.yaml
@@ -43,13 +43,37 @@ properties:
	interrupt-controller: true	interrupt-controller: true

	patternProperties:	patternProperties:
		+ "gpio@[0-9a-f]+$":
		+ type: object
		+ $ref: /schemas/pinctrl/qcom,pmic-gpio.yaml#
		+
		+ "keypad@[0-9a-f]+$":
		+ type: object
		+ $ref: /schemas/input/qcom,pm8921-keypad.yaml#
		+
	"led@[0-9a-f]+$":	"led@[0-9a-f]+$":
	type: object	type: object
	$ref: /schemas/leds/qcom,pm8058-led.yaml#	$ref: /schemas/leds/qcom,pm8058-led.yaml#

		+ "mpps@[0-9a-f]+$":
		+ type: object
		+ $ref: /schemas/pinctrl/qcom,pmic-mpp.yaml#
		+
		+ "pwrkey@[0-9a-f]+$":
		+ type: object
		+ $ref: /schemas/input/qcom,pm8921-pwrkey.yaml#
		+
	"rtc@[0-9a-f]+$":	"rtc@[0-9a-f]+$":
	type: object	type: object
	- $ref: ../rtc/qcom-pm8xxx-rtc.yaml	+ $ref: /schemas/rtc/qcom-pm8xxx-rtc.yaml#
		+
		+ "vibrator@[0-9a-f]+$":
		+ type: object
		+ $ref: /schemas/input/qcom,pm8xxx-vib.yaml#
		+
		+ "xoadc@[0-9a-f]+$":
		+ type: object
		+ $ref: /schemas/iio/adc/qcom,pm8018-adc.yaml#

	required:	required:
	- compatible	- compatible

    rockchip,system-power-controller:
      type: boolean
++    deprecated: true
      description:
        Telling whether or not this PMIC is controlling the system power.
++  system-power-controller: true
++
    wakeup-source:
      type: boolean
      description:
        "^(DCDC_REG[1-4]|LDO_REG[1-3])$":
          type: object
          $ref: ../regulator/regulator.yaml#
++        unevaluatedProperties: false
      unevaluatedProperties: false
  allOf:

    '#gpio-cells':
      const: 2
++  system-power-controller: true
++
    vcc1-supply:
      description:
        The input supply for dcdc-reg1.

    rockchip,system-power-controller:
      type: boolean
++    deprecated: true
      description:
        Telling whether or not this PMIC is controlling the system power.
++  system-power-controller: true
++
    wakeup-source:
      type: boolean
      description:
        "^(DCDC_REG[1-4]|LDO_REG[1-8]|SWITCH_REG[1-2])$":
          type: object
          $ref: ../regulator/regulator.yaml#
++        unevaluatedProperties: false
      unevaluatedProperties: false
  required:

    rockchip,system-power-controller:
      type: boolean
++    deprecated: true
      description:
        Telling whether or not this PMIC is controlling the system power.
++  system-power-controller: true
++
    wakeup-source:
      type: boolean
      description:
      patternProperties:
        "^(LDO_REG[1-9]|DCDC_REG[1-5]|SWITCH_REG[1-2])$":
          type: object
--        $ref: ../regulator/regulator.yaml#
++        $ref: /schemas/regulator/regulator.yaml#
++        unevaluatedProperties: false
      unevaluatedProperties: false
  allOf:

    rockchip,system-power-controller:
      type: boolean
++    deprecated: true
      description:
        Telling whether or not this PMIC is controlling the system power.
++  system-power-controller: true
++
    wakeup-source:
      type: boolean
      description:

    rockchip,system-power-controller:
      type: boolean
++    deprecated: true
      description:
        Telling whether or not this PMIC is controlling the system power.
++  system-power-controller: true
++
    wakeup-source:
      type: boolean
      description:
        "^(DCDC_REG[1-4]|DCDC_BOOST|LDO_REG[1-9]|SWITCH_REG|HDMI_SWITCH|OTG_SWITCH)$":
          type: object
          $ref: ../regulator/regulator.yaml#
++        unevaluatedProperties: false
      unevaluatedProperties: false
  required:

          unevaluatedProperties: false
        db8500_varm:
--        description: The voltage for the ARM Cortex A-9 CPU.
++        description: The voltage for the ARM Cortex-A9 CPU.
          type: object
          $ref: ../regulator/regulator.yaml#
          unevaluatedProperties: false

                - hisilicon,peri-subctrl
                - hpe,gxp-sysreg
                - intel,lgm-syscon
++              - loongson,ls1b-syscon
++              - loongson,ls1c-syscon
                - marvell,armada-3700-usb2-host-misc
                - mediatek,mt8135-pctl-a-syscfg
                - mediatek,mt8135-pctl-b-syscfg
                - rockchip,px30-qos
                - rockchip,rk3036-qos
                - rockchip,rk3066-qos
++              - rockchip,rk3128-qos
                - rockchip,rk3228-qos
                - rockchip,rk3288-qos
                - rockchip,rk3368-qos
                - rockchip,rk3588-qos
                - rockchip,rv1126-qos
                - starfive,jh7100-sysmain
++              - ti,am654-dss-oldi-io-ctrl
            - const: syscon

        "^buck[0123]$":
          type: object
          $ref: /schemas/regulator/regulator.yaml#
++        unevaluatedProperties: false
      required:
        - buck0

        buck3210:
          type: object
          $ref: /schemas/regulator/regulator.yaml#
++        unevaluatedProperties: false
      required:
        - buck3210

        "^buck(10|23)$":
          type: object
          $ref: /schemas/regulator/regulator.yaml#
++        unevaluatedProperties: false
      required:
        - buck10

sys/contrib/device-tree/Bindings/mfd/ti,twl.yaml
@@ -0,0 +1,67 @@
			+# SPDX-License-Identifier: GPL-2.0
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/mfd/ti,twl.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Texas Instruments TWL family
			+
			+maintainers:
			+ - Andreas Kemnade <andreas@kemnade.info>
			+
			+description: \|
			+ The TWLs are Integrated Power Management Chips.
			+ Some version might contain much more analog function like
			+ USB transceiver or Audio amplifier.
			+ These chips are connected to an i2c bus.
			+
			+properties:
			+ compatible:
			+ description:
			+ TWL4030 for integrated power-management/audio CODEC device used in OMAP3
			+ based boards
			+ TWL6030/32 for integrated power-management used in OMAP4 based boards
			+ enum:
			+ - ti,twl4030
			+ - ti,twl6030
			+ - ti,twl6032
			+
			+ reg:
			+ maxItems: 1
			+
			+ interrupts:
			+ maxItems: 1
			+
			+ interrupt-controller: true
			+
			+ "#interrupt-cells":
			+ const: 1
			+
			+ "#clock-cells":
			+ const: 1
			+
			+additionalProperties: false
			+
			+required:
			+ - compatible
			+ - reg
			+ - interrupts
			+ - interrupt-controller
			+ - "#interrupt-cells"
			+
			+examples:
			+ - \|
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ pmic@48 {
			+ compatible = "ti,twl6030";
			+ reg = <0x48>;
			+ interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */
			+ interrupt-controller;
			+ #interrupt-cells = <1>;
			+ interrupt-parent = <&gic>;
			+ };
			+ };
			+

sys/contrib/device-tree/Bindings/mfd/x-powers,axp152.yaml
@@ -67,7 +67,10 @@ allOf:
	properties:	properties:
	compatible:	compatible:
	contains:	contains:
	- ~~const: x-powers,axp305~~	+ enum:
		+ - x-powers,axp15060
		+ - x-powers,axp305
		+ - x-powers,axp313a

	then:	then:
	required:	required:

sys/contrib/device-tree/Bindings/mmc/npcm,sdhci.yaml
@@ -0,0 +1,45 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/mmc/npcm,sdhci.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: NPCM SDHCI Controller
			+
			+maintainers:
			+ - Tomer Maimon <tmaimon77@gmail.com>
			+
			+allOf:
			+ - $ref: mmc-controller.yaml#
			+
			+properties:
			+ compatible:
			+ enum:
			+ - nuvoton,npcm750-sdhci
			+ - nuvoton,npcm845-sdhci
			+
			+ reg:
			+ maxItems: 1
			+
			+ interrupts:
			+ maxItems: 1
			+
			+ clocks:
			+ maxItems: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - interrupts
			+ - clocks
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ mmc@f0840000 {
			+ compatible = "nuvoton,npcm750-sdhci";
			+ reg = <0xf0840000 0x200>;
			+ interrupts = <0 27 4>;
			+ clocks = <&clk 4>;
			+ };

                - renesas,sdhi-r9a07g043 # RZ/G2UL
                - renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
                - renesas,sdhi-r9a07g054 # RZ/V2L
++              - renesas,sdhi-r9a08g045 # RZ/G3S
                - renesas,sdhi-r9a09g011 # RZ/V2M
            - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
        - items:
                - renesas,sdhi-r9a07g043
                - renesas,sdhi-r9a07g044
                - renesas,sdhi-r9a07g054
++              - renesas,sdhi-r9a08g045
                - renesas,sdhi-r9a09g011
      then:
        properties:

                - qcom,sm8350-sdhci
                - qcom,sm8450-sdhci
                - qcom,sm8550-sdhci
++              - qcom,sm8650-sdhci
            - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
    reg:
        - const: iface
        - const: core
        - const: xo
--      - const: ice
++      - enum: [ice, bus, cal, sleep]
--      - const: bus
++      - enum: [ice, bus, cal, sleep]
--      - const: cal
++      - enum: [ice, bus, cal, sleep]
--      - const: sleep
++      - enum: [ice, bus, cal, sleep]
    dma-coherent: true

    - clocks
    - clock-names
    - interrupts
--  - starfive,sysreg
  unevaluatedProperties: false
          fifo-depth = <32>;
          fifo-watermark-aligned;
          data-addr = <0>;
--        starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
      };

sys/contrib/device-tree/Bindings/mtd/mtd.yaml
@@ -43,7 +43,12 @@ patternProperties:
	deprecated: true	deprecated: true

	"^otp(-[0-9]+)?$":	"^otp(-[0-9]+)?$":
	- $ref: ../nvmem/nvmem.yaml#	+ type: object
		+
		+ allOf:
		+ - $ref: ../nvmem/nvmem.yaml#
		+ - $ref: ../nvmem/nvmem-deprecated-cells.yaml#
		+
	unevaluatedProperties: false	unevaluatedProperties: false

	description: \|	description: \|

sys/contrib/device-tree/Bindings/mtd/partitions/fixed-partitions.yaml
@@ -29,6 +29,24 @@ properties:

	"#size-cells": true	"#size-cells": true

		+ compression:
		+ $ref: /schemas/types.yaml#/definitions/string
		+ description: \|
		+ Compression algorithm used to store the data in this partition, chosen
		+ from a list of well-known algorithms.
		+
		+ The contents are compressed using this algorithm.
		+
		+ enum:
		+ - none
		+ - bzip2
		+ - gzip
		+ - lzop
		+ - lz4
		+ - lzma
		+ - xz
		+ - zstd
		+
	patternProperties:	patternProperties:
	"@[0-9a-f]+$":	"@[0-9a-f]+$":
	$ref: partition.yaml#	$ref: partition.yaml#
@@ -64,6 +82,7 @@ examples:

	uimage@100000 {	uimage@100000 {
	reg = <0x0100000 0x200000>;	reg = <0x0100000 0x200000>;
		+ compress = "lzma";
	};	};
	};	};

  allOf:
    - $ref: /schemas/mtd/partitions/partition.yaml#
    - $ref: /schemas/nvmem/nvmem.yaml#
++  - $ref: /schemas/nvmem/nvmem-deprecated-cells.yaml#
  properties:
    compatible:

                patternProperties:
                  "^ethernet-phy@[0-9a-f]$":
                    type: object
++                  $ref: ethernet-phy.yaml#
++                  unevaluatedProperties: false
                    description:
                      Integrated PHY node

          const: 0
      patternProperties:
--      "^port@[0-9]+$":
++      "^port@[0-9a-f]+$":
          type: object
          $ref: ethernet-controller.yaml#

    ports:
      type: object
++    additionalProperties: true
      patternProperties:
        '^port@[0-9a-f]$':

sys/contrib/device-tree/Bindings/net/dsa/dsa.yaml
@@ -40,17 +40,8 @@ $defs:

	patternProperties:	patternProperties:
	"^(ethernet-)?ports$":	"^(ethernet-)?ports$":
	- type: object
	- additionalProperties: false
	-
	- properties:
	- '#address-cells':
	- const: 1
	- '#size-cells':
	- const: 0
	-
	patternProperties:	patternProperties:
	- "^(ethernet-)?port@[0-9]+$":	+ "^(ethernet-)?port@[0-9a-f]+$":
	description: Ethernet switch ports	description: Ethernet switch ports
	$ref: dsa-port.yaml#	$ref: dsa-port.yaml#
	unevaluatedProperties: false	unevaluatedProperties: false

        Check out example 6.
--    - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave.
++    - Port 5 can be wired to an external phy. Port 5 becomes a DSA user port.
        For the multi-chip module MT7530, the external phy must be wired TX to TX
        to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired
  patternProperties:
    "^(ethernet-)?ports$":
      type: object
++    additionalProperties: true
      patternProperties:
--      "^(ethernet-)?port@[0-9]+$":
++      "^(ethernet-)?port@[0-6]$":
          type: object
++        additionalProperties: true
          properties:
            reg:
      patternProperties:
        "^(ethernet-)?ports$":
          patternProperties:
--          "^(ethernet-)?port@[0-9]+$":
++          "^(ethernet-)?port@[0-6]$":
              if:
                required: [ ethernet ]
              then:
      patternProperties:
        "^(ethernet-)?ports$":
          patternProperties:
--          "^(ethernet-)?port@[0-9]+$":
++          "^(ethernet-)?port@[0-6]$":
              if:
                required: [ ethernet ]
              then:

sys/contrib/device-tree/Bindings/net/dsa/microchip,ksz.yaml
@@ -38,6 +38,8 @@ properties:
	Should be a gpio specifier for a reset line.	Should be a gpio specifier for a reset line.
	maxItems: 1	maxItems: 1

		+ wakeup-source: true
		+
	microchip,synclko-125:	microchip,synclko-125:
	$ref: /schemas/types.yaml#/definitions/flag	$ref: /schemas/types.yaml#/definitions/flag
	description:	description:
@@ -49,6 +51,26 @@ properties:
	Set if the output SYNCLKO clock should be disabled. Do not mix with	Set if the output SYNCLKO clock should be disabled. Do not mix with
	microchip,synclko-125.	microchip,synclko-125.

		+ microchip,io-drive-strength-microamp:
		+ description:
		+ IO Pad Drive Strength
		+ enum: [8000, 16000]
		+ default: 16000
		+
		+ microchip,hi-drive-strength-microamp:
		+ description:
		+ High Speed Drive Strength. Controls drive strength of GMII / RGMII /
		+ MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines.
		+ enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]
		+ default: 24000
		+
		+ microchip,lo-drive-strength-microamp:
		+ description:
		+ Low Speed Drive Strength. Controls drive strength of TX_CLK / REFCLKI,
		+ COL, CRS, LEDs, PME_N, NTRP_N, SDO and SDI/SDA/MDIO lines.
		+ enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]
		+ default: 8000
		+
	interrupts:	interrupts:
	maxItems: 1	maxItems: 1

  patternProperties:
    "^(ethernet-)?ports$":
++    additionalProperties: true
      patternProperties:
--      "^(ethernet-)?port@[0-9]+$":
++      "^(ethernet-)?port@[0-7]$":
          allOf:
            - if:
                properties:

    # PHY 1.
    mdios:
      type: object
++    additionalProperties: false
      properties:
        '#address-cells':
  patternProperties:
    "^(ethernet-)?ports$":
++    additionalProperties: true
      patternProperties:
--      "^(ethernet-)?port@[0-9]+$":
++      "^(ethernet-)?port@[0-9]$":
          allOf:
            - if:
                properties:

  patternProperties:
    "^(ethernet-)?ports$":
      type: object
++    additionalProperties: true
      patternProperties:
        "^(ethernet-)?port@[0-6]$":
          type: object

    interrupt-controller:
      type: object
++    additionalProperties: false
++
      description: |
        This defines an interrupt controller with an IRQ line (typically
        a GPIO) that will demultiplex and handle the interrupt from the single

sys/contrib/device-tree/Bindings/net/dsa/renesas,rzn1-a5psw.yaml
@@ -61,17 +61,11 @@ properties:

	ethernet-ports:	ethernet-ports:
	type: object	type: object
	- ~~properties:~~	+ additionalProperties: true
	- '#address-cells':
	- const: 1
	- '#size-cells':
	- const: 0
	-
	patternProperties:	patternProperties:
	"^(ethernet-)?port@[0-4]$":	"^(ethernet-)?port@[0-4]$":
	type: object	type: object
	- ~~description:~~ ~~Ethernet switch ports~~	+ additionalProperties: true
	-
	properties:	properties:
	pcs-handle:	pcs-handle:
	maxItems: 1	maxItems: 1

    mdio:
      type: object
      $ref: mdio.yaml#
++    unevaluatedProperties: false
      description: optional node for embedded MDIO controller
  required:

        properties:
          rx-internal-delay-ps:
            description:
--            RGMII Receive Clock Delay defined in pico seconds.This is used for
++            RGMII Receive Clock Delay defined in pico seconds. This is used for
              controllers that have configurable RX internal delays. If this
              property is present then the MAC applies the RX delay.
          tx-internal-delay-ps:
            description:
--            RGMII Transmit Clock Delay defined in pico seconds.This is used for
++            RGMII Transmit Clock Delay defined in pico seconds. This is used for
              controllers that have configurable TX internal delays. If this
              property is present then the MAC applies the TX delay.

          const: 0
      patternProperties:
--      "^(ethernet-)?port@[0-9]+$":
++      "^(ethernet-)?port@[0-9a-f]+$":
          type: object
          description: Ethernet switch ports
  additionalProperties: true
  $defs:
--  base:
++  ethernet-ports:
      description: An ethernet switch without any extra port properties
      $ref: '#'
      patternProperties:
--      "^(ethernet-)?port@[0-9]+$":
++      "^(ethernet-)?ports$":
--        description: Ethernet switch ports
++        patternProperties:
--        $ref: ethernet-switch-port.yaml#
++          "^(ethernet-)?port@[0-9a-f]+$":
--        unevaluatedProperties: false
++            description: Ethernet switch ports
++            $ref: ethernet-switch-port.yaml#
++            unevaluatedProperties: false
  ...

            - const: fsl,imx6sx-fec
        - items:
            - enum:
++              - fsl,imx8dxl-fec
                - fsl,imx8qxp-fec
            - const: fsl,imx8qm-fec
            - const: fsl,imx6sx-fec

sys/contrib/device-tree/Bindings/net/loongson,ls1b-gmac.yaml
@@ -0,0 +1,114 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/net/loongson,ls1b-gmac.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Loongson-1B Gigabit Ethernet MAC Controller
			+
			+maintainers:
			+ - Keguang Zhang <keguang.zhang@gmail.com>
			+
			+description: \|
			+ Loongson-1B Gigabit Ethernet MAC Controller is based on
			+ Synopsys DesignWare MAC (version 3.50a).
			+
			+ Main features
			+ - Dual 10/100/1000Mbps GMAC controllers
			+ - Full-duplex operation (IEEE 802.3x flow control automatic transmission)
			+ - Half-duplex operation (CSMA/CD Protocol and back-pressure support)
			+ - RX Checksum Offload
			+ - TX Checksum insertion
			+ - MII interface
			+ - RGMII interface
			+
			+select:
			+ properties:
			+ compatible:
			+ contains:
			+ enum:
			+ - loongson,ls1b-gmac
			+ required:
			+ - compatible
			+
			+properties:
			+ compatible:
			+ items:
			+ - enum:
			+ - loongson,ls1b-gmac
			+ - const: snps,dwmac-3.50a
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ maxItems: 1
			+
			+ clock-names:
			+ items:
			+ - const: stmmaceth
			+
			+ interrupts:
			+ maxItems: 1
			+
			+ interrupt-names:
			+ items:
			+ - const: macirq
			+
			+ loongson,ls1-syscon:
			+ $ref: /schemas/types.yaml#/definitions/phandle
			+ description:
			+ Phandle to the syscon containing some extra configurations
			+ including PHY interface mode.
			+
			+ phy-mode:
			+ enum:
			+ - mii
			+ - rgmii-id
			+
			+required:
			+ - compatible
			+ - reg
			+ - clocks
			+ - clock-names
			+ - interrupts
			+ - interrupt-names
			+ - loongson,ls1-syscon
			+
			+allOf:
			+ - $ref: snps,dwmac.yaml#
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/loongson,ls1x-clk.h>
			+ #include <dt-bindings/interrupt-controller/irq.h>
			+
			+ gmac0: ethernet@1fe10000 {
			+ compatible = "loongson,ls1b-gmac", "snps,dwmac-3.50a";
			+ reg = <0x1fe10000 0x10000>;
			+
			+ clocks = <&clkc LS1X_CLKID_AHB>;
			+ clock-names = "stmmaceth";
			+
			+ interrupt-parent = <&intc1>;
			+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
			+ interrupt-names = "macirq";
			+
			+ loongson,ls1-syscon = <&syscon>;
			+
			+ phy-handle = <&phy0>;
			+ phy-mode = "mii";
			+ snps,pbl = <1>;
			+
			+ mdio {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+ compatible = "snps,dwmac-mdio";
			+
			+ phy0: ethernet-phy@0 {
			+ reg = <0x0>;
			+ };
			+ };
			+ };

sys/contrib/device-tree/Bindings/net/loongson,ls1c-emac.yaml
@@ -0,0 +1,113 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/net/loongson,ls1c-emac.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Loongson-1C Ethernet MAC Controller
			+
			+maintainers:
			+ - Keguang Zhang <keguang.zhang@gmail.com>
			+
			+description: \|
			+ Loongson-1C Ethernet MAC Controller is based on
			+ Synopsys DesignWare MAC (version 3.50a).
			+
			+ Main features
			+ - 10/100Mbps
			+ - Full-duplex operation (IEEE 802.3x flow control automatic transmission)
			+ - Half-duplex operation (CSMA/CD Protocol and back-pressure support)
			+ - IEEE 802.1Q VLAN tag detection for reception frames
			+ - MII interface
			+ - RMII interface
			+
			+select:
			+ properties:
			+ compatible:
			+ contains:
			+ enum:
			+ - loongson,ls1c-emac
			+ required:
			+ - compatible
			+
			+properties:
			+ compatible:
			+ items:
			+ - enum:
			+ - loongson,ls1c-emac
			+ - const: snps,dwmac-3.50a
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ maxItems: 1
			+
			+ clock-names:
			+ items:
			+ - const: stmmaceth
			+
			+ interrupts:
			+ maxItems: 1
			+
			+ interrupt-names:
			+ items:
			+ - const: macirq
			+
			+ loongson,ls1-syscon:
			+ $ref: /schemas/types.yaml#/definitions/phandle
			+ description:
			+ Phandle to the syscon containing some extra configurations
			+ including PHY interface mode.
			+
			+ phy-mode:
			+ enum:
			+ - mii
			+ - rmii
			+
			+required:
			+ - compatible
			+ - reg
			+ - clocks
			+ - clock-names
			+ - interrupts
			+ - interrupt-names
			+ - loongson,ls1-syscon
			+
			+allOf:
			+ - $ref: snps,dwmac.yaml#
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/loongson,ls1x-clk.h>
			+ #include <dt-bindings/interrupt-controller/irq.h>
			+
			+ emac: ethernet@1fe10000 {
			+ compatible = "loongson,ls1c-emac", "snps,dwmac-3.50a";
			+ reg = <0x1fe10000 0x10000>;
			+
			+ clocks = <&clkc LS1X_CLKID_AHB>;
			+ clock-names = "stmmaceth";
			+
			+ interrupt-parent = <&intc1>;
			+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
			+ interrupt-names = "macirq";
			+
			+ loongson,ls1-syscon = <&syscon>;
			+
			+ phy-handle = <&phy0>;
			+ phy-mode = "mii";
			+ snps,pbl = <1>;
			+
			+ mdio {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+ compatible = "snps,dwmac-mdio";
			+
			+ phy0: ethernet-phy@13 {
			+ reg = <0x13>;
			+ };
			+ };
			+ };

    local-mac-address: true
    mac-address: true
++  nvmem-cells: true
++  nvmem-cell-names: true
  required:
    - compatible

sys/contrib/device-tree/Bindings/net/mscc,vsc7514-switch.yaml
@@ -24,7 +24,7 @@ allOf:
	compatible:	compatible:
	const: mscc,vsc7514-switch	const: mscc,vsc7514-switch
	then:	then:
	- $ref: ethernet-switch.yaml#	+ $ref: ethernet-switch.yaml#/$defs/ethernet-ports
	required:	required:
	- interrupts	- interrupts
	- interrupt-names	- interrupt-names
@@ -33,28 +33,18 @@ allOf:
	minItems: 21	minItems: 21
	reg-names:	reg-names:
	minItems: 21	minItems: 21
	- ethernet-ports:
	- patternProperties:
	- "^port@[0-9a-f]+$":
	- $ref: ethernet-switch-port.yaml#
	- unevaluatedProperties: false

	- if:	- if:
	properties:	properties:
	compatible:	compatible:
	const: mscc,vsc7512-switch	const: mscc,vsc7512-switch
	then:	then:
	- $ref: /schemas/net/dsa/dsa.yaml#	+ $ref: /schemas/net/dsa/dsa.yaml#/$defs/ethernet-ports
	properties:	properties:
	reg:	reg:
	maxItems: 20	maxItems: 20
	reg-names:	reg-names:
	maxItems: 20	maxItems: 20
	- ethernet-ports:
	- patternProperties:
	- "^port@[0-9a-f]+$":
	- $ref: /schemas/net/dsa/dsa-port.yaml#
	- unevaluatedProperties: false

	properties:	properties:
	compatible:	compatible:
@@ -185,7 +175,7 @@ examples:
	};	};
	# VSC7512 (DSA)	# VSC7512 (DSA)
	- \|	- \|
	- ethernet-switch@1{	+ ethernet-switch@1 {
	compatible = "mscc,vsc7512-switch";	compatible = "mscc,vsc7512-switch";
	reg = <0x71010000 0x10000>,	reg = <0x71010000 0x10000>,
	<0x71030000 0x10000>,	<0x71030000 0x10000>,
@@ -212,22 +202,22 @@ examples:
	"port7", "port8", "port9", "port10", "qsys",	"port7", "port8", "port9", "port10", "qsys",
	"ana", "s0", "s1", "s2";	"ana", "s0", "s1", "s2";

	- ethernet-ports {	+ ethernet-ports {
	- #address-cells = <1>;	+ #address-cells = <1>;
	- #size-cells = <0>;	+ #size-cells = <0>;
	-	+
	- port@0 {	+ port@0 {
	- reg = <0>;	+ reg = <0>;
	- ethernet = <&mac_sw>;	+ ethernet = <&mac_sw>;
	- phy-handle = <&phy0>;	+ phy-handle = <&phy0>;
	- phy-mode = "internal";	+ phy-mode = "internal";
	- };	+ };
	- port@1 {	+ port@1 {
	- reg = <1>;	+ reg = <1>;
	- phy-handle = <&phy1>;	+ phy-handle = <&phy1>;
	- phy-mode = "internal";	+ phy-mode = "internal";
	- };
	};	};
	};	};
		+ };

	...	...

  patternProperties:
    "^ethernet-phy@[0-9a-f]+$":
      type: object
++    additionalProperties: false
      description: |
        Some packages have multiple PHYs. Secondary PHY should be defines as
        subnode of the first (parent) PHY.

        active-high
  patternProperties:
--  "^ethernet-phy@[0-9a-f]$":
++  "@[0-9a-f]$":
      type: object
--    $ref: ethernet-phy.yaml#
  required:
    - compatible

      enum: [0, 2000]
  patternProperties:
--  "^ethernet-phy@[0-9a-f]$":
++  "@[0-9a-f]$":
      type: object
--    $ref: ethernet-phy.yaml#
  required:
    - compatible

sys/contrib/device-tree/Bindings/net/snps,dwmac.yaml
@@ -394,6 +394,11 @@ properties:
	When a PFC frame is received with priorities matching the bitmask,	When a PFC frame is received with priorities matching the bitmask,
	the queue is blocked from transmitting for the pause time specified	the queue is blocked from transmitting for the pause time specified
	in the PFC frame.	in the PFC frame.
		+
		+ snps,coe-unsupported:
		+ type: boolean
		+ description: TX checksum offload is unsupported by the TX queue.
		+
	allOf:	allOf:
	- if:	- if:
	required:	required:

sys/contrib/device-tree/Bindings/net/ti,cc1352p7.yaml
@@ -0,0 +1,51 @@
			+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/net/ti,cc1352p7.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Texas Instruments Simplelink CC1352P7 wireless MCU
			+
			+description:
			+ The CC1352P7 MCU can be connected via SPI or UART.
			+
			+maintainers:
			+ - Ayush Singh <ayushdevel1325@gmail.com>
			+
			+properties:
			+ compatible:
			+ const: ti,cc1352p7
			+
			+ clocks:
			+ items:
			+ - description: high-frequency main system (MCU and peripherals) clock
			+ - description: low-frequency system clock
			+
			+ clock-names:
			+ items:
			+ - const: sclk_hf
			+ - const: sclk_lf
			+
			+ reset-gpios:
			+ maxItems: 1
			+
			+ vdds-supply: true
			+
			+required:
			+ - compatible
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/gpio/gpio.h>
			+
			+ serial {
			+ mcu {
			+ compatible = "ti,cc1352p7";
			+ clocks = <&sclk_hf 0>, <&sclk_lf 25>;
			+ clock-names = "sclk_hf", "sclk_lf";
			+ reset-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
			+ vdds-supply = <&vdds>;
			+ };
			+ };

          const: 0
      patternProperties:
--      "^port@[0-9]+$":
++      "^port@[12]$":
          type: object
          description: CPSW external ports

sys/contrib/device-tree/Bindings/net/ti,icssg-prueth.yaml
@@ -19,6 +19,7 @@ allOf:
	properties:	properties:
	compatible:	compatible:
	enum:	enum:
		+ - ti,am642-icssg-prueth # for AM64x SoC family
	- ti,am654-icssg-prueth # for AM65x SoC family	- ti,am654-icssg-prueth # for AM65x SoC family

	sram:	sram:
@@ -106,6 +107,13 @@ properties:
	phandle to system controller node and register offset	phandle to system controller node and register offset
	to ICSSG control register for RGMII transmit delay	to ICSSG control register for RGMII transmit delay

		+ ti,half-duplex-capable:
		+ type: boolean
		+ description:
		+ Indicates that the PHY output pin COL is routed to ICSSG GPIO pin
		+ (PRGx_PRU0/1_GPIO10) as input so that the ICSSG MII port is
		+ capable of half duplex operations.
		+
	required:	required:
	- reg	- reg
	anyOf:	anyOf:

  allOf:
    - $ref: nvmem.yaml#
++  - $ref: nvmem-deprecated-cells.yaml#
  properties:
    compatible:
        - const: allwinner,sun20i-d1-sid
        - const: allwinner,sun50i-a64-sid
        - items:
--          - const: allwinner,sun50i-a100-sid
++          - enum:
++              - allwinner,sun50i-a100-sid
++              - allwinner,sun50i-h616-sid
            - const: allwinner,sun50i-a64-sid
        - const: allwinner,sun50i-h5-sid
        - const: allwinner,sun50i-h6-sid

  allOf:
    - $ref: nvmem.yaml#
++  - $ref: nvmem-deprecated-cells.yaml#
  properties:
    compatible:

  allOf:
    - $ref: nvmem.yaml#
++  - $ref: nvmem-deprecated-cells.yaml#
  properties:
    compatible:

  allOf:
    - $ref: nvmem.yaml#
++  - $ref: nvmem-deprecated-cells.yaml#
  properties:
    compatible:

  allOf:
    - $ref: nvmem.yaml#
++  - $ref: nvmem-deprecated-cells.yaml#
  properties:
    compatible:

  allOf:
    - $ref: nvmem.yaml#
++  - $ref: nvmem-deprecated-cells.yaml#
  properties:
    $nodename:

  allOf:
    - $ref: nvmem.yaml#
++  - $ref: nvmem-deprecated-cells.yaml#
  properties:
    compatible:

  allOf:
    - $ref: nvmem.yaml#
++  - $ref: nvmem-deprecated-cells.yaml#
  properties:
    compatible:
--    enum:
++    items:
--      - fsl,imx23-ocotp
++      - enum:
--      - fsl,imx28-ocotp
++          - fsl,imx23-ocotp
++          - fsl,imx28-ocotp
++      - const: fsl,ocotp
    reg:
      maxItems: 1
  examples:
    - |
      ocotp: efuse@8002c000 {
--        compatible = "fsl,imx28-ocotp";
++        compatible = "fsl,imx28-ocotp", "fsl,ocotp";
          #address-cells = <1>;
          #size-cells = <1>;
          reg = <0x8002c000 0x2000>;

sys/contrib/device-tree/Bindings/nvmem/nvmem-deprecated-cells.yaml
@@ -0,0 +1,28 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/nvmem/nvmem-deprecated-cells.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: NVMEM old syntax for fixed cells
			+
			+maintainers:
			+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
			+
			+description: \|
			+ Before introducing NVMEM layouts all NVMEM (fixed) cells were defined
			+ as direct device subnodes. That syntax was replaced by "fixed-layout"
			+ and is deprecated now. No new bindings should use it.
			+
			+patternProperties:
			+ "@[0-9a-f]+(,[0-7])?$":
			+ type: object
			+ allOf:
			+ - $ref: layouts/fixed-cell.yaml
			+ - properties:
			+ compatible: false
			+ deprecated: true
			+
			+additionalProperties: true
			+
			+...

sys/contrib/device-tree/Bindings/nvmem/nvmem.yaml
[diff truncated]
@@ -46,15 +46,6 @@ properties:
	container may reference more advanced (dynamic) layout		container may reference more advanced (dynamic) layout