HardenedBSD / src / 705fc7f

  endif()
  add_compile_options($<$<CONFIG:Release>:-Wuninitialized>)
  add_compile_options($<$<CONFIG:Release>:-Wno-dangling-else>)
--add_compile_options(-Wno-string-compare)
  add_compile_options(-Wstack-protector -fstack-protector)
  add_compile_options(-Wstrict-aliasing -fstrict-aliasing)

  #include <db.h>
  #endif
  #include <regex.h>                /* May refer to the bundled regex. */
++#include <stdint.h>
  /*
   * Forward structure declarations.  Not pretty, but the include files

  #include <fcntl.h>
  #include <libgen.h>
  #include <limits.h>
--#include <stdint.h>
  #include <stdio.h>
  #include <stdlib.h>
  #include <string.h>

          {L("shellmeta"),        NULL,                OPT_STR,        0},
  /* O_SHIFTWIDTH            4BSD */
          {L("shiftwidth"),        NULL,                OPT_NUM,        OPT_NOZERO},
++/* O_SHOWFILENAME */
++        {L("showfilename"),        NULL,                OPT_0BOOL,        0},
  /* O_SHOWMATCH            4BSD */
          {L("showmatch"),        NULL,                OPT_0BOOL,        0},
  /* O_SHOWMODE          4.4BSD */
          /* Set numeric and string default values. */
  #define        OI(indx, str) do {                                                \
          a.len = STRLEN(str);                                                \
--        if ((CHAR_T*)str != b2)          /* GCC puts strings in text-space. */        \
++        if (STRCMP((CHAR_T*)str, b2) != 0)                                        \
                  (void)MEMCPY(b2, str, a.len+1);                                \
          if (opts_set(sp, argv, NULL)) {                                        \
                   optindx = indx;                                        \

  .\" that you would have purchased it, or if any company wishes to
  .\" redistribute it, contributions to the authors would be appreciated.
  .\"
--.Dd September 25, 2020
++.Dd April 18, 2024
  .Dt VI 1
  .Os
  .Sh NAME
--.Nm ex , vi , view
++.Nm ex ,
++.Nm vi ,
++.Nm view
  .Nd text editors
  .Sh SYNOPSIS
  .Nm ex
  (if you've modified the file, but not saved your changes,
  .Nm vi
  will refuse to quit).
--.It Cm :q!
++.It Cm :q\&!
  Quit, discarding any modifications that you may have made.
  .El
  .Pp
  .Nm ex
  command being entered, or cancel it if it is only partial.
  .Pp
--.It Aq Cm control-]
++.It Aq Cm control-\(rB
  Push a tag reference onto the tag stack.
  .Pp
  .It Aq Cm control-\(ha
  to the position of the cursor before the last of the following commands:
  .Aq Cm control-A ,
  .Aq Cm control-T ,
--.Aq Cm control-] ,
++.Aq Cm control-\(rB ,
  .Cm % ,
  .Cm \(aq ,
  .Cm \` ,
  .Op Ar +cmd
  .Op Ar file
  .Xc
--Edit a different file. The capitalized command opens a new screen below the
++Edit a different file.
--current screen.
++The capitalized command opens a new screen below the current screen.
  .Pp
  .It Xo
  .Cm exu Ns Op Cm sage
  .Xc
  .Nm vi
  mode only.
--Foreground the specified screen. The capitalized command opens a new screen
++Foreground the specified screen.
--below the current screen.
++The capitalized command opens a new screen below the current screen.
  .Pp
  .It Xo
  .Op Ar range
  .Op Cm !\&
  .Op Ar
  .Xc
--Edit the next file from the argument list. The capitalized command opens a
++Edit the next file from the argument list.
--new screen below the current screen.
++The capitalized command opens a new screen below the current screen.
  .\" .Pp
  .\" .It Xo
  .\" .Op Ar line
  .Cm rev Ns Op Cm ious Ns
  .Op Cm !\&
  .Xc
--Edit the previous file from the argument list. The capitalized command opens
++Edit the previous file from the argument list.
--a new screen below the current screen.
++The capitalized command opens a new screen below the current screen.
  .Pp
  .It Xo
  .Op Ar range
  .Op Cm !\&
  .Ar tagstring
  .Xc
--Edit the file containing the specified tag. The capitalized command opens a
++Edit the file containing the specified tag.
--new screen below the current screen.
++The capitalized command opens a new screen below the current screen.
  .Pp
  .It Xo
  .Cm tagn Ns Op Cm ext Ns
  .Op Ar file
  .Xc
  .Nm vi
--mode only. Edit a different file by opening a new screen below the current
++mode only.
--screen.
++Edit a different file by opening a new screen below the current screen.
  .Pp
  .It Xo
  .Cm viu Ns Op Cm sage
  .Sq !\&
  overwrites a different, preexisting file.
  .Sq >>
--appends to a file that may preexist. Whitespace followed by
++appends to a file that may preexist.
++Whitespace followed by
  .Sq !\&
  pipes the file to
  .Ar shell-command .
  .It Cm ruler Bq off
  .Nm vi
  only.
--Display a row/column ruler on the colon command line.
++Display a row/column/percentage ruler on the colon command line.
  .It Cm scroll , scr Bq "window size / 2"
  Set the number of lines scrolled.
  .It Cm searchincr Bq off
  is necessary.
  .It Cm shiftwidth , sw Bq 8
  Set the autoindent and shift command indentation width.
++.It Cm showfilename Bq off
++.Nm vi
++only.
++Display the file name on the colon command line.
  .It Cm showmatch , sm Bq off
  .Nm vi
  only.
  .Xr ctags 1 ,
  .Xr iconv 1 ,
  .Xr re_format 7
--.Rs
++.Pp
--.%T vi/ex reference manual
++.Lk https://docs.freebsd.org/44doc/usd/13.viref/paper.pdf "Vi/Ex Reference Manual"
--.%U https://docs.freebsd.org/44doc/usd/13.viref/paper.pdf
--.Re
  .Sh STANDARDS
  .Nm nex Ns / Ns Nm nvi
  is close to

contrib/nvi/vi/vs_refresh.c
@@ -774,7 +774,8 @@ vs_modeline(SCR *sp)
	size_t cols, curcol, curlen, endpoint, len, midpoint;	size_t cols, curcol, curlen, endpoint, len, midpoint;
	const char *t = NULL;	const char *t = NULL;
	int ellipsis;	int ellipsis;
	- char buf[20];	+ char buf[30];
		+ recno_t last;

	gp = sp->gp;	gp = sp->gp;

@@ -795,7 +796,7 @@ vs_modeline(SCR *sp)

	/* If more than one screen in the display, show the file name. */	/* If more than one screen in the display, show the file name. */
	curlen = 0;	curlen = 0;
	- if (IS_SPLIT(sp)) {	+ if (IS_SPLIT(sp) \|\| O_ISSET(sp, O_SHOWFILENAME)) {
	CHAR_T wp, p;	CHAR_T wp, p;
	size_t l;	size_t l;

@@ -846,8 +847,14 @@ vs_modeline(SCR *sp)
	cols = sp->cols - 1;	cols = sp->cols - 1;
	if (O_ISSET(sp, O_RULER)) {	if (O_ISSET(sp, O_RULER)) {
	vs_column(sp, &curcol);	vs_column(sp, &curcol);
	- len = snprintf(buf, sizeof(buf), "%lu,%lu",	+
	- (u_long)sp->lno, (u_long)(curcol + 1));	+ if (db_last(sp, &last) \|\| last == 0)
		+ len = snprintf(buf, sizeof(buf), "%lu,%zu",
		+ (u_long)sp->lno, curcol + 1);
		+ else
		+ len = snprintf(buf, sizeof(buf), "%lu,%zu %lu%%",
		+ (u_long)sp->lno, curcol + 1,
		+ (u_long)(sp->lno * 100) / last);

	midpoint = (cols - ((len + 1) / 2)) / 2;	midpoint = (cols - ((len + 1) / 2)) / 2;
	if (curlen < midpoint) {	if (curlen < midpoint) {

sys/contrib/device-tree/Bindings/Makefile
@@ -25,23 +25,25 @@ quiet_cmd_extract_ex = DTEX $@
	$(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE	$(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
	$(call if_changed,extract_ex)	$(call if_changed,extract_ex)

	-find_all_cmd = find $(~~srctree)/$(~~src) \( -name '*.yaml' ! \	+find_all_cmd = find $(src) \( -name '*.yaml' ! \
	-name 'processed-schema*' \)	-name 'processed-schema*' \)

	find_cmd = $(find_all_cmd) \| \	find_cmd = $(find_all_cmd) \| \
	sed 's\|^$(srctree)/\|\|' \| \	sed 's\|^$(srctree)/\|\|' \| \
	grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))" \| \	grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))" \| \
	sed 's\|^\|$(srctree)/\|'	sed 's\|^\|$(srctree)/\|'
	-CHK_DT_DOCS := $(shell $(find_cmd))	+CHK_DT_EXAMPLES := $(patsubst $(srctree)/%.yaml,%.example.dtb, $(shell $(find_cmd)))

	quiet_cmd_yamllint = LINT $(src)	quiet_cmd_yamllint = LINT $(src)
	cmd_yamllint = ($(find_cmd) \| \	cmd_yamllint = ($(find_cmd) \| \
	xargs -n200 -P$$(nproc) \	xargs -n200 -P$$(nproc) \
	- $(DT_SCHEMA_LINT) -f parsable -c $(~~srctree)/$(~~src)/.yamllint >&2) ~~\|\| true~~	+ $(DT_SCHEMA_LINT) -f parsable -c $(src)/.yamllint >&2) \
		+ && touch $@ \|\| true

	-quiet_cmd_chk_bindings = CHKDT $@	+quiet_cmd_chk_bindings = CHKDT $(src)
	cmd_chk_bindings = ($(find_cmd) \| \	cmd_chk_bindings = ($(find_cmd) \| \
	- xargs -n200 -P$$(nproc) $(DT_DOC_CHECKER) -u $(srctree)/$(src)) \|\| true	+ xargs -n200 -P$$(nproc) $(DT_DOC_CHECKER) -u $(src)) \
		+ && touch $@ \|\| true

	quiet_cmd_mk_schema = SCHEMA $@	quiet_cmd_mk_schema = SCHEMA $@
	cmd_mk_schema = f=$$(mktemp) ; \	cmd_mk_schema = f=$$(mktemp) ; \
@@ -49,12 +51,6 @@ quiet_cmd_mk_schema = SCHEMA $@
	$(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \	$(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \
	rm -f $$f	rm -f $$f

	-define rule_chkdt
	- $(if $(DT_SCHEMA_LINT),$(call cmd,yamllint),)
	- $(call cmd,chk_bindings)
	- $(call cmd,mk_schema)
	-endef
	-
	DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd)))	DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd)))

	override DTC_FLAGS := \	override DTC_FLAGS := \
@@ -64,15 +60,19 @@ override DTC_FLAGS := \
	-Wno-unique_unit_address \	-Wno-unique_unit_address \
	-Wunique_unit_address_if_enabled	-Wunique_unit_address_if_enabled

	-# Disable undocumented compatible checks until warning free	+$(obj)/processed-schema.json: $(DT_DOCS) check_dtschema_version FORCE
	-override DT_CHECKER_FLAGS ?=	+ $(call if_changed,mk_schema)
		+
		+targets += .dt-binding.checked .yamllint.checked
		+$(obj)/.yamllint.checked: $(DT_DOCS) $(src)/.yamllint FORCE
		+ $(if $(DT_SCHEMA_LINT),$(call if_changed,yamllint),)

	-$(obj)/processed-schema.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE	+$(obj)/.dt-binding.checked: $(DT_DOCS) FORCE
	- $(call ~~if_changed_rule~~,~~chkdt~~)	+ $(call if_changed,chk_bindings)

	always-y += processed-schema.json	always-y += processed-schema.json
	-always-$(CHECK_DT_BINDING) += $(patsubst $(srctree)/$(src)/%.yaml,%.example.dts, $(CHK_DT_DOCS))	+targets += $(patsubst $(obj)/%,%, $(CHK_DT_EXAMPLES))
	-always-$(CHECK_DT_BINDING) += $(patsubst $(srctree)/$(src)/%.yaml,%.example.dtb, $(CHK_DT_DOCS))	+targets += $(patsubst $(obj)/%.dtb,%.dts, $(CHK_DT_EXAMPLES))

	# Hack: avoid 'Argument list too long' error for 'make clean'. Remove most of	# Hack: avoid 'Argument list too long' error for 'make clean'. Remove most of
	# build artifacts here before they are processed by scripts/Makefile.clean	# build artifacts here before they are processed by scripts/Makefile.clean
@@ -81,3 +81,6 @@ clean-files = $(shell find $(obj) \( -name '*.example.dts' -o \

	dt_compatible_check: $(obj)/processed-schema.json	dt_compatible_check: $(obj)/processed-schema.json
	$(Q)$(srctree)/scripts/dtc/dt-extract-compatibles $(srctree) \| xargs dt-check-compatible -v -s $<	$(Q)$(srctree)/scripts/dtc/dt-extract-compatibles $(srctree) \| xargs dt-check-compatible -v -s $<
		+
		+PHONY += dt_binding_check
		+dt_binding_check: $(obj)/.dt-binding.checked $(obj)/.yamllint.checked $(CHK_DT_EXAMPLES)

sys/contrib/device-tree/Bindings/access-controllers/access-controllers.yaml
@@ -0,0 +1,84 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/access-controllers/access-controllers.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Generic Domain Access Controllers
			+
			+maintainers:
			+ - Oleksii Moisieiev <oleksii_moisieiev@epam.com>
			+
			+description: \|+
			+ Common access controllers properties
			+
			+ Access controllers are in charge of stating which of the hardware blocks under
			+ their responsibility (their domain) can be accesssed by which compartment. A
			+ compartment can be a cluster of CPUs (or coprocessors), a range of addresses
			+ or a group of hardware blocks. An access controller's domain is the set of
			+ resources covered by the access controller.
			+
			+ This device tree binding can be used to bind devices to their access
			+ controller provided by access-controllers property. In this case, the device
			+ is a consumer and the access controller is the provider.
			+
			+ An access controller can be represented by any node in the device tree and
			+ can provide one or more configuration parameters, needed to control parameters
			+ of the consumer device. A consumer node can refer to the provider by phandle
			+ and a set of phandle arguments, specified by '#access-controller-cells'
			+ property in the access controller node.
			+
			+ Access controllers are typically used to set/read the permissions of a
			+ hardware block and grant access to it. Any of which depends on the access
			+ controller. The capabilities of each access controller are defined by the
			+ binding of the access controller device.
			+
			+ Each node can be a consumer for the several access controllers.
			+
			+# always select the core schema
			+select: true
			+
			+properties:
			+ "#access-controller-cells":
			+ description:
			+ Number of cells in an access-controllers specifier;
			+ Can be any value as specified by device tree binding documentation
			+ of a particular provider. The node is an access controller.
			+
			+ access-controller-names:
			+ $ref: /schemas/types.yaml#/definitions/string-array
			+ description:
			+ A list of access-controllers names, sorted in the same order as
			+ access-controllers entries. Consumer drivers will use
			+ access-controller-names to match with existing access-controllers entries.
			+
			+ access-controllers:
			+ $ref: /schemas/types.yaml#/definitions/phandle-array
			+ description:
			+ A list of access controller specifiers, as defined by the
			+ bindings of the access-controllers provider.
			+
			+additionalProperties: true
			+
			+examples:
			+ - \|
			+ clock_controller: access-controllers@50000 {
			+ reg = <0x50000 0x400>;
			+ #access-controller-cells = <2>;
			+ };
			+
			+ bus_controller: bus@60000 {
			+ reg = <0x60000 0x10000>;
			+ #address-cells = <1>;
			+ #size-cells = <1>;
			+ ranges;
			+ #access-controller-cells = <3>;
			+
			+ uart4: serial@60100 {
			+ reg = <0x60100 0x400>;
			+ clocks = <&clk_serial>;
			+ access-controllers = <&clock_controller 1 2>,
			+ <&bus_controller 1 3 5>;
			+ access-controller-names = "clock", "bus";
			+ };
			+ };

sys/contrib/device-tree/Bindings/arc/snps,archs-pct.yaml
@@ -0,0 +1,33 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/arc/snps,archs-pct.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: ARC HS Performance Counters
			+
			+maintainers:
			+ - Aryabhatta Dey <aryabhattadey35@gmail.com>
			+
			+description:
			+ The ARC HS can be configured with a pipeline performance monitor for counting
			+ CPU and cache events like cache misses and hits. Like conventional PCT there
			+ are 100+ hardware conditions dynamically mapped to up to 32 counters.
			+ It also supports overflow interrupts.
			+
			+properties:
			+ compatible:
			+ const: snps,archs-pct
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ maxItems: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - clocks
			+
			+additionalProperties: false

sys/contrib/device-tree/Bindings/arm/airoha.yaml
@@ -22,6 +22,10 @@ properties:
	- enum:	- enum:
	- airoha,en7523-evb	- airoha,en7523-evb
	- const: airoha,en7523	- const: airoha,en7523
		+ - items:
		+ - enum:
		+ - airoha,en7581-evb
		+ - const: airoha,en7581

	additionalProperties: true	additionalProperties: true

sys/contrib/device-tree/Bindings/arm/amlogic.yaml
@@ -7,19 +7,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
	title: Amlogic SoC based Platforms	title: Amlogic SoC based Platforms

	maintainers:	maintainers:
		+ - Neil Armstrong <neil.armstrong@linaro.org>
		+ - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
		+ - Jerome Brunet <jbrunet@baylibre.com>
	- Kevin Hilman <khilman@baylibre.com>	- Kevin Hilman <khilman@baylibre.com>

	-description: \|+
	- Work in progress statement:
	-
	- Device tree files and bindings applying to Amlogic SoCs and boards are
	- considered "unstable". Any Amlogic device tree binding may change at
	- any time. Be sure to use a device tree binary and a kernel image
	- generated from the same source tree.
	-
	- Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
	- stable binding/ABI.
	-
	properties:	properties:
	$nodename:	$nodename:
	const: '/'	const: '/'
@@ -99,6 +91,7 @@ properties:
	- libretech,aml-s905x-cc	- libretech,aml-s905x-cc
	- libretech,aml-s905x-cc-v2	- libretech,aml-s905x-cc-v2
	- nexbox,a95x	- nexbox,a95x
		+ - osmc,vero4k
	- const: amlogic,s905x	- const: amlogic,s905x
	- const: amlogic,meson-gxl	- const: amlogic,meson-gxl

@@ -115,6 +108,13 @@ properties:
	- const: amlogic,s905d	- const: amlogic,s905d
	- const: amlogic,meson-gxl	- const: amlogic,meson-gxl

		+ - description: Boards with the Amlogic Meson GXLX S905L SoC
		+ items:
		+ - enum:
		+ - amlogic,p271
		+ - const: amlogic,s905l
		+ - const: amlogic,meson-gxlx
		+
	- description: Boards with the Amlogic Meson GXM S912 SoC	- description: Boards with the Amlogic Meson GXM S912 SoC
	items:	items:
	- enum:	- enum:
@@ -146,6 +146,7 @@ properties:
	- enum:	- enum:
	- amediatech,x96-max	- amediatech,x96-max
	- amlogic,u200	- amlogic,u200
		+ - freebox,fbx8am
	- radxa,zero	- radxa,zero
	- seirobotics,sei510	- seirobotics,sei510
	- const: amlogic,g12a	- const: amlogic,g12a
@@ -164,6 +165,7 @@ properties:
	items:	items:
	- enum:	- enum:
	- bananapi,bpi-cm4io	- bananapi,bpi-cm4io
		+ - mntre,reform2-cm4
	- const: bananapi,bpi-cm4	- const: bananapi,bpi-cm4
	- const: amlogic,a311d	- const: amlogic,a311d
	- const: amlogic,g12b	- const: amlogic,g12b
@@ -175,6 +177,8 @@ properties:
	- azw,gtking	- azw,gtking
	- azw,gtking-pro	- azw,gtking-pro
	- bananapi,bpi-m2s	- bananapi,bpi-m2s
		+ - dream,dreambox-one
		+ - dream,dreambox-two
	- hardkernel,odroid-go-ultra	- hardkernel,odroid-go-ultra
	- hardkernel,odroid-n2	- hardkernel,odroid-n2
	- hardkernel,odroid-n2l	- hardkernel,odroid-n2l
@@ -208,6 +212,18 @@ properties:
	- amlogic,ad402	- amlogic,ad402
	- const: amlogic,a1	- const: amlogic,a1

		+ - description: Boards with the Amlogic A4 A113L2 SoC
		+ items:
		+ - enum:
		+ - amlogic,ba400
		+ - const: amlogic,a4
		+
		+ - description: Boards with the Amlogic A5 A113X2 SoC
		+ items:
		+ - enum:
		+ - amlogic,av400
		+ - const: amlogic,a5
		+
	- description: Boards with the Amlogic C3 C302X/C308L SoC	- description: Boards with the Amlogic C3 C302X/C308L SoC
	items:	items:
	- enum:	- enum:

sys/contrib/device-tree/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
@@ -25,10 +25,18 @@ select:

	properties:	properties:
	compatible:	compatible:
	- items:	+ oneOf:
	- - const: amlogic,meson-gx-ao-secure	+ - items:
	- - const: syscon	+ - const: amlogic,meson-gx-ao-secure
	-	+ - const: syscon
		+ - items:
		+ - enum:
		+ - amlogic,a4-ao-secure
		+ - amlogic,c3-ao-secure
		+ - amlogic,s4-ao-secure
		+ - amlogic,t7-ao-secure
		+ - const: amlogic,meson-gx-ao-secure
		+ - const: syscon
	reg:	reg:
	maxItems: 1	maxItems: 1

  maintainers:
    - Mike Leach <mike.leach@linaro.org>
    - Suzuki K Poulose <suzuki.poulose@arm.com>
--  - James Clark <james.clark@arm.com>
++  - James Clark <james.clark@linaro.org>
    - Mao Jinlong <quic_jinlmao@quicinc.com>
    - Hao Zhang <quic_hazha@quicinc.com>

    The Coresight dummy source component is for the specific coresight source
    devices kernel don't have permission to access or configure. For some SOCs,
    there would be Coresight source trace components on sub-processor which
--  are conneted to AP processor via debug bus. For these devices, a dummy driver
++  are connected to AP processor via debug bus. For these devices, a dummy driver
    is needed to register them as Coresight source devices, so that paths can be
    created in the driver. It provides Coresight API for operations on dummy
    source devices, such as enabling and disabling them. It also provides the
  maintainers:
    - Mike Leach <mike.leach@linaro.org>
    - Suzuki K Poulose <suzuki.poulose@arm.com>
--  - James Clark <james.clark@arm.com>
++  - James Clark <james.clark@linaro.org>
    - Mao Jinlong <quic_jinlmao@quicinc.com>
    - Hao Zhang <quic_hazha@quicinc.com>

  title: ARM Corstone1000
  maintainers:
--  - Vishnu Banavath <vishnu.banavath@arm.com>
++  - Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
--  - Rui Miguel Silva <rui.silva@linaro.org>
++  - Hugues Kamba Mpiana <hugues.kambampiana@arm.com>
  description: |+
    ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that

sys/contrib/device-tree/Bindings/arm/arm,juno-fpga-apb-regs.yaml
@@ -0,0 +1,61 @@
			+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/arm/arm,juno-fpga-apb-regs.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: ARM Juno FPGA APB Registers
			+
			+maintainers:
			+ - Sudeep Holla <sudeep.holla@arm.com>
			+
			+properties:
			+ compatible:
			+ items:
			+ - const: arm,juno-fpga-apb-regs
			+ - const: syscon
			+ - const: simple-mfd
			+
			+ reg:
			+ maxItems: 1
			+
			+ ranges: true
			+
			+ "#address-cells":
			+ const: 1
			+
			+ "#size-cells":
			+ const: 1
			+
			+patternProperties:
			+ "^led@[0-9a-f]+,[0-9a-f]$":
			+ $ref: /schemas/leds/register-bit-led.yaml#
			+
			+required:
			+ - compatible
			+ - reg
			+ - ranges
			+ - "#address-cells"
			+ - "#size-cells"
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ syscon@10000 {
			+ compatible = "arm,juno-fpga-apb-regs", "syscon", "simple-mfd";
			+ reg = <0x010000 0x1000>;
			+ ranges = <0x0 0x10000 0x1000>;
			+ #address-cells = <1>;
			+ #size-cells = <1>;
			+
			+ led@8,0 {
			+ compatible = "register-bit-led";
			+ reg = <0x08 0x04>;
			+ offset = <0x08>;
			+ mask = <0x01>;
			+ label = "vexpress:0";
			+ linux,default-trigger = "heartbeat";
			+ default-state = "on";
			+ };
			+ };

    - Linus Walleij <linus.walleij@linaro.org>
  description: |+
--  The ARM RealView series of reference designs were built to explore the ARM
++  The ARM RealView series of reference designs were built to explore the Arm11,
--  11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
++  Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the
--  the earlier CPUs such as TrustZone and multicore (MPCore).
++  earlier CPUs such as TrustZone and multicore (MPCore).
  properties:
    $nodename:

                - ampere,mtjade-bmc
                - aspeed,ast2500-evb
                - asrock,e3c246d4i-bmc
++              - asrock,e3c256d4i-bmc
                - asrock,romed8hm3-bmc
++              - asrock,spc621d8hm3-bmc
++              - asrock,x570d4u-bmc
                - bytedance,g220a-bmc
                - facebook,cmm-bmc
                - facebook,minipack-bmc
                - ampere,mtmitchell-bmc
                - aspeed,ast2600-evb
                - aspeed,ast2600-evb-a1
++              - asus,x4tf-bmc
                - facebook,bletchley-bmc
++              - facebook,catalina-bmc
                - facebook,cloudripper-bmc
                - facebook,elbert-bmc
                - facebook,fuji-bmc
                - facebook,greatlakes-bmc
++              - facebook,harma-bmc
                - facebook,minerva-cmc
                - facebook,yosemite4-bmc
++              - ibm,blueridge-bmc
                - ibm,everest-bmc
++              - ibm,fuji-bmc
                - ibm,rainier-bmc
++              - ibm,system1-bmc
                - ibm,tacoma-bmc
                - inventec,starscream-bmc
                - inventec,transformer-bmc

sys/contrib/device-tree/Bindings/arm/atmel-at91.yaml
@@ -179,6 +179,12 @@ properties:
	- const: microchip,sama7g5	- const: microchip,sama7g5
	- const: microchip,sama7	- const: microchip,sama7

		+ - description: Microchip SAMA7G54 Curiosity Board
		+ items:
		+ - const: microchip,sama7g54-curiosity
		+ - const: microchip,sama7g5
		+ - const: microchip,sama7
		+
	- description: Microchip LAN9662 Evaluation Boards.	- description: Microchip LAN9662 Evaluation Boards.
	items:	items:
	- enum:	- enum:

sys/contrib/device-tree/Bindings/arm/atmel-sysregs.txt
@@ -11,7 +11,8 @@ PIT Timer required properties:
	shared across all System Controller members.	shared across all System Controller members.

	PIT64B Timer required properties:	PIT64B Timer required properties:
	-- compatible: Should be "microchip,sam9x60-pit64b"	+- compatible: Should be "microchip,sam9x60-pit64b" or
		+ "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"
	- reg: Should contain registers location and length	- reg: Should contain registers location and length
	- interrupts: Should contain interrupt for PIT64B timer	- interrupts: Should contain interrupt for PIT64B timer
	- clocks: Should contain the available clock sources for PIT64B timer.	- clocks: Should contain the available clock sources for PIT64B timer.
@@ -31,7 +32,8 @@ RAMC SDRAM/DDR Controller required properties:
	"atmel,at91sam9g45-ddramc",	"atmel,at91sam9g45-ddramc",
	"atmel,sama5d3-ddramc",	"atmel,sama5d3-ddramc",
	"microchip,sam9x60-ddramc",	"microchip,sam9x60-ddramc",
	- "microchip,sama7g5-uddrc"	+ "microchip,sama7g5-uddrc",
		+ "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc".
	- reg: Should contain registers location and length	- reg: Should contain registers location and length

	Examples:	Examples:
@@ -41,35 +43,6 @@ Examples:
	reg = <0xffffe800 0x200>;	reg = <0xffffe800 0x200>;
	};	};

	-RAMC PHY Controller required properties:
	-- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon"
	-- reg: Should contain registers location and length
	-
	-Example:
	-
	- ddr3phy: ddr3phy@e3804000 {
	- compatible = "microchip,sama7g5-ddr3phy", "syscon";
	- reg = <0xe3804000 0x1000>;
	-};
	-
	-Special Function Registers (SFR)
	-
	-Special Function Registers (SFR) manage specific aspects of the integrated
	-memory, bridge implementations, processor and other functionality not controlled
	-elsewhere.
	-
	-required properties:
	-- compatible: Should be "atmel,<chip>-sfr", "syscon" or
	- "atmel,<chip>-sfrbu", "syscon"
	- <chip> can be "sama5d3", "sama5d4" or "sama5d2".
	- It also can be "microchip,sam9x60-sfr", "syscon".
	-- reg: Should contain registers location and length
	-
	- sfr@f0038000 {
	- compatible = "atmel,sama5d3-sfr", "syscon";
	- reg = <0xf0038000 0x60>;
	- };
	-
	Security Module (SECUMOD)	Security Module (SECUMOD)

	The Security Module macrocell provides all necessary secure functions to avoid	The Security Module macrocell provides all necessary secure functions to avoid

sys/contrib/device-tree/Bindings/arm/axis.txt
@@ -7,22 +7,6 @@ ARTPEC-6 ARM SoC
	Required root node properties:	Required root node properties:
	- compatible = "axis,artpec6";	- compatible = "axis,artpec6";

	-ARTPEC-6 System Controller
	---------------------------
	-
	-The ARTPEC-6 has a system controller with mixed functions controlling DMA, PCIe
	-and resets.
	-
	-Required properties:
	-- compatible: "axis,artpec6-syscon", "syscon"
	-- reg: Address and length of the register bank.
	-
	-Example:
	- syscon {
	- compatible = "axis,artpec6-syscon", "syscon";
	- reg = <0xf8000000 0x48>;
	- };
	-
	ARTPEC-6 Development board:	ARTPEC-6 Development board:
	---------------------------	---------------------------
	Required root node properties:	Required root node properties:

sys/contrib/device-tree/Bindings/arm/bcm/bcm2835.yaml
@@ -23,6 +23,12 @@ properties:
	- raspberrypi,4-model-b	- raspberrypi,4-model-b
	- const: brcm,bcm2711	- const: brcm,bcm2711

		+ - description: BCM2712 based Boards
		+ items:
		+ - enum:
		+ - raspberrypi,5-model-b
		+ - const: brcm,bcm2712
		+
	- description: BCM2835 based Boards	- description: BCM2835 based Boards
	items:	items:
	- enum:	- enum:

        - description: BCM4709 based boards
          items:
            - enum:
++              - asus,rt-ac3200
                - asus,rt-ac87u
                - buffalo,wxr-1900dhp
                - linksys,ea9200
          items:
            - enum:
                - asus,rt-ac3100
++              - asus,rt-ac5300
                - asus,rt-ac88u
                - dlink,dir-885l
                - dlink,dir-890l

sys/contrib/device-tree/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
@@ -46,6 +46,30 @@ properties:
	- compatible	- compatible
	- "#clock-cells"	- "#clock-cells"

		+ gpio:
		+ type: object
		+ additionalProperties: false
		+
		+ properties:
		+ compatible:
		+ const: raspberrypi,firmware-gpio
		+
		+ gpio-controller: true
		+
		+ "#gpio-cells":
		+ const: 2
		+ description:
		+ The first cell is the pin number, and the second cell is used to
		+ specify the gpio polarity (GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW).
		+
		+ gpio-line-names:
		+ minItems: 8
		+
		+ required:
		+ - compatible
		+ - gpio-controller
		+ - "#gpio-cells"
		+
	reset:	reset:
	type: object	type: object
	additionalProperties: false	additionalProperties: false
@@ -96,6 +120,12 @@ examples:
	#clock-cells = <1>;	#clock-cells = <1>;
	};	};

		+ expgpio: gpio {
		+ compatible = "raspberrypi,firmware-gpio";
		+ gpio-controller;
		+ #gpio-cells = <2>;
		+ };
		+
	reset: reset {	reset: reset {
	compatible = "raspberrypi,firmware-reset";	compatible = "raspberrypi,firmware-reset";
	#reset-cells = <1>;	#reset-cells = <1>;

sys/contrib/device-tree/Bindings/arm/cirrus/cirrus,ep9301.yaml
@@ -0,0 +1,38 @@
			+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/arm/cirrus/cirrus,ep9301.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Cirrus Logic EP93xx platforms
			+
			+description:
			+ The EP93xx SoC is a ARMv4T-based with 200 MHz ARM9 CPU.
			+
			+maintainers:
			+ - Alexander Sverdlin <alexander.sverdlin@gmail.com>
			+ - Nikita Shubin <nikita.shubin@maquefel.me>
			+
			+properties:
			+ $nodename:
			+ const: '/'
			+ compatible:
			+ oneOf:
			+ - description: The TS-7250 is a compact, full-featured Single Board
			+ Computer (SBC) based upon the Cirrus EP9302 ARM9 CPU
			+ items:
			+ - const: technologic,ts7250
			+ - const: cirrus,ep9301
			+
			+ - description: The Liebherr BK3 is a derivate from ts7250 board
			+ items:
			+ - const: liebherr,bk3
			+ - const: cirrus,ep9301
			+
			+ - description: EDB302 is an evaluation board by Cirrus Logic,
			+ based on a Cirrus Logic EP9302 CPU
			+ items:
			+ - const: cirrus,edb9302
			+ - const: cirrus,ep9301
			+
			+additionalProperties: true

sys/contrib/device-tree/Bindings/arm/cpu-enable-method/al,alpine-smp
@@ -27,16 +27,6 @@ Properties:
	- reg : Offset and length of the register set for the device	- reg : Offset and length of the register set for the device


	-* Alpine System-Fabric Service Registers
	-
	-The System-Fabric Service Registers allow various operation on CPU and
	-system fabric, like powering CPUs off.
	-
	-Properties:
	-- compatible : Should contain "al,alpine-sysfabric-service" and "syscon".
	-- reg : Offset and length of the register set for the device
	-
	-
	Example:	Example:

	cpus {	cpus {

        - arm,cortex-a710
        - arm,cortex-a715
        - arm,cortex-a720
++      - arm,cortex-a725
        - arm,cortex-m0
        - arm,cortex-m0+
        - arm,cortex-m1
        - arm,cortex-x2
        - arm,cortex-x3
        - arm,cortex-x4
++      - arm,cortex-x925
        - arm,neoverse-e1
        - arm,neoverse-n1
        - arm,neoverse-n2
++      - arm,neoverse-n3
        - arm,neoverse-v1
++      - arm,neoverse-v2
++      - arm,neoverse-v3
++      - arm,neoverse-v3ae
        - brcm,brahma-b15
        - brcm,brahma-b53
        - brcm,vulcan

  title: Freescale i.MX7ULP System Integration Module
  maintainers:
--  - Anson Huang <anson.huang@nxp.com>
++  - Shawn Guo <shawnguo@kernel.org>
++  - Sascha Hauer <s.hauer@pengutronix.de>
++  - Fabio Estevam <festevam@gmail.com>
  description: |
    The system integration module (SIM) provides system control and chip configuration

sys/contrib/device-tree/Bindings/arm/fsl.yaml
@@ -8,7 +8,6 @@ title: Freescale i.MX Platforms

	maintainers:	maintainers:
	- Shawn Guo <shawnguo@kernel.org>	- Shawn Guo <shawnguo@kernel.org>
	- - Li Yang <leoyang.li@nxp.com>

	properties:	properties:
	$nodename:	$nodename:
@@ -363,6 +362,12 @@ properties:
	- const: gw,ventana	- const: gw,ventana
	- const: fsl,imx6q	- const: fsl,imx6q

		+ - description: i.MX6Q Kontron SMARC-sAMX6i on SMARC Eval Carrier 2.0
		+ items:
		+ - const: kontron,imx6q-samx6i-ads2
		+ - const: kontron,imx6q-samx6i
		+ - const: fsl,imx6q
		+
	- description: i.MX6Q PHYTEC phyBOARD-Mira	- description: i.MX6Q PHYTEC phyBOARD-Mira
	items:	items:
	- enum:	- enum:
@@ -384,7 +389,8 @@ properties:
	- toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board	- toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board
	- toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board	- toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board
	- toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board	- toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board
	- - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board	+ - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board v1.0/v1.1
		+ - toradex,apalis_imx6q-eval-v1.2 # Apalis iMX6Q/D Module on Apalis Evaluation Board v1.2
	- const: toradex,apalis_imx6q	- const: toradex,apalis_imx6q
	- const: fsl,imx6q	- const: fsl,imx6q

@@ -469,6 +475,7 @@ properties:
	- prt,prtvt7 # Protonic VT7 board	- prt,prtvt7 # Protonic VT7 board
	- rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board	- rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board
	- riot,imx6s-riotboard # RIoTboard i.MX6S	- riot,imx6s-riotboard # RIoTboard i.MX6S
		+ - sielaff,imx6dl-board # Sielaff i.MX6 Solo Board
	- skov,imx6dl-skov-revc-lt2 # SKOV IMX6 CPU SoloCore lt2	- skov,imx6dl-skov-revc-lt2 # SKOV IMX6 CPU SoloCore lt2
	- skov,imx6dl-skov-revc-lt6 # SKOV IMX6 CPU SoloCore lt6	- skov,imx6dl-skov-revc-lt6 # SKOV IMX6 CPU SoloCore lt6
	- solidrun,cubox-i/dl # SolidRun Cubox-i Solo/DualLite	- solidrun,cubox-i/dl # SolidRun Cubox-i Solo/DualLite
@@ -542,6 +549,12 @@ properties:
	- const: gw,ventana	- const: gw,ventana
	- const: fsl,imx6dl	- const: fsl,imx6dl

		+ - description: i.MX6DL Kontron SMARC-sAMX6i on SMARC Eval Carrier 2.0
		+ items:
		+ - const: kontron,imx6dl-samx6i-ads2
		+ - const: kontron,imx6dl-samx6i
		+ - const: fsl,imx6dl
		+
	- description: i.MX6DL PHYTEC phyBOARD-Mira	- description: i.MX6DL PHYTEC phyBOARD-Mira
	items:	items:
	- enum:	- enum:
@@ -708,6 +721,7 @@ properties:
	- toradex,colibri-imx6ull # Colibri iMX6ULL Modules	- toradex,colibri-imx6ull # Colibri iMX6ULL Modules
	- toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module	- toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
	- toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Modules	- toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Modules
		+ - uni-t,uti260b # UNI-T UTi260B Thermal Camera
	- const: fsl,imx6ull	- const: fsl,imx6ull

	- description: i.MX6ULL Armadeus Systems OPOS6ULDev Board	- description: i.MX6ULL Armadeus Systems OPOS6ULDev Board
@@ -795,19 +809,27 @@ properties:
	- const: kontron,sl-imx6ull # Kontron SL i.MX6ULL SoM	- const: kontron,sl-imx6ull # Kontron SL i.MX6ULL SoM
	- const: fsl,imx6ull	- const: fsl,imx6ull

	- - description: TQ Systems TQMa6ULLx SoM on MBa6ULx board	+ - description: TQ-Systems TQMa6ULLx SoM on MBa6ULx board
		+ items:
		+ - enum:
		+ - tq,imx6ull-tqma6ull2-mba6ulx # TQMa6ULL socketable SoM with MCIMX6Y2 on MBa6ULx EVK
		+ - const: tq,imx6ull-tqma6ull2 # TQMa6ULL socketable SoM with MCIMX6Y2
		+ - const: fsl,imx6ull
		+
		+ - description: TQ-Systems TQMa6ULLxL SoM on MBa6ULx[L] board
	items:	items:
	- enum:	- enum:
	- - tq,imx6ull-tqma6ull2-mba6ulx	+ - tq,imx6ull-tqma6ull2l-mba6ulx # TQMa6ULLxL LGA SoM with socketable Adapter on MBa6ULx EVK
	- - const: tq,imx6ull-tqma6ull2 # MCIMX6Y2	+ - tq,imx6ull-tqma6ull2l-mba6ulxl # TQMa6ULLxL LGA SoM on MBa6ULxL gateway board
		+ - const: tq,imx6ull-tqma6ull2l # TQMa6ULLxL LGA SoM with MCIMX6Y2
	- const: fsl,imx6ull	- const: fsl,imx6ull

	- - description: TQ ~~Systems~~ ~~TQMa6ULLxL~~ SoM on ~~MBa6ULx[L]~~ ~~board~~	+ - description: Seeed Stuido i.MX6ULL SoM on dev boards
	items:	items:
	- enum:	- enum:
	- - tq,imx6ull-tqma6ull2l-mba6ulx # using LGA adapter	+ - seeed,imx6ull-seeed-npi-emmc
	- - tq,imx6ull-tqma6ull2l-mba6ulxl	+ - seeed,imx6ull-seeed-npi-nand
	- - const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant	+ - const: seeed,imx6ull-seeed-npi
	- const: fsl,imx6ull	- const: fsl,imx6ull

	- description: i.MX6ULZ based Boards	- description: i.MX6ULZ based Boards
@@ -917,8 +939,8 @@ properties:
	- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board	- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
	- fsl,imx8mm-evk # i.MX8MM EVK Board	- fsl,imx8mm-evk # i.MX8MM EVK Board
	- fsl,imx8mm-evkb # i.MX8MM EVKB Board	- fsl,imx8mm-evkb # i.MX8MM EVKB Board
		+ - gateworks,imx8mm-gw75xx-0x # i.MX8MM Gateworks Board
	- gateworks,imx8mm-gw7904	- gateworks,imx8mm-gw7904
	- - gateworks,imx8mm-gw7905-0x # i.MX8MM Gateworks Board
	- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit	- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
	- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit	- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
	- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit	- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
@@ -931,10 +953,16 @@ properties:
	- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules	- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
	- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT	- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
	- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules	- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
	- - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
	- prt,prt8mm # i.MX8MM Protonic PRT8MM Board	- prt,prt8mm # i.MX8MM Protonic PRT8MM Board
	- const: fsl,imx8mm	- const: fsl,imx8mm

		+ - description: Compulab i.MX8MM UCM SoM based boards
		+ items:
		+ - enum:
		+ - compulab,imx8mm-iot-gateway # i.MX8MM Compulab IoT-Gateway
		+ - const: compulab,imx8mm-ucm-som # i.MX8MM Compulab UCM SoM
		+ - const: fsl,imx8mm
		+
	- description: Emtop i.MX8MM based Boards	- description: Emtop i.MX8MM based Boards
	items:	items:
	- const: ees,imx8mm-emtop-baseboard # i.MX8MM Emtop SoM on i.MX8M Mini Baseboard V1	- const: ees,imx8mm-emtop-baseboard # i.MX8MM Emtop SoM on i.MX8M Mini Baseboard V1
@@ -1026,7 +1054,7 @@ properties:
	items:	items:
	- enum:	- enum:
	- dimonoff,gateway-evk # i.MX8MN Dimonoff Gateway EVK Board	- dimonoff,gateway-evk # i.MX8MN Dimonoff Gateway EVK Board
	- - rve,~~rve-~~gateway # i.MX8MN RVE Gateway Board	+ - rve,gateway # i.MX8MN RVE Gateway Board
	- variscite,var-som-mx8mn-symphony	- variscite,var-som-mx8mn-symphony
	- const: variscite,var-som-mx8mn	- const: variscite,var-som-mx8mn
	- const: fsl,imx8mn	- const: fsl,imx8mn
@@ -1047,12 +1075,13 @@ properties:
	- enum:	- enum:
	- beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit	- beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit
	- dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC	- dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
		+ - emcraft,imx8mp-navqp # i.MX8MP Emcraft Systems NavQ+ Kit
	- fsl,imx8mp-evk # i.MX8MP EVK Board	- fsl,imx8mp-evk # i.MX8MP EVK Board
	- gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board	- gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board
	- gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board	- gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board
	- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board	- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
	- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board	- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
	- - gateworks,imx8mp-~~gw7905~~-2x # i.MX8MP Gateworks Board	+ - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
	- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel	- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
	- skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel	- skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
	- skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel	- skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
@@ -1133,8 +1162,15 @@ properties:
	version as an industrial computing device.	version as an industrial computing device.
	items:	items:
	- enum:	- enum:
	- - tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL	+ - tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL
	- - ~~const:~~ tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM	+ - tq,imx8mp-tqma8mpql-mba8mp-ras314 # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MP-RAS314
		+ - const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM
		+ - const: fsl,imx8mp
		+
		+ - description: Variscite VAR-SOM-MX8M Plus based boards
		+ items:
		+ - const: variscite,var-som-mx8mp-symphony
		+ - const: variscite,var-som-mx8mp
	- const: fsl,imx8mp	- const: fsl,imx8mp

	- description: i.MX8MQ based Boards	- description: i.MX8MQ based Boards
@@ -1194,7 +1230,8 @@ properties:
	- description: i.MX8QM Boards with Toradex Apalis iMX8 Modules	- description: i.MX8QM Boards with Toradex Apalis iMX8 Modules
	items:	items:
	- enum:	- enum:
	- - toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation Board	+ - toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation V1.0/V1.1 Board
		+ - toradex,apalis-imx8-eval-v1.2 # Apalis iMX8 Module on Apalis Evaluation V1.2 Board
	- toradex,apalis-imx8-ixora-v1.1 # Apalis iMX8 Module on Ixora V1.1 Carrier Board	- toradex,apalis-imx8-ixora-v1.1 # Apalis iMX8 Module on Ixora V1.1 Carrier Board
	- const: toradex,apalis-imx8	- const: toradex,apalis-imx8
	- const: fsl,imx8qm	- const: fsl,imx8qm
@@ -1202,7 +1239,8 @@ properties:
	- description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules	- description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules
	items:	items:
	- enum:	- enum:
	- - toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. Board	+ - toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. V1.0/V1.1 Board
		+ - toradex,apalis-imx8-v1.1-eval-v1.2 # Apalis iMX8 V1.1 Module on Apalis Eval. V1.2 Board
	- toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board	- toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board
	- toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board	- toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board
	- const: toradex,apalis-imx8-v1.1	- const: toradex,apalis-imx8-v1.1
@@ -1213,7 +1251,6 @@ properties:
	- enum:	- enum:
	- einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board	- einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board
	- fsl,imx8qxp-mek # i.MX8QXP MEK Board	- fsl,imx8qxp-mek # i.MX8QXP MEK Board
	- - toradex,colibri-imx8x # Colibri iMX8X Modules
	- const: fsl,imx8qxp	- const: fsl,imx8qxp

	- description: i.MX8DXL based Boards	- description: i.MX8DXL based Boards
@@ -1222,7 +1259,7 @@ properties:
	- fsl,imx8dxl-evk # i.MX8DXL EVK Board	- fsl,imx8dxl-evk # i.MX8DXL EVK Board
	- const: fsl,imx8dxl	- const: fsl,imx8dxl

	- - description: i.MX8QXP Boards with Toradex Colibri iMX8X Modules	+ - description: i.MX8QXP/i.MX8DX Boards with Toradex Colibri iMX8X Modules
	items:	items:
	- enum:	- enum:
	- toradex,colibri-imx8x-aster # Colibri iMX8X Module on Aster Board	- toradex,colibri-imx8x-aster # Colibri iMX8X Module on Aster Board
@@ -1230,7 +1267,25 @@ properties:
	- toradex,colibri-imx8x-iris # Colibri iMX8X Module on Iris Board	- toradex,colibri-imx8x-iris # Colibri iMX8X Module on Iris Board
	- toradex,colibri-imx8x-iris-v2 # Colibri iMX8X Module on Iris Board V2	- toradex,colibri-imx8x-iris-v2 # Colibri iMX8X Module on Iris Board V2
	- const: toradex,colibri-imx8x	- const: toradex,colibri-imx8x
	- - ~~const: fsl,imx8qxp~~	+ - enum:
		+ - fsl,imx8qxp
		+ - fsl,imx8dx
		+
		+ - description:
		+ TQMa8Xx is a series of SOM featuring NXP i.MX8X system-on-chip
		+ variants. It is designed to be clicked on different carrier boards
		+ MBa8Xx is the starterkit
		+ oneOf:
		+ - items:
		+ - enum:
		+ - tq,imx8dxp-tqma8xdp-mba8xx # TQ-Systems GmbH TQMa8XDP SOM on MBa8Xx
		+ - const: tq,imx8dxp-tqma8xdp # TQ-Systems GmbH TQMa8XDP SOM (with i.MX8DXP)
		+ - const: fsl,imx8dxp
		+ - items:
		+ - enum:
		+ - tq,imx8qxp-tqma8xqp-mba8xx # TQ-Systems GmbH TQMa8XQP SOM on MBa8Xx
		+ - const: tq,imx8qxp-tqma8xqp # TQ-Systems GmbH TQMa8XQP SOM (with i.MX8QXP)
		+ - const: fsl,imx8qxp

	- description: i.MX8ULP based Boards	- description: i.MX8ULP based Boards
	items:	items:
@@ -1241,9 +1296,17 @@ properties:
	- description: i.MX93 based Boards	- description: i.MX93 based Boards
	items:	items:
	- enum:	- enum:
		+ - fsl,imx93-9x9-qsb # i.MX93 9x9 QSB Board
	- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board	- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
		+ - fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board
	- const: fsl,imx93	- const: fsl,imx93

		+ - description: i.MX95 based Boards
		+ items:
		+ - enum:
		+ - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board
		+ - const: fsl,imx95
		+
	- description: i.MXRT1050 based Boards	- description: i.MXRT1050 based Boards
	items:	items:
	- enum:	- enum:
@@ -1275,6 +1338,24 @@ properties:
	- const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM	- const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM
	- const: fsl,imx93	- const: fsl,imx93

		+ - description: PHYTEC phyCORE-i.MX93 SoM based boards
		+ items:
		+ - const: phytec,imx93-phyboard-segin # phyBOARD-Segin with i.MX93
		+ - const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM
		+ - const: fsl,imx93
		+
		+ - description: Variscite VAR-SOM-MX93 based boards
		+ items:
		+ - const: variscite,var-som-mx93-symphony
		+ - const: variscite,var-som-mx93
		+ - const: fsl,imx93
		+
		+ - description: Kontron OSM-S i.MX93 SoM based boards
		+ items:
		+ - const: kontron,imx93-bl-osm-s # Kontron BL i.MX93 OSM-S board
		+ - const: kontron,imx93-osm-s # Kontron OSM-S i.MX93 SoM
		+ - const: fsl,imx93
		+
	- description:	- description:
	Freescale Vybrid Platform Device Tree Bindings	Freescale Vybrid Platform Device Tree Bindings

@@ -1454,6 +1535,12 @@ properties:
	- fsl,ls2080a-rdb	- fsl,ls2080a-rdb
	- const: fsl,ls2080a	- const: fsl,ls2080a

		+ - description: LS2081A based Boards
		+ items:
		+ - enum:
		+ - fsl,ls2081a-rdb
		+ - const: fsl,ls2081a
		+
	- description: LS2088A based Boards	- description: LS2088A based Boards
	items:	items:
	- enum:	- enum:
@@ -1503,6 +1590,12 @@ properties:
	- nxp,s32g274a-rdb2	- nxp,s32g274a-rdb2
	- const: nxp,s32g2	- const: nxp,s32g2

		+ - description: S32G3 based Boards
		+ items:
		+ - enum:
		+ - nxp,s32g399a-rdb3
		+ - const: nxp,s32g3
		+
	- description: S32V234 based Boards	- description: S32V234 based Boards
	items:	items:
	- enum:	- enum:

    initialized early into boot process and provides services to Operating Systems
    on multiple processors including ones running Linux.
--  See http://processors.wiki.ti.com/index.php/TISCI for protocol definition.
++  See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
    The TI-SCI node describes the Texas Instrument's System Controller entity node.
    This parent node may optionally have additional children nodes which describe
    mboxes:
      minItems: 2
--  ti,system-reboot-controller:
--    description: Determines If system reboot can be triggered by SoC reboot
--    type: boolean
    ti,host-id:
      $ref: /schemas/types.yaml#/definitions/uint32
      description: |
    - |
      pmmc: system-controller@2921800 {
        compatible = "ti,k2g-sci";
--      ti,system-reboot-controller;
        mbox-names = "rx", "tx";
        mboxes = <&msgmgr 5 2>,
                 <&msgmgr 0 0>;

sys/contrib/device-tree/Bindings/arm/marvell/armada-38x.yaml
@@ -0,0 +1,70 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/arm/marvell/armada-38x.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Marvell Armada 38x Platforms
			+
			+maintainers:
			+ - Gregory CLEMENT <gregory.clement@bootlin.com>
			+
			+properties:
			+ $nodename:
			+ const: '/'
			+ compatible:
			+ oneOf:
			+
			+ - description:
			+ Netgear Armada 380 GS110EM Managed Switch.
			+ items:
			+ - const: netgear,gs110emx
			+ - const: marvell,armada380
			+
			+ - description:
			+ Marvell Armada 385 Development Boards.
			+ items:
			+ - enum:
			+ - marvell,a385-db-amc
			+ - marvell,a385-db-ap
			+ - const: marvell,armada385
			+ - const: marvell,armada380
			+
			+ - description:
			+ SolidRun Armada 385 based single-board computers.
			+ items:
			+ - enum:
			+ - solidrun,clearfog-gtr-l8
			+ - solidrun,clearfog-gtr-s4
			+ - const: marvell,armada385
			+ - const: marvell,armada380
			+
			+ - description:
			+ Kobol Armada 388 based Helios-4 NAS.
			+ items:
			+ - const: kobol,helios4
			+ - const: marvell,armada388
			+ - const: marvell,armada385
			+ - const: marvell,armada380
			+
			+ - description:
			+ Marvell Armada 388 Development Boards.
			+ items:
			+ - enum:
			+ - marvell,a388-gp
			+ - const: marvell,armada388
			+ - const: marvell,armada385
			+ - const: marvell,armada380
			+
			+ - description:
			+ SolidRun Armada 388 clearfog family single-board computers.
			+ items:
			+ - enum:
			+ - solidrun,clearfog-base-a1
			+ - solidrun,clearfog-pro-a1
			+ - const: solidrun,clearfog-a1
			+ - const: marvell,armada388
			+ - const: marvell,armada385
			+ - const: marvell,armada380
			+
			+additionalProperties: true

sys/contrib/device-tree/Bindings/arm/marvell/armada-7k-8k.yaml
@@ -82,4 +82,22 @@ properties:
	- const: marvell,armada-ap807-quad	- const: marvell,armada-ap807-quad
	- const: marvell,armada-ap807	- const: marvell,armada-ap807

		+ - description:
		+ SolidRun CN9130 SoM based single-board computers
		+ items:
		+ - enum:
		+ - solidrun,cn9130-clearfog-base
		+ - solidrun,cn9130-clearfog-pro
		+ - solidrun,cn9131-solidwan
		+ - const: solidrun,cn9130-sr-som
		+ - const: marvell,cn9130
		+
		+ - description:
		+ SolidRun CN9132 COM-Express Type 7 based single-board computers
		+ items:
		+ - enum:
		+ - solidrun,cn9132-clearfog
		+ - const: solidrun,cn9132-sr-cex7
		+ - const: marvell,cn9130
		+
	additionalProperties: true	additionalProperties: true

sys/contrib/device-tree/Bindings/arm/marvell/marvell,dove.txt
@@ -5,18 +5,3 @@ Boards with a Marvell Dove SoC shall have the following properties:

	Required root node property:	Required root node property:
	- compatible: must contain "marvell,dove";	- compatible: must contain "marvell,dove";
	-
	-* Global Configuration registers
	-
	-Global Configuration registers of Dove SoC are shared by a syscon node.
	-
	-Required properties:
	-- compatible: must contain "marvell,dove-global-config" and "syscon".
	-- reg: base address and size of the Global Configuration registers.
	-
	-Example:
	-
	-gconf: global-config@e802c {
	- compatible = "marvell,dove-global-config", "syscon";
	- reg = <0xe802c 0x14>;
	-};

sys/contrib/device-tree/Bindings/arm/mediatek.yaml
@@ -17,6 +17,7 @@ properties:
	const: '/'	const: '/'
	compatible:	compatible:
	oneOf:	oneOf:
		+ # Sort by SoC (last) compatible, then board compatible
	- items:	- items:
	- enum:	- enum:
	- mediatek,mt2701-evb	- mediatek,mt2701-evb
@@ -84,13 +85,25 @@ properties:
	- const: mediatek,mt7629	- const: mediatek,mt7629
	- items:	- items:
	- enum:	- enum:
		+ - cudy,wr3000-v1
		+ - openwrt,one
		+ - xiaomi,ax3000t
		+ - const: mediatek,mt7981b
		+ - items:
		+ - enum:
		+ - acelink,ew-7886cax
	- bananapi,bpi-r3	- bananapi,bpi-r3
		+ - bananapi,bpi-r3mini
	- mediatek,mt7986a-rfb	- mediatek,mt7986a-rfb
	- const: mediatek,mt7986a	- const: mediatek,mt7986a
	- items:	- items:
	- enum:	- enum:
	- mediatek,mt7986b-rfb	- mediatek,mt7986b-rfb
	- const: mediatek,mt7986b	- const: mediatek,mt7986b
		+ - items:
		+ - enum:
		+ - bananapi,bpi-r4
		+ - const: mediatek,mt7988a
	- items:	- items:
	- enum:	- enum:
	- mediatek,mt8127-moose	- mediatek,mt8127-moose
@@ -129,75 +142,10 @@ properties:
	- enum:	- enum:
	- mediatek,mt8173-evb	- mediatek,mt8173-evb
	- const: mediatek,mt8173	- const: mediatek,mt8173
	- - items:
	- - enum:
	- - mediatek,mt8183-evb
	- - const: mediatek,mt8183
	- - description: Google Hayato rev5
	- items:
	- - const: google,hayato-rev5-sku2
	- - const: google,hayato-sku2
	- - const: google,hayato
	- - const: mediatek,mt8192
	- - description: Google Hayato
	- items:
	- - const: google,hayato-rev1
	- - const: google,hayato
	- - const: mediatek,mt8192
	- - description: Google Spherion rev4 (Acer Chromebook 514)
	- items:
	- - const: google,spherion-rev4
	- - const: google,spherion
	- - const: mediatek,mt8192
	- - description: Google Spherion (Acer Chromebook 514)
	- items:
	- - const: google,spherion-rev3
	- - const: google,spherion-rev2
	- - const: google,spherion-rev1
	- - const: google,spherion-rev0
	- - const: google,spherion
	- - const: mediatek,mt8192
	- - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H)
	- items:
	- - enum:
	- - google,tomato-rev2
	- - google,tomato-rev1
	- - const: google,tomato
	- - const: mediatek,mt8195
	- - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H)
	- items:
	- - const: google,tomato-rev4
	- - const: google,tomato-rev3
	- - const: google,tomato
	- - const: mediatek,mt8195
	- - items:
	- - enum:
	- - mediatek,mt8186-evb
	- - const: mediatek,mt8186
	- - items:
	- - enum:
	- - mediatek,mt8188-evb
	- - const: mediatek,mt8188
	- - items:
	- - enum:
	- - mediatek,mt8192-evb
	- - const: mediatek,mt8192
	- - items:
	- - enum:
	- - mediatek,mt8195-demo
	- - mediatek,mt8195-evb
	- - const: mediatek,mt8195
	- description: Google Burnet (HP Chromebook x360 11MK G3 EE)	- description: Google Burnet (HP Chromebook x360 11MK G3 EE)
	items:	items:
	- const: google,burnet	- const: google,burnet
	- const: mediatek,mt8183	- const: mediatek,mt8183
	- - description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
	- items:
	- - enum:
	- - google,krane-sku0
	- - google,krane-sku176
	- - const: google,krane
	- - const: mediatek,mt8183
	- description: Google Cozmo (Acer Chromebook 314)	- description: Google Cozmo (Acer Chromebook 314)
	items:	items:
	- const: google,cozmo	- const: google,cozmo
@@ -255,6 +203,13 @@ properties:
	- google,kodama-sku32	- google,kodama-sku32
	- const: google,kodama	- const: google,kodama
	- const: mediatek,mt8183	- const: mediatek,mt8183
		+ - description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
		+ items:
		+ - enum:
		+ - google,krane-sku0
		+ - google,krane-sku176
		+ - const: google,krane
		+ - const: mediatek,mt8183
	- description: Google Makomo (Lenovo 100e Chromebook 2nd Gen MTK 2)	- description: Google Makomo (Lenovo 100e Chromebook 2nd Gen MTK 2)
	items:	items:
	- enum:	- enum:
@@ -276,17 +231,154 @@ properties:
	- google,willow-sku1	- google,willow-sku1
	- const: google,willow	- const: google,willow
	- const: mediatek,mt8183	- const: mediatek,mt8183
		+ - items:
		+ - enum:
		+ - mediatek,mt8183-evb
		+ - const: mediatek,mt8183
	- items:	- items:
	- enum:	- enum:
	- mediatek,mt8183-pumpkin	- mediatek,mt8183-pumpkin
	- const: mediatek,mt8183	- const: mediatek,mt8183
		+ - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
		+ items:
		+ - const: google,steelix-sku393219
		+ - const: google,steelix-sku393216
		+ - const: google,steelix
		+ - const: mediatek,mt8186
		+ - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
		+ items:
		+ - const: google,steelix-sku393220
		+ - const: google,steelix-sku393217
		+ - const: google,steelix
		+ - const: mediatek,mt8186
		+ - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
		+ items:
		+ - const: google,steelix-sku393221
		+ - const: google,steelix-sku393218
		+ - const: google,steelix
		+ - const: mediatek,mt8186
		+ - description: Google Rusty (Lenovo 100e Chromebook Gen 4)
		+ items:
		+ - const: google,steelix-sku196609
		+ - const: google,steelix-sku196608
		+ - const: google,steelix
		+ - const: mediatek,mt8186
		+ - description: Google Steelix (Lenovo 300e Yoga Chromebook Gen 4)
		+ items:
		+ - enum:
		+ - google,steelix-sku131072
		+ - google,steelix-sku131073
		+ - const: google,steelix
		+ - const: mediatek,mt8186
		+ - description: Google Tentacruel (ASUS Chromebook CM14 Flip CM1402F)
		+ items:
		+ - const: google,tentacruel-sku262147
		+ - const: google,tentacruel-sku262146
		+ - const: google,tentacruel-sku262145
		+ - const: google,tentacruel-sku262144
		+ - const: google,tentacruel
		+ - const: mediatek,mt8186
		+ - description: Google Tentacruel (ASUS Chromebook CM14 Flip CM1402F)
		+ items:
		+ - const: google,tentacruel-sku262151
		+ - const: google,tentacruel-sku262150
		+ - const: google,tentacruel-sku262149
		+ - const: google,tentacruel-sku262148
		+ - const: google,tentacruel
		+ - const: mediatek,mt8186
		+ - description: Google Tentacool (ASUS Chromebook CM14 CM1402C)
		+ items:
		+ - const: google,tentacruel-sku327681
		+ - const: google,tentacruel
		+ - const: mediatek,mt8186
		+ - description: Google Tentacool (ASUS Chromebook CM14 CM1402C)
		+ items:
		+ - const: google,tentacruel-sku327683
		+ - const: google,tentacruel
		+ - const: mediatek,mt8186
		+ - description: Google Voltorb (Acer Chromebook 311 C723/C732T)
		+ items:
		+ - enum:
		+ - google,voltorb-sku589824
		+ - google,voltorb-sku589825
		+ - const: google,voltorb
		+ - const: mediatek,mt8186
		+ - items:
		+ - enum:
		+ - mediatek,mt8186-evb
		+ - const: mediatek,mt8186
		+ - items:
		+ - enum:
		+ - mediatek,mt8188-evb
		+ - const: mediatek,mt8188
		+ - description: Google Hayato
		+ items:
		+ - const: google,hayato-rev1
		+ - const: google,hayato
		+ - const: mediatek,mt8192
		+ - description: Google Hayato rev5
		+ items:
		+ - const: google,hayato-rev5-sku2
		+ - const: google,hayato-sku2
		+ - const: google,hayato
		+ - const: mediatek,mt8192
		+ - description: Google Spherion (Acer Chromebook 514)
		+ items:
		+ - const: google,spherion-rev3
		+ - const: google,spherion-rev2
		+ - const: google,spherion-rev1
		+ - const: google,spherion-rev0
		+ - const: google,spherion
		+ - const: mediatek,mt8192
		+ - description: Google Spherion rev4 (Acer Chromebook 514)
		+ items:
		+ - const: google,spherion-rev4
		+ - const: google,spherion
		+ - const: mediatek,mt8192
		+ - items:
		+ - enum:
		+ - mediatek,mt8192-evb
		+ - const: mediatek,mt8192
		+ - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H)
		+ items:
		+ - enum:
		+ - google,tomato-rev2
		+ - google,tomato-rev1
		+ - const: google,tomato
		+ - const: mediatek,mt8195
		+ - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H)
		+ items:
		+ - const: google,tomato-rev4
		+ - const: google,tomato-rev3
		+ - const: google,tomato
		+ - const: mediatek,mt8195
		+ - description: HP Dojo sku1, 3, 5, 7 (HP Chromebook x360 13b-ca0002sa)
		+ items:
		+ - const: google,dojo-sku7
		+ - const: google,dojo-sku5
		+ - const: google,dojo-sku3
		+ - const: google,dojo-sku1
		+ - const: google,dojo
		+ - const: mediatek,mt8195
		+ - items:
		+ - enum:
		+ - mediatek,mt8195-demo
		+ - mediatek,mt8195-evb
		+ - const: mediatek,mt8195
	- items:	- items:
	- enum:	- enum:
	- mediatek,mt8365-evk	- mediatek,mt8365-evk
	- const: mediatek,mt8365	- const: mediatek,mt8365
	- items:	- items:
	- enum:	- enum:
		+ - mediatek,mt8390-evk
		+ - const: mediatek,mt8390
		+ - const: mediatek,mt8188
		+ - items:
		+ - enum:
		+ - kontron,3-5-sbc-i1200
	- mediatek,mt8395-evk	- mediatek,mt8395-evk
		+ - radxa,nio-12l
	- const: mediatek,mt8395	- const: mediatek,mt8395
	- const: mediatek,mt8195	- const: mediatek,mt8195
	- items:	- items:

            - arm,cortex-a710-pmu
            - arm,cortex-a715-pmu
            - arm,cortex-a720-pmu
++          - arm,cortex-a725-pmu
            - arm,cortex-x1-pmu
            - arm,cortex-x2-pmu
            - arm,cortex-x3-pmu
            - arm,cortex-x4-pmu
++          - arm,cortex-x925-pmu
            - arm,neoverse-e1-pmu
            - arm,neoverse-n1-pmu
            - arm,neoverse-n2-pmu
++          - arm,neoverse-n3-pmu
            - arm,neoverse-v1-pmu
++          - arm,neoverse-v2-pmu
++          - arm,neoverse-v3-pmu
++          - arm,neoverse-v3ae-pmu
            - brcm,vulcan-pmu
            - cavium,thunder-pmu
            - nvidia,denver-pmu

sys/contrib/device-tree/Bindings/arm/qcom,coresight-tpda.yaml
@@ -66,13 +66,11 @@ properties:
	- const: apb_pclk	- const: apb_pclk

	in-ports:	in-ports:
	- type: object
	description: \|	description: \|
	Input connections from TPDM to TPDA	Input connections from TPDM to TPDA
	$ref: /schemas/graph.yaml#/properties/ports	$ref: /schemas/graph.yaml#/properties/ports

	out-ports:	out-ports:
	- type: object
	description: \|	description: \|
	Output connections from the TPDA to legacy CoreSight trace bus.	Output connections from the TPDA to legacy CoreSight trace bus.
	$ref: /schemas/graph.yaml#/properties/ports	$ref: /schemas/graph.yaml#/properties/ports
@@ -97,33 +95,31 @@ examples:
	# minimum tpda definition.	# minimum tpda definition.
	- \|	- \|
	tpda@6004000 {	tpda@6004000 {
	- compatible = "qcom,coresight-tpda", "arm,primecell";	+ compatible = "qcom,coresight-tpda", "arm,primecell";
	- reg = <0x6004000 0x1000>;	+ reg = <0x6004000 0x1000>;

	- clocks = <&aoss_qmp>;	+ clocks = <&aoss_qmp>;
	- clock-names = "apb_pclk";	+ clock-names = "apb_pclk";

	- in-ports {	+ in-ports {
	- #address-cells = <1>;	+ #address-cells = <1>;
	- #size-cells = <0>;	+ #size-cells = <0>;

	port@0 {	port@0 {
	reg = <0>;	reg = <0>;
	tpda_qdss_0_in_tpdm_dcc: endpoint {	tpda_qdss_0_in_tpdm_dcc: endpoint {
	- remote-endpoint =	+ remote-endpoint = <&tpdm_dcc_out_tpda_qdss_0>;
	- <&tpdm_dcc_out_tpda_qdss_0>;	+ };
	- };
	};	};
	};	};

	- out-ports {	+ out-ports {
	- port {	+ port {
	- tpda_qdss_out_funnel_in0: endpoint {	+ tpda_qdss_out_funnel_in0: endpoint {
	- remote-endpoint =	+ remote-endpoint = <&funnel_in0_in_tpda_qdss>;
	- <&funnel_in0_in_tpda_qdss>;
	- };
	};	};
	- };	+ };
		+ };
	};	};

	...	...

sys/contrib/device-tree/Bindings/arm/qcom,coresight-tpdm.yaml
@@ -44,14 +44,21 @@ properties:
	minItems: 1	minItems: 1
	maxItems: 2	maxItems: 2

	- qcom,dsb-element-~~size:~~	+ qcom,dsb-element-bits:
	description:	description:
	Specifies the DSB(Discrete Single Bit) element size supported by	Specifies the DSB(Discrete Single Bit) element size supported by
	the monitor. The associated aggregator will read this size before it	the monitor. The associated aggregator will read this size before it
	is enabled. DSB element size currently only supports 32-bit and 64-bit.	is enabled. DSB element size currently only supports 32-bit and 64-bit.
	- $ref: /schemas/types.yaml#/definitions/uint8
	enum: [32, 64]	enum: [32, 64]

		+ qcom,cmb-element-bits:
		+ description:
		+ Specifies the CMB(Continuous Multi-Bit) element size supported by
		+ the monitor. The associated aggregator will read this size before it
		+ is enabled. CMB element size currently only supports 8-bit, 32-bit
		+ and 64-bit.
		+ enum: [8, 32, 64]
		+
	qcom,dsb-msrs-num:	qcom,dsb-msrs-num:
	description:	description:
	Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)	Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)
@@ -61,6 +68,15 @@ properties:
	minimum: 0	minimum: 0
	maximum: 32	maximum: 32

		+ qcom,cmb-msrs-num:
		+ description:
		+ Specifies the number of CMB MSR(mux select register) registers supported
		+ by the monitor. If this property is not configured or set to 0, it means
		+ this TPDM doesn't support CMB MSR.
		+ $ref: /schemas/types.yaml#/definitions/uint32
		+ minimum: 0
		+ maximum: 32
		+
	clocks:	clocks:
	maxItems: 1	maxItems: 1

@@ -94,7 +110,7 @@ examples:
	compatible = "qcom,coresight-tpdm", "arm,primecell";	compatible = "qcom,coresight-tpdm", "arm,primecell";
	reg = <0x0684c000 0x1000>;	reg = <0x0684c000 0x1000>;

	- qcom,dsb-element-~~size~~ = ~~/bits/ 8~~ <32>;	+ qcom,dsb-element-bits = <32>;
	qcom,dsb-msrs-num = <16>;	qcom,dsb-msrs-num = <16>;

	clocks = <&aoss_qmp>;	clocks = <&aoss_qmp>;
@@ -110,4 +126,22 @@ examples:
	};	};
	};	};

		+ tpdm@6c29000 {
		+ compatible = "qcom,coresight-tpdm", "arm,primecell";
		+ reg = <0x06c29000 0x1000>;
		+
		+ qcom,cmb-element-bits = <64>;
		+ qcom,cmb-msrs-num = <32>;
		+
		+ clocks = <&aoss_qmp>;
		+ clock-names = "apb_pclk";
		+
		+ out-ports {
		+ port {
		+ tpdm_ipcc_out_funnel_center: endpoint {
		+ remote-endpoint = <&funnel_center_in_tpdm_ipcc>;
		+ };
		+ };
		+ };
		+ };
	...	...

sys/contrib/device-tree/Bindings/arm/qcom.yaml
@@ -10,17 +10,10 @@ maintainers:
	- Bjorn Andersson <bjorn.andersson@linaro.org>	- Bjorn Andersson <bjorn.andersson@linaro.org>

	description: \|	description: \|
	- Some qcom based bootloaders identify the dtb blob based on a set of	+ For devices using the Qualcomm SoC the "compatible" properties consists of
	- device properties like SoC and platform and revisions of those components.	+ one or several "manufacturer,model" strings, describing the device itself,
	- To support this scheme, we encode this information into the board compatible	+ followed by one or several "qcom,<SoC>" strings, describing the SoC used in
	- string.	+ the device.
	-
	- Each board must specify a top-level board compatible string with the following
	- format:
	-
	- compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
	-
	- The 'SoC' and 'board' elements are required. All other elements are optional.

	The 'SoC' element must be one of the following strings:	The 'SoC' element must be one of the following strings:

@@ -49,6 +42,7 @@ description: \|
	msm8996	msm8996
	msm8998	msm8998
	qcs404	qcs404
		+ qcs8550
	qcm2290	qcm2290
	qcm6490	qcm6490
	qdu1000	qdu1000
@@ -90,43 +84,9 @@ description: \|
	sm8650	sm8650
	x1e80100	x1e80100

	- The 'board' element must be one of the following strings:
	-
	- adp
	- cdp
	- dragonboard
	- idp
	- liquid
	- mtp
	- qcp
	- qrd
	- rb2
	- ride
	- sbc
	- x100
	-
	- The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
	- where the minor number may be omitted when it's zero, i.e. v1.0 is the same
	- as v1. If all versions of the 'board_version' elements match, then a
	- wildcard '' should be used, e.g. 'v'.
	-
	- The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9.
	-
	- Examples:
	-
	- "qcom,msm8916-v1-cdp-pm8916-v2.1"
	-
	- A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version
	- 2.1.
	-
	- "qcom,apq8074-v2.0-2-dragonboard/1-v0.1"
	-
	- A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in
	- foundry 2.
	-
	There are many devices in the list below that run the standard ChromeOS	There are many devices in the list below that run the standard ChromeOS
	bootloader setup and use the open source depthcharge bootloader to boot the	bootloader setup and use the open source depthcharge bootloader to boot the
	- OS. These devices ~~do not~~ use the ~~scheme~~ ~~described~~ ~~above. For details, see:~~	+ OS. These devices use the bootflow explained at
	https://docs.kernel.org/arch/arm/google/chromebook-boot-flow.html	https://docs.kernel.org/arch/arm/google/chromebook-boot-flow.html

	properties:	properties:
@@ -137,6 +97,7 @@ properties:
	- items:	- items:
	- enum:	- enum:
	- qcom,apq8016-sbc	- qcom,apq8016-sbc
		+ - schneider,apq8016-hmibsc
	- const: qcom,apq8016	- const: qcom,apq8016

	- items:	- items:
@@ -145,6 +106,7 @@ properties:
	- huawei,sturgeon	- huawei,sturgeon
	- lg,lenok	- lg,lenok
	- samsung,matisse-wifi	- samsung,matisse-wifi
		+ - samsung,milletwifi
	- const: qcom,apq8026	- const: qcom,apq8026

	- items:	- items:
@@ -178,6 +140,8 @@ properties:
	- microsoft,dempsey	- microsoft,dempsey
	- microsoft,makepeace	- microsoft,makepeace
	- microsoft,moneypenny	- microsoft,moneypenny
		+ - motorola,falcon
		+ - samsung,ms013g
	- samsung,s3ve3g	- samsung,s3ve3g
	- const: qcom,msm8226	- const: qcom,msm8226

@@ -187,9 +151,15 @@ properties:
	- microsoft,superman-lte	- microsoft,superman-lte
	- microsoft,tesla	- microsoft,tesla
	- motorola,peregrine	- motorola,peregrine
		+ - samsung,matisselte
	- const: qcom,msm8926	- const: qcom,msm8926
	- const: qcom,msm8226	- const: qcom,msm8226

		+ - items:
		+ - enum:
		+ - wingtech,wt82918hd
		+ - const: qcom,msm8929
		+
	- items:	- items:
	- enum:	- enum:
	- huawei,kiwi	- huawei,kiwi
@@ -197,6 +167,8 @@ properties:
	- samsung,a7	- samsung,a7
	- sony,kanuti-tulip	- sony,kanuti-tulip
	- square,apq8039-t2	- square,apq8039-t2
		+ - wingtech,wt82918
		+ - wingtech,wt82918hdhw39
	- const: qcom,msm8939	- const: qcom,msm8939

	- items:	- items:
@@ -214,6 +186,7 @@ properties:
	- items:	- items:
	- enum:	- enum:
	- lge,hammerhead	- lge,hammerhead
		+ - samsung,hlte
	- sony,xperia-amami	- sony,xperia-amami
	- sony,xperia-honami	- sony,xperia-honami
	- const: qcom,msm8974	- const: qcom,msm8974
@@ -221,16 +194,21 @@ properties:
	- items:	- items:
	- enum:	- enum:
	- fairphone,fp2	- fairphone,fp2
		+ - htc,m8
	- oneplus,bacon	- oneplus,bacon
	- samsung,klte	- samsung,klte
		+ - sony,xperia-aries
	- sony,xperia-castor	- sony,xperia-castor
		+ - sony,xperia-leo
	- const: qcom,msm8974pro	- const: qcom,msm8974pro
	- const: qcom,msm8974	- const: qcom,msm8974

	- items:	- items:
	- - ~~const: qcom,msm8916-mtp~~	+ - enum:
	- - const: qcom,msm8916-mtp/1	+ - samsung,kltechn
	- - const: ~~qcom~~,~~msm8916~~	+ - const: samsung,klte
		+ - const: qcom,msm8974pro
		+ - const: qcom,msm8974

	- items:	- items:
	- enum:	- enum:
@@ -239,28 +217,37 @@ properties:
	- asus,z00l	- asus,z00l
	- gplus,fl8005a	- gplus,fl8005a
	- huawei,g7	- huawei,g7
		+ - lg,c50
		+ - lg,m216
	- longcheer,l8910	- longcheer,l8910
		+ - longcheer,l8150
		+ - motorola,harpia
		+ - motorola,osprey
		+ - motorola,surnia
		+ - qcom,msm8916-mtp
	- samsung,a3u-eur	- samsung,a3u-eur
	- samsung,a5u-eur	- samsung,a5u-eur
	- samsung,e5	- samsung,e5
	- samsung,e7	- samsung,e7
		+ - samsung,fortuna3g
		+ - samsung,gprimeltecan
	- samsung,grandmax	- samsung,grandmax
		+ - samsung,grandprimelte
	- samsung,gt510	- samsung,gt510
	- samsung,gt58	- samsung,gt58
		+ - samsung,j3ltetw
	- samsung,j5	- samsung,j5
	- samsung,j5x	- samsung,j5x
		+ - samsung,rossa
	- samsung,serranove	- samsung,serranove
	- thwc,uf896	- thwc,uf896
	- thwc,ufi001c	- thwc,ufi001c
		+ - wingtech,wt86518
		+ - wingtech,wt86528
	- wingtech,wt88047	- wingtech,wt88047
	- yiming,uz801-v3	- yiming,uz801-v3
	- const: qcom,msm8916	- const: qcom,msm8916

	- - items:
	- - const: longcheer,l8150
	- - const: qcom,msm8916-v1-qrd/9-v1
	- - const: qcom,msm8916
	-
	- items:	- items:
	- enum:	- enum:
	- motorola,potter	- motorola,potter
@@ -273,6 +260,7 @@ properties:
	- items:	- items:
	- enum:	- enum:
	- lg,bullhead	- lg,bullhead
		+ - lg,h815
	- microsoft,talkman	- microsoft,talkman
	- xiaomi,libra	- xiaomi,libra
	- const: qcom,msm8992	- const: qcom,msm8992
@@ -351,6 +339,7 @@ properties:
	- items:	- items:
	- enum:	- enum:
	- qcom,ipq5018-rdp432-c2	- qcom,ipq5018-rdp432-c2
		+ - tplink,archer-ax55-v1
	- const: qcom,ipq5018	- const: qcom,ipq5018

	- items:	- items:
@@ -401,6 +390,7 @@ properties:
	- fairphone,fp5	- fairphone,fp5
	- qcom,qcm6490-idp	- qcom,qcm6490-idp
	- qcom,qcs6490-rb3gen2	- qcom,qcs6490-rb3gen2
		+ - shift,otter
	- const: qcom,qcm6490	- const: qcom,qcm6490

	- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform	- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
@@ -837,6 +827,7 @@ properties:

	- items:	- items:
	- enum:	- enum:
		+ - lenovo,tbx605f
	- motorola,ali	- motorola,ali
	- const: qcom,sdm450	- const: qcom,sdm450

@@ -918,6 +909,7 @@ properties:
	- items:	- items:
	- enum:	- enum:
	- qcom,sa8775p-ride	- qcom,sa8775p-ride
		+ - qcom,sa8775p-ride-r3
	- const: qcom,sa8775p	- const: qcom,sa8775p

	- items:	- items:
@@ -988,6 +980,7 @@ properties:

	- items:	- items:
	- enum:	- enum:
		+ - xiaomi,curtana
	- xiaomi,joyeuse	- xiaomi,joyeuse
	- const: qcom,sm7125	- const: qcom,sm7125

@@ -1035,18 +1028,39 @@ properties:

	- items:	- items:
	- enum:	- enum:
		+ - qcom,sm8550-hdk
	- qcom,sm8550-mtp	- qcom,sm8550-mtp
	- qcom,sm8550-qrd	- qcom,sm8550-qrd
		+ - samsung,q5q
		+ - sony,pdx234
	- const: qcom,sm8550	- const: qcom,sm8550

	- items:	- items:
	- enum:	- enum:
		+ - qcom,qcs8550-aim300-aiot
		+ - const: qcom,qcs8550-aim300
		+ - const: qcom,qcs8550
		+ - const: qcom,sm8550
		+
		+ - items:
		+ - enum:
		+ - qcom,sm8650-hdk
	- qcom,sm8650-mtp	- qcom,sm8650-mtp
	- qcom,sm8650-qrd	- qcom,sm8650-qrd
	- const: qcom,sm8650	- const: qcom,sm8650

	- items:	- items:
	- enum:	- enum:
		+ - lenovo,thinkpad-t14s
		+ - const: qcom,x1e78100
		+ - const: qcom,x1e80100
		+
		+ - items:
		+ - enum:
		+ - asus,vivobook-s15
		+ - lenovo,yoga-slim7x
		+ - microsoft,romulus13
		+ - microsoft,romulus15
	- qcom,x1e80100-crd	- qcom,x1e80100-crd
	- qcom,x1e80100-qcp	- qcom,x1e80100-qcp
	- const: qcom,x1e80100	- const: qcom,x1e80100

sys/contrib/device-tree/Bindings/arm/rockchip.yaml
@@ -37,30 +37,22 @@ properties:
	- anbernic,rg351v	- anbernic,rg351v
	- const: rockchip,rk3326	- const: rockchip,rk3326

	- - description: Anbernic ~~RG353P~~	+ - description: Anbernic RK3566 Handheld Gaming Console
	items:	items:
	- - const: anbernic,rg353p	+ - enum:
	- - const: rockchip,rk3566	+ - anbernic,rg353p
	-	+ - anbernic,rg353ps
	- - description: Anbernic RG353PS	+ - anbernic,rg353v
	- items:	+ - anbernic,rg353vs
	- - ~~const:~~ anbernic,~~rg353ps~~	+ - anbernic,rg503
	- - const: rockchip,rk3566	+ - anbernic,rg-arc-d
	-	+ - anbernic,rg-arc-s
	- - description: Anbernic RG353V
	- items:
	- - const: anbernic,rg353v
	- - const: rockchip,rk3566
	-
	- - description: Anbernic RG353VS
	- items:
	- - const: anbernic,rg353vs
	- const: rockchip,rk3566	- const: rockchip,rk3566

	- - description: ~~Anbernic~~ ~~RG503~~	+ - description: ArmSoM Sige7 board
	items:	items:
	- - const: ~~anbernic~~,~~rg503~~	+ - const: armsom,sige7
	- - const: rockchip,~~rk3566~~	+ - const: rockchip,rk3588

	- description: Asus Tinker board	- description: Asus Tinker board
	items:	items:
@@ -104,6 +96,13 @@ properties:
	- const: coolpi,pi-cm5	- const: coolpi,pi-cm5
	- const: rockchip,rk3588	- const: rockchip,rk3588

		+ - description: Cool Pi CM5 GenBook
		+ items:
		+ - enum:
		+ - coolpi,pi-cm5-genbook
		+ - const: coolpi,pi-cm5
		+ - const: rockchip,rk3588
		+
	- description: Cool Pi 4 Model B	- description: Cool Pi 4 Model B
	items:	items:
	- const: coolpi,pi-4b	- const: coolpi,pi-4b
@@ -156,6 +155,12 @@ properties:
	- const: engicam,px30-core	- const: engicam,px30-core
	- const: rockchip,px30	- const: rockchip,px30

		+ - description: Firefly Core-PX30-JD4 on MB-JD4-PX30 baseboard
		+ items:
		+ - const: firefly,px30-jd4-core-mb
		+ - const: firefly,px30-jd4-core
		+ - const: rockchip,px30
		+
	- description: Firefly Firefly-RK3288	- description: Firefly Firefly-RK3288
	items:	items:
	- enum:	- enum:
@@ -211,12 +216,20 @@ properties:
	- const: firefly,rk3568-roc-pc	- const: firefly,rk3568-roc-pc
	- const: rockchip,rk3568	- const: rockchip,rk3568

		+ - description: Forlinx FET3588-C SoM
		+ items:
		+ - enum:
		+ - forlinx,ok3588-c
		+ - const: forlinx,fet3588-c
		+ - const: rockchip,rk3588
		+
	- description: FriendlyElec NanoPi R2 series boards	- description: FriendlyElec NanoPi R2 series boards
	items:	items:
	- enum:	- enum:
	- friendlyarm,nanopi-r2c	- friendlyarm,nanopi-r2c
	- friendlyarm,nanopi-r2c-plus	- friendlyarm,nanopi-r2c-plus
	- friendlyarm,nanopi-r2s	- friendlyarm,nanopi-r2s
		+ - friendlyarm,nanopi-r2s-plus
	- const: rockchip,rk3328	- const: rockchip,rk3328

	- description: FriendlyElec NanoPi4 series boards	- description: FriendlyElec NanoPi4 series boards
@@ -237,11 +250,37 @@ properties:
	- friendlyarm,nanopi-r5s	- friendlyarm,nanopi-r5s
	- const: rockchip,rk3568	- const: rockchip,rk3568

	- - description: FriendlyElec ~~NanoPC~~ T6	+ - description: FriendlyElec NanoPi R6 series boards
		+ items:
		+ - enum:
		+ - friendlyarm,nanopi-r6c
		+ - friendlyarm,nanopi-r6s
		+ - const: rockchip,rk3588s
		+
		+ - description: FriendlyElec NanoPC T6 series boards
	items:	items:
	- - const: friendlyarm,nanopc-t6	+ - enum:
		+ - friendlyarm,nanopc-t6
		+ - friendlyarm,nanopc-t6-lts
	- const: rockchip,rk3588	- const: rockchip,rk3588

		+ - description: FriendlyElec CM3588-based boards
		+ items:
		+ - enum:
		+ - friendlyarm,cm3588-nas
		+ - const: friendlyarm,cm3588
		+ - const: rockchip,rk3588
		+
		+ - description: GameForce Ace
		+ items:
		+ - const: gameforce,ace
		+ - const: rockchip,rk3588s
		+
		+ - description: GameForce Chi
		+ items:
		+ - const: gameforce,chi
		+ - const: rockchip,rk3326
		+
	- description: GeekBuying GeekBox	- description: GeekBuying GeekBox
	items:	items:
	- const: geekbuying,geekbox	- const: geekbuying,geekbox
@@ -563,9 +602,19 @@ properties:

	- description: Hardkernel Odroid M1	- description: Hardkernel Odroid M1
	items:	items:
	- - const: ~~rockchip~~,~~rk3568-~~odroid-m1	+ - const: hardkernel,odroid-m1
	- const: rockchip,rk3568	- const: rockchip,rk3568

		+ - description: Hardkernel Odroid M1S
		+ items:
		+ - const: hardkernel,odroid-m1s
		+ - const: rockchip,rk3566
		+
		+ - description: Hardkernel Odroid M2
		+ items:
		+ - const: hardkernel,odroid-m2
		+ - const: rockchip,rk3588s
		+
	- description: Hugsun X99 TV Box	- description: Hugsun X99 TV Box
	items:	items:
	- const: hugsun,x99	- const: hugsun,x99
@@ -604,6 +653,11 @@ properties:
	- const: leez,p710	- const: leez,p710
	- const: rockchip,rk3399	- const: rockchip,rk3399

		+ - description: LCKFB Taishan Pi RK3566
		+ items:
		+ - const: lckfb,tspi-rk3566
		+ - const: rockchip,rk3566
		+
	- description: Lunzn FastRhino R66S / R68S	- description: Lunzn FastRhino R66S / R68S
	items:	items:
	- enum:	- enum:
@@ -616,6 +670,11 @@ properties:
	- const: mqmaker,miqi	- const: mqmaker,miqi
	- const: rockchip,rk3288	- const: rockchip,rk3288

		+ - description: Neardi LBA3368
		+ items:
		+ - const: neardi,lba3368
		+ - const: rockchip,rk3368
		+
	- description: Netxeon R89 board	- description: Netxeon R89 board
	items:	items:
	- const: netxeon,r89	- const: netxeon,r89
@@ -626,9 +685,9 @@ properties:
	- const: openailab,eaidk-610	- const: openailab,eaidk-610
	- const: rockchip,rk3399	- const: rockchip,rk3399

	- - description: Orange Pi RK3399 board	+ - description: Xunlong Orange Pi RK3399 board
	items:	items:
	- - const: ~~rockchip~~,rk3399-orangepi	+ - const: xunlong,rk3399-orangepi
	- const: rockchip,rk3399	- const: rockchip,rk3399

	- description: Phytec phyCORE-RK3288 Rapid Development Kit	- description: Phytec phyCORE-RK3288 Rapid Development Kit
@@ -637,7 +696,7 @@ properties:
	- const: phytec,rk3288-phycore-som	- const: phytec,rk3288-phycore-som
	- const: rockchip,rk3288	- const: rockchip,rk3288

	- - description: Pine64 ~~PinebookPro~~	+ - description: Pine64 Pinebook Pro
	items:	items:
	- const: pine64,pinebook-pro	- const: pine64,pinebook-pro
	- const: rockchip,rk3399	- const: rockchip,rk3399
@@ -650,11 +709,19 @@ properties:
	- const: pine64,pinenote	- const: pine64,pinenote
	- const: rockchip,rk3566	- const: rockchip,rk3566

	- - description: Pine64 ~~PinePhonePro~~	+ - description: Pine64 PinePhone Pro
	items:	items:
	- const: pine64,pinephone-pro	- const: pine64,pinephone-pro
	- const: rockchip,rk3399	- const: rockchip,rk3399

		+ - description: Pine64 PineTab2
		+ items:
		+ - enum:
		+ - pine64,pinetab2-v0.1
		+ - pine64,pinetab2-v2.0
		+ - const: pine64,pinetab2
		+ - const: rockchip,rk3566
		+
	- description: Pine64 Rock64	- description: Pine64 Rock64
	items:	items:
	- const: pine64,rock64	- const: pine64,rock64
@@ -680,7 +747,7 @@ properties:
	- const: pine64,quartzpro64	- const: pine64,quartzpro64
	- const: rockchip,rk3588	- const: rockchip,rk3588

	- - description: Pine64 ~~SoQuartz SoM~~	+ - description: Pine64 SOQuartz
	items:	items:
	- enum:	- enum:
	- pine64,soquartz-blade	- pine64,soquartz-blade
@@ -692,12 +759,23 @@ properties:
	- description: Powkiddy RK3566 Handheld Gaming Console	- description: Powkiddy RK3566 Handheld Gaming Console
	items:	items:
	- enum:	- enum:
		+ - powkiddy,rgb10max3
	- powkiddy,rgb30	- powkiddy,rgb30
	- powkiddy,rk2023	- powkiddy,rk2023
	- powkiddy,x55	- powkiddy,x55
	- const: rockchip,rk3566	- const: rockchip,rk3566

	- - description: ~~Radxa~~ ~~Compute~~ ~~Module 3(CM3)~~	+ - description: Protonic MECSBC board
		+ items:
		+ - const: prt,mecsbc
		+ - const: rockchip,rk3568
		+
		+ - description: QNAP TS-433-4G 4-Bay NAS
		+ items:
		+ - const: qnap,ts433
		+ - const: rockchip,rk3568
		+
		+ - description: Radxa Compute Module 3 (CM3)
	items:	items:
	- enum:	- enum:
	- radxa,cm3-io	- radxa,cm3-io
@@ -759,26 +837,53 @@ properties:
	- const: radxa,rockpis	- const: radxa,rockpis
	- const: rockchip,rk3308	- const: rockchip,rk3308

	- - description: Radxa ~~Rock2~~ Square	+ - description: Radxa Rock 2 Square
	items:	items:
	- const: radxa,rock2-square	- const: radxa,rock2-square
	- const: rockchip,rk3288	- const: rockchip,rk3288

	- - description: Radxa ~~ROCK3~~ ~~Model A~~	+ - description: Radxa ROCK 3A
	items:	items:
	- const: radxa,rock3a	- const: radxa,rock3a
	- const: rockchip,rk3568	- const: rockchip,rk3568

	- - description: Radxa ROCK ~~5 Model A~~	+ - description: Radxa ROCK 3B
		+ items:
		+ - const: radxa,rock-3b
		+ - const: rockchip,rk3568
		+
		+ - description: Radxa ROCK 3C
		+ items:
		+ - const: radxa,rock-3c
		+ - const: rockchip,rk3566
		+
		+ - description: Radxa ROCK 5 ITX
		+ items:
		+ - const: radxa,rock-5-itx
		+ - const: rockchip,rk3588
		+
		+ - description: Radxa ROCK 5A
	items:	items:
	- const: radxa,rock-5a	- const: radxa,rock-5a
	- const: rockchip,rk3588s	- const: rockchip,rk3588s

	- - description: Radxa ROCK ~~5 Model B~~	+ - description: Radxa ROCK 5B
	items:	items:
	- const: radxa,rock-5b	- const: radxa,rock-5b
	- const: rockchip,rk3588	- const: rockchip,rk3588

		+ - description: Radxa ROCK S0
		+ items:
		+ - const: radxa,rock-s0
		+ - const: rockchip,rk3308
		+
		+ - description: Radxa ZERO 3W/3E
		+ items:
		+ - enum:
		+ - radxa,zero-3e
		+ - radxa,zero-3w
		+ - const: rockchip,rk3566
		+
	- description: Rikomagic MK808 v1	- description: Rikomagic MK808 v1
	items:	items:
	- const: rikomagic,mk808	- const: rikomagic,mk808
@@ -878,6 +983,11 @@ properties:
	- const: rockchip,rv1108-evb	- const: rockchip,rv1108-evb
	- const: rockchip,rv1108	- const: rockchip,rv1108

		+ - description: Rockchip Toybrick TB-RK3588X board
		+ items:
		+ - const: rockchip,rk3588-toybrick-x0
		+ - const: rockchip,rk3588
		+
	- description: Theobroma Systems PX30-uQ7 with Haikou baseboard	- description: Theobroma Systems PX30-uQ7 with Haikou baseboard
	items:	items:
	- const: tsd,px30-ringneck-haikou	- const: tsd,px30-ringneck-haikou
@@ -898,6 +1008,12 @@ properties:
	- const: tsd,rk3588-jaguar	- const: tsd,rk3588-jaguar
	- const: rockchip,rk3588	- const: rockchip,rk3588

		+ - description: Theobroma Systems RK3588-Q7 with Haikou baseboard
		+ items:
		+ - const: tsd,rk3588-tiger-haikou
		+ - const: tsd,rk3588-tiger
		+ - const: rockchip,rk3588
		+
	- description: Tronsmart Orion R68 Meta	- description: Tronsmart Orion R68 Meta
	items:	items:
	- const: tronsmart,orion-r68-meta	- const: tronsmart,orion-r68-meta
@@ -908,6 +1024,19 @@ properties:
	- const: turing,rk1	- const: turing,rk1
	- const: rockchip,rk3588	- const: rockchip,rk3588

		+ - description: WolfVision PF5 mainboard
		+ items:
		+ - const: wolfvision,rk3568-pf5
		+ - const: rockchip,rk3568
		+
		+ - description: Xunlong Orange Pi 3B
		+ items:
		+ - enum:
		+ - xunlong,orangepi-3b-v1.1
		+ - xunlong,orangepi-3b-v2.1
		+ - const: xunlong,orangepi-3b
		+ - const: rockchip,rk3566
		+
	- description: Xunlong Orange Pi 5 Plus	- description: Xunlong Orange Pi 5 Plus
	items:	items:
	- const: xunlong,orangepi-5-plus	- const: xunlong,orangepi-5-plus
@@ -940,9 +1069,9 @@ properties:
	- const: rockchip,rk3568-evb1-v10	- const: rockchip,rk3568-evb1-v10
	- const: rockchip,rk3568	- const: rockchip,rk3568

	- - description: ~~Rockchip~~ RK3568 Banana Pi R2 Pro	+ - description: Sinovoip RK3568 Banana Pi R2 Pro
	items:	items:
	- - const: ~~rockchip~~,rk3568-bpi-r2pro	+ - const: sinovoip,rk3568-bpi-r2pro
	- const: rockchip,rk3568	- const: rockchip,rk3568

	- description: Sonoff iHost Smart Home Hub	- description: Sonoff iHost Smart Home Hub

            - rockchip,rk3368-pmu
            - rockchip,rk3399-pmu
            - rockchip,rk3568-pmu
++          - rockchip,rk3576-pmu
            - rockchip,rk3588-pmu
            - rockchip,rv1126-pmu
            - rockchip,rk3368-pmu
            - rockchip,rk3399-pmu
            - rockchip,rk3568-pmu
++          - rockchip,rk3576-pmu
            - rockchip,rk3588-pmu
            - rockchip,rv1126-pmu
        - const: syscon

  examples:
    - |
--    mlahb: ahb@38000000 {
++    ahb {
        compatible = "st,mlahb", "simple-bus";
        #address-cells = <1>;
        #size-cells = <1>;
--      reg = <0x10000000 0x40000>;
        ranges;
        dma-ranges = <0x00000000 0x38000000 0x10000>,
                     <0x10000000 0x10000000 0x60000>,

sys/contrib/device-tree/Bindings/arm/stm32/stm32.yaml
@@ -54,17 +54,31 @@ properties:
	- description: ST STM32MP151 based Boards	- description: ST STM32MP151 based Boards
	items:	items:
	- enum:	- enum:
		+ - prt,mecio1r0 # Protonic MECIO1r0
		+ - prt,mect1s # Protonic MECT1S
	- prt,prtt1a # Protonic PRTT1A	- prt,prtt1a # Protonic PRTT1A
	- prt,prtt1c # Protonic PRTT1C	- prt,prtt1c # Protonic PRTT1C
	- prt,prtt1s # Protonic PRTT1S	- prt,prtt1s # Protonic PRTT1S
	- const: st,stm32mp151	- const: st,stm32mp151

		+ - description: DH STM32MP135 DHCOR SoM based Boards
		+ items:
		+ - const: dh,stm32mp135f-dhcor-dhsbc
		+ - const: dh,stm32mp135f-dhcor-som
		+ - const: st,stm32mp135
		+
	- description: DH STM32MP151 DHCOR SoM based Boards	- description: DH STM32MP151 DHCOR SoM based Boards
	items:	items:
	- const: dh,stm32mp151a-dhcor-testbench	- const: dh,stm32mp151a-dhcor-testbench
	- const: dh,stm32mp151a-dhcor-som	- const: dh,stm32mp151a-dhcor-som
	- const: st,stm32mp151	- const: st,stm32mp151

		+ - description: ST STM32MP153 based Boards
		+ items:
		+ - enum:
		+ - prt,mecio1r1 # Protonic MECIO1r1
		+ - const: st,stm32mp153
		+
	- description: DH STM32MP153 DHCOM SoM based Boards	- description: DH STM32MP153 DHCOM SoM based Boards
	items:	items:
	- const: dh,stm32mp153c-dhcom-drc02	- const: dh,stm32mp153c-dhcom-drc02

sys/contrib/device-tree/Bindings/arm/sunxi.yaml
@@ -56,6 +56,26 @@ properties:
	- const: anbernic,rg-nano	- const: anbernic,rg-nano
	- const: allwinner,sun8i-v3s	- const: allwinner,sun8i-v3s

		+ - description: Anbernic RG35XX (2024)
		+ items:
		+ - const: anbernic,rg35xx-2024
		+ - const: allwinner,sun50i-h700
		+
		+ - description: Anbernic RG35XX H
		+ items:
		+ - const: anbernic,rg35xx-h
		+ - const: allwinner,sun50i-h700
		+
		+ - description: Anbernic RG35XX Plus
		+ items:
		+ - const: anbernic,rg35xx-plus
		+ - const: allwinner,sun50i-h700
		+
		+ - description: Anbernic RG35XX SP
		+ items:
		+ - const: anbernic,rg35xx-sp
		+ - const: allwinner,sun50i-h700
		+
	- description: Amarula A64 Relic	- description: Amarula A64 Relic
	items:	items:
	- const: amarula,a64-relic	- const: amarula,a64-relic
@@ -693,12 +713,12 @@ properties:
	- const: olimex,a64-teres-i	- const: olimex,a64-teres-i
	- const: allwinner,sun50i-a64	- const: allwinner,sun50i-a64

	- - description: Pine64	+ - description: Pine64 PINE A64
	items:	items:
	- const: pine64,pine64	- const: pine64,pine64
	- const: allwinner,sun50i-a64	- const: allwinner,sun50i-a64

	- - description: Pine64+	+ - description: Pine64 PINE A64+
	items:	items:
	- const: pine64,pine64-plus	- const: pine64,pine64-plus
	- const: allwinner,sun50i-a64	- const: allwinner,sun50i-a64
@@ -709,17 +729,17 @@ properties:
	- const: sochip,s3	- const: sochip,s3
	- const: allwinner,sun8i-v3	- const: allwinner,sun8i-v3

	- - description: Pine64 ~~PineH64~~ ~~model~~ A	+ - description: Pine64 PINE H64 Model A
	items:	items:
	- const: pine64,pine-h64	- const: pine64,pine-h64
	- const: allwinner,sun50i-h6	- const: allwinner,sun50i-h6

	- - description: Pine64 ~~PineH64~~ ~~model~~ B	+ - description: Pine64 PINE H64 Model B
	items:	items:
	- const: pine64,pine-h64-model-b	- const: pine64,pine-h64-model-b
	- const: allwinner,sun50i-h6	- const: allwinner,sun50i-h6

	- - description: Pine64 LTS	+ - description: Pine64 PINE A64 LTS
	items:	items:
	- const: pine64,pine64-lts	- const: pine64,pine64-lts
	- const: allwinner,sun50i-r18	- const: allwinner,sun50i-r18
@@ -748,17 +768,17 @@ properties:
	- const: pine64,pinephone	- const: pine64,pinephone
	- const: allwinner,sun50i-a64	- const: allwinner,sun50i-a64

	- - description: Pine64 PineTab, ~~Development~~ Sample	+ - description: Pine64 PineTab Developer Sample
	items:	items:
	- const: pine64,pinetab	- const: pine64,pinetab
	- const: allwinner,sun50i-a64	- const: allwinner,sun50i-a64

	- - description: Pine64 PineTab, Early ~~Adopter's batch (and maybe later ones)~~	+ - description: Pine64 PineTab Early Adopter
	items:	items:
	- const: pine64,pinetab-early-adopter	- const: pine64,pinetab-early-adopter
	- const: allwinner,sun50i-a64	- const: allwinner,sun50i-a64

	- - description: Pine64 ~~SoPine Baseboard~~	+ - description: Pine64 SOPINE
	items:	items:
	- const: pine64,sopine-baseboard	- const: pine64,sopine-baseboard
	- const: pine64,sopine	- const: pine64,sopine
@@ -774,6 +794,11 @@ properties:
	- const: pocketbook,touch-lux-3	- const: pocketbook,touch-lux-3
	- const: allwinner,sun5i-a13	- const: allwinner,sun5i-a13

		+ - description: PocketBook 614 Plus
		+ items:
		+ - const: pocketbook,614-plus
		+ - const: allwinner,sun5i-a13
		+
	- description: Point of View Protab2-IPS9	- description: Point of View Protab2-IPS9
	items:	items:
	- const: pov,protab2-ips9	- const: pov,protab2-ips9
@@ -815,6 +840,12 @@ properties:
	- const: allwinner,r7-tv-dongle	- const: allwinner,r7-tv-dongle
	- const: allwinner,sun5i-a10s	- const: allwinner,sun5i-a10s

		+ - description: Remix Mini PC
		+ items:
		+ - const: jide,remix-mini-pc
		+ - const: allwinner,sun50i-h64
		+ - const: allwinner,sun50i-a64
		+
	- description: RerVision H3-DVK	- description: RerVision H3-DVK
	items:	items:
	- const: rervision,h3-dvk	- const: rervision,h3-dvk
@@ -835,6 +866,12 @@ properties:
	- const: sinlinx,sina33	- const: sinlinx,sina33
	- const: allwinner,sun8i-a33	- const: allwinner,sun8i-a33

		+ - description: Sipeed Longan Pi 3H board for the Sipeed Longan Module 3H
		+ items:
		+ - const: sipeed,longan-pi-3h
		+ - const: sipeed,longan-module-3h
		+ - const: allwinner,sun50i-h618
		+
	- description: SourceParts PopStick v1.1	- description: SourceParts PopStick v1.1
	items:	items:
	- const: sourceparts,popstick-v1.1	- const: sourceparts,popstick-v1.1
@@ -848,6 +885,11 @@ properties:
	- const: allwinner,sl631	- const: allwinner,sl631
	- const: allwinner,sun8i-v3	- const: allwinner,sun8i-v3

		+ - description: Tanix TX1
		+ items:
		+ - const: oranth,tanix-tx1
		+ - const: allwinner,sun50i-h616
		+
	- description: Tanix TX6	- description: Tanix TX6
	items:	items:
	- const: oranth,tanix-tx6	- const: oranth,tanix-tx6

sys/contrib/device-tree/Bindings/arm/syna.txt
@@ -6,18 +6,6 @@ berlin SoCs are now Synaptics' SoCs now.

	---------------------------------------------------------------	---------------------------------------------------------------

	-Work in progress statement:
	-
	-Device tree files and bindings applying to Marvell Berlin SoCs and boards are
	-considered "unstable". Any Marvell Berlin device tree binding may change at any
	-time. Be sure to use a device tree binary and a kernel image generated from the
	-same source tree.
	-
	-Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
	-stable binding/ABI.
	-
	----------------------------------------------------------------
	-
	Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500	Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
	shall have the following properties:	shall have the following properties:

sys/contrib/device-tree/Bindings/arm/tegra.yaml
@@ -64,6 +64,14 @@ properties:
	- items:	- items:
	- const: asus,tf700t	- const: asus,tf700t
	- const: nvidia,tegra30	- const: nvidia,tegra30
		+ - description: LG Optimus 4X P880
		+ items:
		+ - const: lg,p880
		+ - const: nvidia,tegra30
		+ - description: LG Optimus Vu P895
		+ items:
		+ - const: lg,p895
		+ - const: nvidia,tegra30
	- items:	- items:
	- const: toradex,apalis_t30-eval	- const: toradex,apalis_t30-eval
	- const: toradex,apalis_t30	- const: toradex,apalis_t30
@@ -119,6 +127,48 @@ properties:
	- nvidia,norrin	- nvidia,norrin
	- const: nvidia,tegra132	- const: nvidia,tegra132
	- const: nvidia,tegra124	- const: nvidia,tegra124
		+ - items:
		+ - const: google,nyan-blaze-rev10
		+ - const: google,nyan-blaze-rev9
		+ - const: google,nyan-blaze-rev8
		+ - const: google,nyan-blaze-rev7
		+ - const: google,nyan-blaze-rev6
		+ - const: google,nyan-blaze-rev5
		+ - const: google,nyan-blaze-rev4
		+ - const: google,nyan-blaze-rev3
		+ - const: google,nyan-blaze-rev2
		+ - const: google,nyan-blaze-rev1
		+ - const: google,nyan-blaze-rev0
		+ - const: google,nyan-blaze
		+ - const: google,nyan
		+ - const: nvidia,tegra124
		+ - items:
		+ - const: google,nyan-big-rev10
		+ - const: google,nyan-big-rev9
		+ - const: google,nyan-big-rev8
		+ - const: google,nyan-big-rev7
		+ - const: google,nyan-big-rev6
		+ - const: google,nyan-big-rev5
		+ - const: google,nyan-big-rev4
		+ - const: google,nyan-big-rev3
		+ - const: google,nyan-big-rev2
		+ - const: google,nyan-big-rev1
		+ - const: google,nyan-big-rev0
		+ - const: google,nyan-big
		+ - const: google,nyan
		+ - const: nvidia,tegra124
		+ - items:
		+ - const: google,nyan-big-rev7
		+ - const: google,nyan-big-rev6
		+ - const: google,nyan-big-rev5
		+ - const: google,nyan-big-rev4
		+ - const: google,nyan-big-rev3
		+ - const: google,nyan-big-rev2
		+ - const: google,nyan-big-rev1
		+ - const: google,nyan-big-rev0
		+ - const: google,nyan-big
		+ - const: google,nyan
		+ - const: nvidia,tegra124
	- items:	- items:
	- enum:	- enum:
	- nvidia,darcy	- nvidia,darcy

sys/contrib/device-tree/Bindings/arm/tegra/nvidia,tegra186-pmc.yaml
@@ -27,7 +27,7 @@ properties:
	- const: pmc	- const: pmc
	- const: wake	- const: wake
	- const: aotag	- const: aotag
	- - ~~const:~~ scratch	+ - enum: [ scratch, misc ]
	- const: misc	- const: misc

	interrupt-controller: true	interrupt-controller: true
@@ -41,25 +41,43 @@ properties:
	description: If present, inverts the PMU interrupt signal.	description: If present, inverts the PMU interrupt signal.
	$ref: /schemas/types.yaml#/definitions/flag	$ref: /schemas/types.yaml#/definitions/flag

	-if:	+allOf:
	- properties:	+ - if:
	- compatible:	+ properties:
	- ~~contains:~~	+ compatible:
	- ~~const: nvidia,tegra186-pmc~~	+ contains:
	-then:	+ const: nvidia,tegra186-pmc
	- properties:	+ then:
	- reg:	+ properties:
	- maxItems: 4	+ reg:
	-	+ maxItems: 4
	- reg-names:	+ reg-names:
	- maxItems: 4	+ maxItems: 4
	-else:	+ contains:
	- properties:	+ const: scratch
	- reg:	+
	- minItems: 5	+ - if:
	-	+ properties:
	- reg-names:	+ compatible:
	- ~~minItems: 5~~	+ contains:
		+ const: nvidia,tegra194-pmc
		+ then:
		+ properties:
		+ reg:
		+ minItems: 5
		+ reg-names:
		+ minItems: 5
		+
		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ const: nvidia,tegra234-pmc
		+ then:
		+ properties:
		+ reg-names:
		+ contains:
		+ const: misc

	patternProperties:	patternProperties:
	"^[a-z0-9]+-[a-z0-9]+$":	"^[a-z0-9]+-[a-z0-9]+$":

sys/contrib/device-tree/Bindings/arm/ti/k3.yaml
@@ -25,6 +25,12 @@ properties:
	- ti,am62a7-sk	- ti,am62a7-sk
	- const: ti,am62a7	- const: ti,am62a7

		+ - description: K3 AM62A7 SoC PHYTEC phyBOARD-Lyra
		+ items:
		+ - const: phytec,am62a7-phyboard-lyra-rdk
		+ - const: phytec,am62a-phycore-som
		+ - const: ti,am62a7
		+
	- description: K3 AM62P5 SoC and Boards	- description: K3 AM62P5 SoC and Boards
	items:	items:
	- enum:	- enum:
@@ -87,12 +93,20 @@ properties:
	- const: tq,am642-tqma6442l	- const: tq,am642-tqma6442l
	- const: ti,am642	- const: ti,am642

		+ - description: K3 AM642 SoC SolidRun SoM based boards
		+ items:
		+ - enum:
		+ - solidrun,am642-hummingboard-t
		+ - const: solidrun,am642-sr-som
		+ - const: ti,am642
		+
	- description: K3 AM654 SoC	- description: K3 AM654 SoC
	items:	items:
	- enum:	- enum:
	- siemens,iot2050-advanced	- siemens,iot2050-advanced
	- siemens,iot2050-advanced-m2	- siemens,iot2050-advanced-m2
	- siemens,iot2050-advanced-pg2	- siemens,iot2050-advanced-pg2
		+ - siemens,iot2050-advanced-sm
	- siemens,iot2050-basic	- siemens,iot2050-basic
	- siemens,iot2050-basic-pg2	- siemens,iot2050-basic-pg2
	- ti,am654-evm	- ti,am654-evm
@@ -123,6 +137,13 @@ properties:
	- ti,j721s2-evm	- ti,j721s2-evm
	- const: ti,j721s2	- const: ti,j721s2

		+ - description: K3 J722S SoC and Boards
		+ items:
		+ - enum:
		+ - beagle,am67a-beagley-ai
		+ - ti,j722s-evm
		+ - const: ti,j722s
		+
	- description: K3 J784s4 SoC	- description: K3 J784s4 SoC
	items:	items:
	- enum:	- enum:

sys/contrib/device-tree/Bindings/ata/ahci-platform.yaml
@@ -30,6 +30,8 @@ select:
	- marvell,armada-3700-ahci	- marvell,armada-3700-ahci
	- marvell,armada-8k-ahci	- marvell,armada-8k-ahci
	- marvell,berlin2q-ahci	- marvell,berlin2q-ahci
		+ - qcom,apq8064-ahci
		+ - qcom,ipq806x-ahci
	- socionext,uniphier-pro4-ahci	- socionext,uniphier-pro4-ahci
	- socionext,uniphier-pxs2-ahci	- socionext,uniphier-pxs2-ahci
	- socionext,uniphier-pxs3-ahci	- socionext,uniphier-pxs3-ahci
@@ -45,6 +47,8 @@ properties:
	- marvell,armada-8k-ahci	- marvell,armada-8k-ahci
	- marvell,berlin2-ahci	- marvell,berlin2-ahci
	- marvell,berlin2q-ahci	- marvell,berlin2q-ahci
		+ - qcom,apq8064-ahci
		+ - qcom,ipq806x-ahci
	- socionext,uniphier-pro4-ahci	- socionext,uniphier-pro4-ahci
	- socionext,uniphier-pxs2-ahci	- socionext,uniphier-pxs2-ahci
	- socionext,uniphier-pxs3-ahci	- socionext,uniphier-pxs3-ahci
@@ -64,11 +68,11 @@ properties:

	clocks:	clocks:
	minItems: 1	minItems: 1
	- maxItems: 3	+ maxItems: 5

	clock-names:	clock-names:
	minItems: 1	minItems: 1
	- maxItems: 3	+ maxItems: 5

	interrupts:	interrupts:
	maxItems: 1	maxItems: 1
@@ -97,6 +101,31 @@ required:

	allOf:	allOf:
	- $ref: ahci-common.yaml#	- $ref: ahci-common.yaml#
		+
		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ enum:
		+ - qcom,apq8064-ahci
		+ - qcom,ipq806x-ahci
		+ then:
		+ properties:
		+ clocks:
		+ minItems: 5
		+ clock-names:
		+ items:
		+ - const: slave_iface
		+ - const: iface
		+ - const: core
		+ - const: rxoob
		+ - const: pmalive
		+ required:
		+ - phys
		+ - phy-names
		+ - clocks
		+ - clock-names
		+
	- if:	- if:
	properties:	properties:
	compatible:	compatible:

sys/contrib/device-tree/Bindings/ata/cirrus,ep9312-pata.yaml
@@ -0,0 +1,42 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/ata/cirrus,ep9312-pata.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Cirrus Logic EP9312 PATA controller
			+
			+maintainers:
			+ - Damien Le Moal <dlemoal@kernel.org>
			+
			+properties:
			+ compatible:
			+ oneOf:
			+ - const: cirrus,ep9312-pata
			+ - items:
			+ - const: cirrus,ep9315-pata
			+ - const: cirrus,ep9312-pata
			+
			+ reg:
			+ maxItems: 1
			+
			+ interrupts:
			+ maxItems: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - interrupts
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ ide@800a0000 {
			+ compatible = "cirrus,ep9312-pata";
			+ reg = <0x800a0000 0x38>;
			+ interrupt-parent = <&vic1>;
			+ interrupts = <8>;
			+ pinctrl-names = "default";
			+ pinctrl-0 = <&ide_default_pins>;
			+ };

sys/contrib/device-tree/Bindings/ata/fsl,ahci.yaml
@@ -0,0 +1,64 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/ata/fsl,ahci.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Freescale QorIQ AHCI SATA Controller
			+
			+maintainers:
			+ - Frank Li <Frank.Li@nxp.com>
			+
			+properties:
			+ compatible:
			+ oneOf:
			+ - description: SATA controller for ls1012a
			+ items:
			+ - const: fsl,ls1012a-ahci
			+ - const: fsl,ls1043a-ahci
			+ - enum:
			+ - fsl,ls1021a-ahci
			+ - fsl,ls1028a-ahci
			+ - fsl,ls1043a-ahci
			+ - fsl,ls1046a-ahci
			+ - fsl,ls1088a-ahci
			+ - fsl,ls2080a-ahci
			+ - fsl,lx2160a-ahci
			+
			+ reg:
			+ minItems: 1
			+ maxItems: 2
			+
			+ reg-names:
			+ items:
			+ - const: ahci
			+ - const: sata-ecc
			+ minItems: 1
			+
			+ clocks:
			+ maxItems: 1
			+
			+ interrupts:
			+ maxItems: 1
			+
			+ dma-coherent: true
			+
			+required:
			+ - compatible
			+ - reg
			+ - clocks
			+ - interrupts
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/interrupt-controller/arm-gic.h>
			+
			+ sata@3200000 {
			+ compatible = "fsl,ls1021a-ahci";
			+ reg = <0x3200000 0x10000>;
			+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			+ clocks = <&platform_clk 1>;
			+ dma-coherent;
			+ };

sys/contrib/device-tree/Bindings/ata/fsl,imx-pata.yaml
@@ -0,0 +1,42 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/ata/fsl,imx-pata.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Freescale i.MX PATA Controller
			+
			+maintainers:
			+ - Animesh Agarwal <animeshagarwal28@gmail.com>
			+
			+properties:
			+ compatible:
			+ oneOf:
			+ - items:
			+ - enum:
			+ - fsl,imx31-pata
			+ - fsl,imx51-pata
			+ - const: fsl,imx27-pata
			+ - const: fsl,imx27-pata
			+
			+ reg:
			+ maxItems: 1
			+
			+ interrupts:
			+ items:
			+ - description: PATA Controller interrupts
			+
			+ clocks:
			+ items:
			+ - description: PATA Controller clocks
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ pata: pata@83fe0000 {
			+ compatible = "fsl,imx51-pata", "fsl,imx27-pata";
			+ reg = <0x83fe0000 0x4000>;
			+ interrupts = <70>;
			+ clocks = <&clks 161>;
			+ };

sys/contrib/device-tree/Bindings/ata/imx-sata.yaml
@@ -19,6 +19,7 @@ properties:
	- fsl,imx53-ahci	- fsl,imx53-ahci
	- fsl,imx6q-ahci	- fsl,imx6q-ahci
	- fsl,imx6qp-ahci	- fsl,imx6qp-ahci
		+ - fsl,imx8qm-ahci

	reg:	reg:
	maxItems: 1	maxItems: 1
@@ -27,12 +28,14 @@ properties:
	maxItems: 1	maxItems: 1

	clocks:	clocks:
		+ minItems: 2
	items:	items:
	- description: sata clock	- description: sata clock
	- description: sata reference clock	- description: sata reference clock
	- description: ahb clock	- description: ahb clock

	clock-names:	clock-names:
		+ minItems: 2
	items:	items:
	- const: sata	- const: sata
	- const: sata_ref	- const: sata_ref
@@ -58,6 +61,25 @@ properties:
	$ref: /schemas/types.yaml#/definitions/flag	$ref: /schemas/types.yaml#/definitions/flag
	description: if present, disable spread-spectrum clocking on the SATA link.	description: if present, disable spread-spectrum clocking on the SATA link.

		+ phys:
		+ items:
		+ - description: phandle to SATA PHY.
		+ Since "REXT" pin is only present for first lane of i.MX8QM PHY, it's
		+ calibration result will be stored, passed through second lane, and
		+ shared with all three lanes PHY. The first two lanes PHY are used as
		+ calibration PHYs, although only the third lane PHY is used by SATA.
		+ - description: phandle to the first lane PHY of i.MX8QM.
		+ - description: phandle to the second lane PHY of i.MX8QM.
		+
		+ phy-names:
		+ items:
		+ - const: sata-phy
		+ - const: cali-phy0
		+ - const: cali-phy1
		+
		+ power-domains:
		+ maxItems: 1
		+
	required:	required:
	- compatible	- compatible
	- reg	- reg
@@ -65,6 +87,31 @@ required:
	- clocks	- clocks
	- clock-names	- clock-names

		+allOf:
		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ enum:
		+ - fsl,imx53-ahci
		+ - fsl,imx6q-ahci
		+ - fsl,imx6qp-ahci
		+ then:
		+ properties:
		+ clock-names:
		+ minItems: 3
		+
		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ enum:
		+ - fsl,imx8qm-ahci
		+ then:
		+ properties:
		+ clock-names:
		+ minItems: 2
		+
	additionalProperties: false	additionalProperties: false

	examples:	examples:

sys/contrib/device-tree/Bindings/ata/mediatek,mtk-ahci.yaml
@@ -0,0 +1,98 @@
			+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/ata/mediatek,mtk-ahci.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MediaTek Serial ATA controller
			+
			+maintainers:
			+ - Ryder Lee <ryder.lee@mediatek.com>
			+
			+allOf:
			+ - $ref: ahci-common.yaml#
			+
			+properties:
			+ compatible:
			+ items:
			+ - enum:
			+ - mediatek,mt7622-ahci
			+ - const: mediatek,mtk-ahci
			+
			+ reg:
			+ maxItems: 1
			+
			+ interrupts:
			+ maxItems: 1
			+
			+ interrupt-names:
			+ const: hostc
			+
			+ clocks:
			+ maxItems: 5
			+
			+ clock-names:
			+ items:
			+ - const: ahb
			+ - const: axi
			+ - const: asic
			+ - const: rbc
			+ - const: pm
			+
			+ power-domains:
			+ maxItems: 1
			+
			+ resets:
			+ maxItems: 3
			+
			+ reset-names:
			+ items:
			+ - const: axi
			+ - const: sw
			+ - const: reg
			+
			+ mediatek,phy-mode:
			+ description: System controller phandle, used to enable SATA function
			+ $ref: /schemas/types.yaml#/definitions/phandle
			+
			+required:
			+ - reg
			+ - interrupts
			+ - interrupt-names
			+ - clocks
			+ - clock-names
			+ - phys
			+ - phy-names
			+ - ports-implemented
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/mt7622-clk.h>
			+ #include <dt-bindings/interrupt-controller/arm-gic.h>
			+ #include <dt-bindings/phy/phy.h>
			+ #include <dt-bindings/power/mt7622-power.h>
			+ #include <dt-bindings/reset/mt7622-reset.h>
			+
			+ sata@1a200000 {
			+ compatible = "mediatek,mt7622-ahci", "mediatek,mtk-ahci";
			+ reg = <0x1a200000 0x1100>;
			+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
			+ interrupt-names = "hostc";
			+ clocks = <&pciesys CLK_SATA_AHB_EN>,
			+ <&pciesys CLK_SATA_AXI_EN>,
			+ <&pciesys CLK_SATA_ASIC_EN>,
			+ <&pciesys CLK_SATA_RBC_EN>,
			+ <&pciesys CLK_SATA_PM_EN>;
			+ clock-names = "ahb", "axi", "asic", "rbc", "pm";
			+ phys = <&u3port1 PHY_TYPE_SATA>;
			+ phy-names = "sata-phy";
			+ ports-implemented = <0x1>;
			+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
			+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
			+ <&pciesys MT7622_SATA_PHY_SW_RST>,
			+ <&pciesys MT7622_SATA_PHY_REG_RST>;
			+ reset-names = "axi", "sw", "reg";
			+ mediatek,phy-mode = <&pciesys>;
			+ };

    ports-implemented:
      const: 1
++  power-domains:
++    maxItems: 1
++
    sata-port@0:
      $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port

sys/contrib/device-tree/Bindings/ata/ti,da850-ahci.yaml
@@ -0,0 +1,39 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/ata/ti,da850-ahci.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: TI DA850 AHCI SATA Controller
			+
			+maintainers:
			+ - Animesh Agarwal <animeshagarwal28@gmail.com>
			+
			+properties:
			+ compatible:
			+ const: ti,da850-ahci
			+
			+ reg:
			+ items:
			+ - description: Address and size of the register map as defined by the AHCI 1.1 standard.
			+ - description:
			+ Address and size of Power Down Control Register (PWRDN) for enabling/disabling the SATA clock
			+ receiver.
			+
			+ interrupts:
			+ maxItems: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - interrupts
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ sata@218000 {
			+ compatible = "ti,da850-ahci";
			+ reg = <0x218000 0x2000>, <0x22c018 0x4>;
			+ interrupts = <67>;
			+ };

  examples:
    - |
      lcd@10008000 {
--            compatible = "arm,versatile-lcd";
++        compatible = "arm,versatile-lcd";
--            reg = <0x10008000 0x1000>;
++        reg = <0x10008000 0x1000>;
      };

sys/contrib/device-tree/Bindings/auxdisplay/gpio-7-segment.yaml
@@ -0,0 +1,55 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/auxdisplay/gpio-7-segment.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: GPIO based LED segment display
			+
			+maintainers:
			+ - Chris Packham <chris.packham@alliedtelesis.co.nz>
			+
			+properties:
			+ compatible:
			+ const: gpio-7-segment
			+
			+ segment-gpios:
			+ description: \|
			+ An array of GPIOs one per segment. The first GPIO corresponds to the A
			+ segment, the seventh GPIO corresponds to the G segment. Some LED blocks
			+ also have a decimal point which can be specified as an optional eighth
			+ segment.
			+
			+ -a-
			+ \| \|
			+ f b
			+ \| \|
			+ -g-
			+ \| \|
			+ e c
			+ \| \|
			+ -d- dp
			+
			+ minItems: 7
			+ maxItems: 8
			+
			+required:
			+ - segment-gpios
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+
			+ #include <dt-bindings/gpio/gpio.h>
			+
			+ led-7seg {
			+ compatible = "gpio-7-segment";
			+ segment-gpios = <&gpio 0 GPIO_ACTIVE_LOW>,
			+ <&gpio 1 GPIO_ACTIVE_LOW>,
			+ <&gpio 2 GPIO_ACTIVE_LOW>,
			+ <&gpio 3 GPIO_ACTIVE_LOW>,
			+ <&gpio 4 GPIO_ACTIVE_LOW>,
			+ <&gpio 5 GPIO_ACTIVE_LOW>,
			+ <&gpio 6 GPIO_ACTIVE_LOW>;
			+ };

sys/contrib/device-tree/Bindings/auxdisplay/hit,hd44780.yaml
@@ -84,42 +84,44 @@ additionalProperties: false
	examples:	examples:
	- \|	- \|
	#include <dt-bindings/gpio/gpio.h>	#include <dt-bindings/gpio/gpio.h>
	- auxdisplay {	+ display-controller {
	- compatible = "hit,hd44780";	+ compatible = "hit,hd44780";
	-	+
	- data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>,	+ data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>,
	- <&hc595 1 GPIO_ACTIVE_HIGH>,	+ <&hc595 1 GPIO_ACTIVE_HIGH>,
	- <&hc595 2 GPIO_ACTIVE_HIGH>,	+ <&hc595 2 GPIO_ACTIVE_HIGH>,
	- <&hc595 3 GPIO_ACTIVE_HIGH>;	+ <&hc595 3 GPIO_ACTIVE_HIGH>;
	- enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;	+ enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
	- rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;	+ rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
	-	+
	- display-height-chars = <2>;	+ display-height-chars = <2>;
	- display-width-chars = <16>;	+ display-width-chars = <16>;
	};	};
		+
	- \|	- \|
	#include <dt-bindings/gpio/gpio.h>	#include <dt-bindings/gpio/gpio.h>
	i2c {	i2c {
	- #address-cells = <1>;	+ #address-cells = <1>;
	- #size-cells = <0>;	+ #size-cells = <0>;
	-	+
	- pcf8574: pcf8574@27 {	+ pcf8574: gpio-expander@27 {
	- compatible = "nxp,pcf8574";	+ compatible = "nxp,pcf8574";
	- reg = <0x27>;	+ reg = <0x27>;
	- gpio-controller;	+ gpio-controller;
	- #gpio-cells = <2>;	+ #gpio-cells = <2>;
	- };	+ };
	};	};
	- hd44780 {	+
	- compatible = "hit,hd44780";	+ display-controller {
	- display-height-chars = <2>;	+ compatible = "hit,hd44780";
	- display-~~width~~-chars = ~~<16>;~~	+ display-height-chars = <2>;
	- data-gpios = <&pcf8574 4 0>,	+ display-width-chars = <16>;
	- <&pcf8574 5 0>,	+ data-gpios = <&pcf8574 4 GPIO_ACTIVE_HIGH>,
	- <&pcf8574 6 0>,	+ <&pcf8574 5 GPIO_ACTIVE_HIGH>,
	- <&pcf8574 7 ~~0>;~~	+ <&pcf8574 6 GPIO_ACTIVE_HIGH>,
	- enable-gpios = <&pcf8574 2 0>;	+ <&pcf8574 7 GPIO_ACTIVE_HIGH>;
	- rs-gpios = <&pcf8574 0 0>;	+ enable-gpios = <&pcf8574 2 GPIO_ACTIVE_HIGH>;
	- rw-gpios = <&pcf8574 1 ~~0>;~~	+ rs-gpios = <&pcf8574 0 GPIO_ACTIVE_HIGH>;
	- backlight-gpios = <&pcf8574 3 0>;	+ rw-gpios = <&pcf8574 1 GPIO_ACTIVE_HIGH>;
		+ backlight-gpios = <&pcf8574 3 GPIO_ACTIVE_HIGH>;
	};	};

sys/contrib/device-tree/Bindings/auxdisplay/holtek,ht16k33.yaml
@@ -74,31 +74,31 @@ examples:
	#include <dt-bindings/input/input.h>	#include <dt-bindings/input/input.h>
	#include <dt-bindings/leds/common.h>	#include <dt-bindings/leds/common.h>
	i2c {	i2c {
	- #address-cells = <1>;	+ #address-cells = <1>;
	- #size-cells = <0>;	+ #size-cells = <0>;
	-	+
	- ht16k33: ht16k33@70 {	+ display-controller@70 {
	- compatible = "holtek,ht16k33";	+ compatible = "holtek,ht16k33";
	- reg = <0x70>;	+ reg = <0x70>;
	- refresh-rate-hz = <20>;	+ refresh-rate-hz = <20>;
	- interrupt-parent = <&gpio4>;	+ interrupt-parent = <&gpio4>;
	- interrupts = <5 (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_EDGE_RISING)>;	+ interrupts = <5 (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_EDGE_RISING)>;
	- debounce-delay-ms = <50>;	+ debounce-delay-ms = <50>;
	- linux,keymap = <MATRIX_KEY(2, 0, KEY_F6)>,	+ linux,keymap = <MATRIX_KEY(2, 0, KEY_F6)>,
	- <MATRIX_KEY(3, 0, KEY_F8)>,	+ <MATRIX_KEY(3, 0, KEY_F8)>,
	- <MATRIX_KEY(4, 0, KEY_F10)>,	+ <MATRIX_KEY(4, 0, KEY_F10)>,
	- <MATRIX_KEY(5, 0, KEY_F4)>,	+ <MATRIX_KEY(5, 0, KEY_F4)>,
	- <MATRIX_KEY(6, 0, KEY_F2)>,	+ <MATRIX_KEY(6, 0, KEY_F2)>,
	- <MATRIX_KEY(2, 1, KEY_F5)>,	+ <MATRIX_KEY(2, 1, KEY_F5)>,
	- <MATRIX_KEY(3, 1, KEY_F7)>,	+ <MATRIX_KEY(3, 1, KEY_F7)>,
	- <MATRIX_KEY(4, 1, KEY_F9)>,	+ <MATRIX_KEY(4, 1, KEY_F9)>,
	- <MATRIX_KEY(5, 1, KEY_F3)>,	+ <MATRIX_KEY(5, 1, KEY_F3)>,
	- <MATRIX_KEY(6, 1, KEY_F1)>;	+ <MATRIX_KEY(6, 1, KEY_F1)>;
	-	+
	- led {	+ led {
	- color = <LED_COLOR_ID_RED>;	+ color = <LED_COLOR_ID_RED>;
	- function = LED_FUNCTION_BACKLIGHT;	+ function = LED_FUNCTION_BACKLIGHT;
	- linux,default-trigger = "backlight";	+ linux,default-trigger = "backlight";
	- };
	};	};
	- };	+ };
		+ };

  examples:
    - |
      lcd: lcd@17fff000 {
--            compatible = "img,boston-lcd";
++        compatible = "img,boston-lcd";
--            reg = <0x17fff000 0x8>;
++        reg = <0x17fff000 0x8>;
      };

sys/contrib/device-tree/Bindings/auxdisplay/maxim,max6959.yaml
@@ -0,0 +1,44 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/auxdisplay/maxim,max6959.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MAX6958/6959 7-segment LED display controller
			+
			+maintainers:
			+ - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
			+
			+description:
			+ The Maxim MAX6958/6959 7-segment LED display controller provides
			+ an I2C interface to up to four 7-segment LED digits. The MAX6959,
			+ in comparison to MAX6958, adds input support. Type of the chip can
			+ be autodetected via specific register read, and hence the features
			+ may be enabled in the driver at run-time, in case they are requested
			+ via Device Tree. A given hardware is simple and does not provide
			+ any additional pins, such as reset or power enable.
			+
			+properties:
			+ compatible:
			+ const: maxim,max6959
			+
			+ reg:
			+ maxItems: 1
			+
			+required:
			+ - compatible
			+ - reg
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ display-controller@38 {
			+ compatible = "maxim,max6959";
			+ reg = <0x38>;
			+ };
			+ };

sys/contrib/device-tree/Bindings/board/fsl,bcsr.yaml
@@ -0,0 +1,32 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/board/fsl,bcsr.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Board Control and Status
			+
			+maintainers:
			+ - Frank Li <Frank.Li@nxp.com>
			+
			+properties:
			+ compatible:
			+ enum:
			+ - fsl,mpc8360mds-bcsr
			+
			+ reg:
			+ maxItems: 1
			+
			+required:
			+ - compatible
			+ - reg
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ board@f8000000 {
			+ compatible = "fsl,mpc8360mds-bcsr";
			+ reg = <0xf8000000 0x8000>;
			+ };
			+

sys/contrib/device-tree/Bindings/board/fsl,fpga-qixis-i2c.yaml
@@ -0,0 +1,70 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/board/fsl,fpga-qixis-i2c.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Freescale on-board FPGA connected on I2C bus
			+
			+maintainers:
			+ - Frank Li <Frank.Li@nxp.com>
			+
			+properties:
			+ compatible:
			+ oneOf:
			+ - items:
			+ - enum:
			+ - fsl,bsc9132qds-fpga
			+ - const: fsl,fpga-qixis-i2c
			+ - items:
			+ - enum:
			+ - fsl,ls1028aqds-fpga
			+ - fsl,lx2160aqds-fpga
			+ - const: fsl,fpga-qixis-i2c
			+ - const: simple-mfd
			+
			+ interrupts:
			+ maxItems: 1
			+
			+ reg:
			+ maxItems: 1
			+
			+ mux-controller:
			+ $ref: /schemas/mux/reg-mux.yaml
			+
			+required:
			+ - compatible
			+ - reg
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ board-control@66 {
			+ compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
			+ reg = <0x66>;
			+ };
			+ };
			+
			+ - \|
			+ i2c {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ board-control@66 {
			+ compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
			+ "simple-mfd";
			+ reg = <0x66>;
			+
			+ mux-controller {
			+ compatible = "reg-mux";
			+ #mux-control-cells = <1>;
			+ mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
			+ };
			+ };
			+ };
			+

sys/contrib/device-tree/Bindings/board/fsl,fpga-qixis.yaml
@@ -0,0 +1,81 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/board/fsl,fpga-qixis.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Freescale on-board FPGA/CPLD
			+
			+maintainers:
			+ - Frank Li <Frank.Li@nxp.com>
			+
			+properties:
			+ compatible:
			+ oneOf:
			+ - items:
			+ - const: fsl,p1022ds-fpga
			+ - const: fsl,fpga-ngpixis
			+ - items:
			+ - enum:
			+ - fsl,ls1088aqds-fpga
			+ - fsl,ls1088ardb-fpga
			+ - fsl,ls2080aqds-fpga
			+ - fsl,ls2080ardb-fpga
			+ - const: fsl,fpga-qixis
			+ - items:
			+ - enum:
			+ - fsl,ls1043aqds-fpga
			+ - fsl,ls1043ardb-fpga
			+ - fsl,ls1046aqds-fpga
			+ - fsl,ls1046ardb-fpga
			+ - fsl,ls208xaqds-fpga
			+ - const: fsl,fpga-qixis
			+ - const: simple-mfd
			+ - enum:
			+ - fsl,ls1043ardb-cpld
			+ - fsl,ls1046ardb-cpld
			+ - fsl,t1040rdb-cpld
			+ - fsl,t1042rdb-cpld
			+ - fsl,t1042rdb_pi-cpld
			+
			+ interrupts:
			+ maxItems: 1
			+
			+ reg:
			+ maxItems: 1
			+
			+ "#address-cells":
			+ const: 1
			+
			+ "#size-cells":
			+ const: 1
			+
			+ ranges:
			+ maxItems: 1
			+
			+patternProperties:
			+ '^mdio-mux@[a-f0-9,]+$':
			+ $ref: /schemas/net/mdio-mux-mmioreg.yaml
			+
			+required:
			+ - compatible
			+ - reg
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/interrupt-controller/irq.h>
			+ board-control@3 {
			+ compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
			+ reg = <3 0x30>;
			+ interrupt-parent = <&mpic>;
			+ interrupts = <8 IRQ_TYPE_LEVEL_LOW 0 0>;
			+ };
			+
			+ - \|
			+ board-control@3 {
			+ compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
			+ reg = <0x3 0x10000>;
			+ };
			+

            - const: brcm,gisb-arb
        - items:
            - enum:
++              - brcm,bcm74165-gisb-arb  # for V7 new style 16nm chips
                - brcm,bcm7278-gisb-arb  # for V7 28nm chips
                - brcm,bcm7435-gisb-arb  # for newer 40nm chips
                - brcm,bcm7400-gisb-arb  # for older 40nm chips and all 65nm chips

sys/contrib/device-tree/Bindings/bus/qcom,ebi2.yaml
@@ -0,0 +1,239 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/bus/qcom,ebi2.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm External Bus Interface 2 (EBI2)
			+
			+description: \|
			+ The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
			+ external memory (such as NAND or other memory-mapped peripherals) whereas
			+ LCDC handles LCD displays.
			+
			+ As it says it connects devices to an external bus interface, meaning address
			+ lines (up to 9 address lines so can only address 1KiB external memory space),
			+ data lines (16 bits), OE (output enable), ADV (address valid, used on some
			+ NOR flash memories), WE (write enable). This on top of 6 different chip selects
			+ (CS0 thru CS5) so that in theory 6 different devices can be connected.
			+
			+ Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
			+ and the bus can only come out on these pins, however if some of the pins are
			+ unused they can be left unconnected or remuxed to be used as GPIO or in some
			+ cases other orthogonal functions as well.
			+
			+ Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
			+
			+ The chip selects have the following memory range assignments. This region of
			+ memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
			+
			+ Chip Select Physical address base
			+ CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
			+ CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
			+ CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
			+ CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
			+ CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
			+ CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
			+
			+ The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
			+ August 6, 2012 contains some incomplete documentation of the EBI2.
			+
			+ FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
			+ We have not been able to figure out which bit fields these correspond to
			+ in the hardware, or what valid values exist. The current hypothesis is that
			+ this is something just used on the FAST chip selects and that the SLOW
			+ chip selects are understood fully. There is also a "byte device enable"
			+ flag somewhere for 8bit memories.
			+
			+ FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit
			+ unclear what this means, if they are mutually exclusive or can be used
			+ together, or if some chip selects are hardwired to be FAST and others are SLOW
			+ by design.
			+
			+ The XMEM registers are totally undocumented but could be partially decoded
			+ because the Cypress AN49576 Antioch Westbridge apparently has suspiciously
			+ similar register layout, see: http://www.cypress.com/file/105771/download
			+
			+maintainers:
			+ - Bjorn Andersson <andersson@kernel.org>
			+
			+properties:
			+ compatible:
			+ enum:
			+ - qcom,apq8060-ebi2
			+ - qcom,msm8660-ebi2
			+
			+ reg:
			+ items:
			+ - description: EBI2 config region
			+ - description: XMEM config region
			+
			+ reg-names:
			+ items:
			+ - const: ebi2
			+ - const: xmem
			+
			+ ranges: true
			+
			+ clocks:
			+ items:
			+ - description: EBI_2X clock
			+ - description: EBI clock
			+
			+ clock-names:
			+ items:
			+ - const: ebi2x
			+ - const: ebi2
			+
			+ '#address-cells':
			+ const: 2
			+
			+ '#size-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - reg-names
			+ - ranges
			+ - clocks
			+ - clock-names
			+ - '#address-cells'
			+ - '#size-cells'
			+
			+patternProperties:
			+ "^.*@[0-5],[0-9a-f]+$":
			+ type: object
			+ additionalProperties: true
			+ properties:
			+ reg:
			+ maxItems: 1
			+
			+ # SLOW chip selects
			+ qcom,xmem-recovery-cycles:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ description: >
			+ The time the memory continues to drive the data bus after OE
			+ is de-asserted, in order to avoid contention on the data bus.
			+ They are inserted when reading one CS and switching to another
			+ CS or read followed by write on the same CS. Minimum value is
			+ actually 1, so a value of 0 will still yield 1 recovery cycle.
			+ minimum: 0
			+ maximum: 15
			+
			+ qcom,xmem-write-hold-cycles:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ description: >
			+ The extra cycles inserted after every write minimum 1. The
			+ data out is driven from the time WE is asserted until CS is
			+ asserted. With a hold of 1 (value = 0), the CS stays active
			+ for 1 extra cycle, etc.
			+ minimum: 0
			+ maximum: 15
			+
			+ qcom,xmem-write-delta-cycles:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ description: >
			+ The initial latency for write cycles inserted for the first
			+ write to a page or burst memory.
			+ minimum: 0
			+ maximum: 255
			+
			+ qcom,xmem-read-delta-cycles:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ description: >
			+ The initial latency for read cycles inserted for the first
			+ read to a page or burst memory.
			+ minimum: 0
			+ maximum: 255
			+
			+ qcom,xmem-write-wait-cycles:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ description: >
			+ The number of wait cycles for every write access.
			+ minimum: 0
			+ maximum: 15
			+
			+ qcom,xmem-read-wait-cycles:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ description: >
			+ The number of wait cycles for every read access.
			+ minimum: 0
			+ maximum: 15
			+
			+
			+ # FAST chip selects
			+ qcom,xmem-address-hold-enable:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ description: >
			+ Holds the address for an extra cycle to meet hold time
			+ requirements with ADV assertion, when set to 1.
			+ enum: [ 0, 1 ]
			+
			+ qcom,xmem-adv-to-oe-recovery-cycles:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ description: >
			+ The number of cycles elapsed before an OE assertion, with
			+ respect to the cycle where ADV (address valid) is asserted.
			+ minimum: 0
			+ maximum: 3
			+
			+ qcom,xmem-read-hold-cycles:
			+ $ref: /schemas/types.yaml#/definitions/uint32
			+ description: >
			+ The length in cycles of the first segment of a read transfer.
			+ For a single read transfer this will be the time from CS
			+ assertion to OE assertion.
			+ minimum: 0
			+ maximum: 15
			+
			+ required:
			+ - reg
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/qcom,gcc-msm8660.h>
			+ #include <dt-bindings/interrupt-controller/irq.h>
			+ #include <dt-bindings/gpio/gpio.h>
			+
			+ external-bus@1a100000 {
			+ compatible = "qcom,msm8660-ebi2";
			+ reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
			+ reg-names = "ebi2", "xmem";
			+ ranges = <0 0x0 0x1a800000 0x00800000>,
			+ <1 0x0 0x1b000000 0x00800000>,
			+ <2 0x0 0x1b800000 0x00800000>,
			+ <3 0x0 0x1d000000 0x08000000>,
			+ <4 0x0 0x1c800000 0x00800000>,
			+ <5 0x0 0x1c000000 0x00800000>;
			+
			+ clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
			+ clock-names = "ebi2x", "ebi2";
			+
			+ #address-cells = <2>;
			+ #size-cells = <1>;
			+
			+ ethernet@2,0 {
			+ compatible = "smsc,lan9221", "smsc,lan9115";
			+ reg = <2 0x0 0x100>;
			+
			+ interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>,
			+ <&tlmm 29 IRQ_TYPE_EDGE_RISING>;
			+ reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
			+
			+ phy-mode = "mii";
			+ reg-io-width = <2>;
			+ smsc,force-external-phy;
			+ smsc,irq-push-pull;
			+
			+ /* SLOW chipselect config */
			+ qcom,xmem-recovery-cycles = <0>;
			+ qcom,xmem-write-hold-cycles = <3>;
			+ qcom,xmem-write-delta-cycles = <31>;
			+ qcom,xmem-read-delta-cycles = <28>;
			+ qcom,xmem-write-wait-cycles = <9>;
			+ qcom,xmem-read-wait-cycles = <9>;
			+ };
			+ };

sys/contrib/device-tree/Bindings/bus/st,stm32-etzpc.yaml
@@ -0,0 +1,96 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/bus/st,stm32-etzpc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: STM32 Extended TrustZone protection controller
			+
			+description: \|
			+ The ETZPC configures TrustZone security in a SoC having bus masters and
			+ devices with programmable-security attributes (securable resources).
			+
			+maintainers:
			+ - Gatien Chevallier <gatien.chevallier@foss.st.com>
			+
			+select:
			+ properties:
			+ compatible:
			+ contains:
			+ const: st,stm32-etzpc
			+ required:
			+ - compatible
			+
			+properties:
			+ compatible:
			+ items:
			+ - const: st,stm32-etzpc
			+ - const: simple-bus
			+
			+ reg:
			+ maxItems: 1
			+
			+ "#address-cells":
			+ const: 1
			+
			+ "#size-cells":
			+ const: 1
			+
			+ ranges: true
			+
			+ "#access-controller-cells":
			+ const: 1
			+ description:
			+ Contains the firewall ID associated to the peripheral.
			+
			+patternProperties:
			+ "^.*@[0-9a-f]+$":
			+ description: Peripherals
			+ type: object
			+
			+ additionalProperties: true
			+
			+ required:
			+ - access-controllers
			+
			+required:
			+ - compatible
			+ - reg
			+ - "#address-cells"
			+ - "#size-cells"
			+ - "#access-controller-cells"
			+ - ranges
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ // In this example, the usart2 device refers to rifsc as its access
			+ // controller.
			+ // Access rights are verified before creating devices.
			+
			+ #include <dt-bindings/interrupt-controller/arm-gic.h>
			+ #include <dt-bindings/clock/stm32mp13-clks.h>
			+ #include <dt-bindings/reset/stm32mp13-resets.h>
			+
			+ etzpc: bus@5c007000 {
			+ compatible = "st,stm32-etzpc", "simple-bus";
			+ reg = <0x5c007000 0x400>;
			+ #address-cells = <1>;
			+ #size-cells = <1>;
			+ #access-controller-cells = <1>;
			+ ranges;
			+
			+ usart2: serial@4c001000 {
			+ compatible = "st,stm32h7-uart";
			+ reg = <0x4c001000 0x400>;
			+ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
			+ clocks = <&rcc USART2_K>;
			+ resets = <&rcc USART2_R>;
			+ wakeup-source;
			+ dmas = <&dmamux1 43 0x400 0x5>,
			+ <&dmamux1 44 0x400 0x1>;
			+ dma-names = "rx", "tx";
			+ access-controllers = <&etzpc 17>;
			+ };
			+ };

sys/contrib/device-tree/Bindings/bus/st,stm32mp25-rifsc.yaml
@@ -0,0 +1,105 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: STM32 Resource isolation framework security controller
			+
			+maintainers:
			+ - Gatien Chevallier <gatien.chevallier@foss.st.com>
			+
			+description: \|
			+ Resource isolation framework (RIF) is a comprehensive set of hardware blocks
			+ designed to enforce and manage isolation of STM32 hardware resources like
			+ memory and peripherals.
			+
			+ The RIFSC (RIF security controller) is composed of three sets of registers,
			+ each managing a specific set of hardware resources:
			+ - RISC registers associated with RISUP logic (resource isolation device unit
			+ for peripherals), assign all non-RIF aware peripherals to zero, one or
			+ any security domains (secure, privilege, compartment).
			+ - RIMC registers: associated with RIMU logic (resource isolation master
			+ unit), assign all non RIF-aware bus master to one security domain by
			+ setting secure, privileged and compartment information on the system bus.
			+ Alternatively, the RISUP logic controlling the device port access to a
			+ peripheral can assign target bus attributes to this peripheral master port
			+ (supported attribute: CID).
			+ - RISC registers associated with RISAL logic (resource isolation device unit
			+ for address space - Lite version), assign address space subregions to one
			+ security domains (secure, privilege, compartment).
			+
			+select:
			+ properties:
			+ compatible:
			+ contains:
			+ const: st,stm32mp25-rifsc
			+ required:
			+ - compatible
			+
			+properties:
			+ compatible:
			+ items:
			+ - const: st,stm32mp25-rifsc
			+ - const: simple-bus
			+
			+ reg:
			+ maxItems: 1
			+
			+ "#address-cells":
			+ const: 1
			+
			+ "#size-cells":
			+ const: 1
			+
			+ ranges: true
			+
			+ "#access-controller-cells":
			+ const: 1
			+ description:
			+ Contains the firewall ID associated to the peripheral.
			+
			+patternProperties:
			+ "^.*@[0-9a-f]+$":
			+ description: Peripherals
			+ type: object
			+
			+ additionalProperties: true
			+
			+ required:
			+ - access-controllers
			+
			+required:
			+ - compatible
			+ - reg
			+ - "#address-cells"
			+ - "#size-cells"
			+ - "#access-controller-cells"
			+ - ranges
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ // In this example, the usart2 device refers to rifsc as its domain
			+ // controller.
			+ // Access rights are verified before creating devices.
			+
			+ #include <dt-bindings/interrupt-controller/arm-gic.h>
			+
			+ rifsc: bus@42080000 {
			+ compatible = "st,stm32mp25-rifsc", "simple-bus";
			+ reg = <0x42080000 0x1000>;
			+ #address-cells = <1>;
			+ #size-cells = <1>;
			+ #access-controller-cells = <1>;
			+ ranges;
			+
			+ usart2: serial@400e0000 {
			+ compatible = "st,stm32h7-uart";
			+ reg = <0x400e0000 0x400>;
			+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			+ clocks = <&ck_flexgen_08>;
			+ access-controllers = <&rifsc 32>;
			+ };
			+ };

sys/contrib/device-tree/Bindings/cache/qcom,llcc.yaml
@@ -21,6 +21,7 @@ properties:
	compatible:	compatible:
	enum:	enum:
	- qcom,qdu1000-llcc	- qcom,qdu1000-llcc
		+ - qcom,sa8775p-llcc
	- qcom,sc7180-llcc	- qcom,sc7180-llcc
	- qcom,sc7280-llcc	- qcom,sc7280-llcc
	- qcom,sc8180x-llcc	- qcom,sc8180x-llcc
@@ -66,7 +67,6 @@ allOf:
	compatible:	compatible:
	contains:	contains:
	enum:	enum:
	- - qcom,qdu1000-llcc
	- qcom,sc7180-llcc	- qcom,sc7180-llcc
	- qcom,sm6350-llcc	- qcom,sm6350-llcc
	then:	then:
@@ -80,6 +80,33 @@ allOf:
	- const: llcc0_base	- const: llcc0_base
	- const: llcc_broadcast_base	- const: llcc_broadcast_base

		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ enum:
		+ - qcom,sa8775p-llcc
		+ then:
		+ properties:
		+ reg:
		+ items:
		+ - description: LLCC0 base register region
		+ - description: LLCC1 base register region
		+ - description: LLCC2 base register region
		+ - description: LLCC3 base register region
		+ - description: LLCC4 base register region
		+ - description: LLCC5 base register region
		+ - description: LLCC broadcast base register region
		+ reg-names:
		+ items:
		+ - const: llcc0_base
		+ - const: llcc1_base
		+ - const: llcc2_base
		+ - const: llcc3_base
		+ - const: llcc4_base
		+ - const: llcc5_base
		+ - const: llcc_broadcast_base
		+
	- if:	- if:
	properties:	properties:
	compatible:	compatible:
@@ -104,6 +131,7 @@ allOf:
	compatible:	compatible:
	contains:	contains:
	enum:	enum:
		+ - qcom,qdu1000-llcc
	- qcom,sc8180x-llcc	- qcom,sc8180x-llcc
	- qcom,sc8280xp-llcc	- qcom,sc8280xp-llcc
	- qcom,x1e80100-llcc	- qcom,x1e80100-llcc
@@ -141,8 +169,31 @@ allOf:
	- qcom,sm8150-llcc	- qcom,sm8150-llcc
	- qcom,sm8250-llcc	- qcom,sm8250-llcc
	- qcom,sm8350-llcc	- qcom,sm8350-llcc
		+ then:
		+ properties:
		+ reg:
		+ items:
		+ - description: LLCC0 base register region
		+ - description: LLCC1 base register region
		+ - description: LLCC2 base register region
		+ - description: LLCC3 base register region
		+ - description: LLCC broadcast base register region
		+ reg-names:
		+ items:
		+ - const: llcc0_base
		+ - const: llcc1_base
		+ - const: llcc2_base
		+ - const: llcc3_base
		+ - const: llcc_broadcast_base
		+
		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ enum:
	- qcom,sm8450-llcc	- qcom,sm8450-llcc
	- qcom,sm8550-llcc	- qcom,sm8550-llcc
		+ - qcom,sm8650-llcc
	then:	then:
	properties:	properties:
	reg:	reg:
@@ -151,7 +202,8 @@ allOf:
	- description: LLCC1 base register region	- description: LLCC1 base register region
	- description: LLCC2 base register region	- description: LLCC2 base register region
	- description: LLCC3 base register region	- description: LLCC3 base register region
	- - description: LLCC broadcast ~~base~~ register region	+ - description: LLCC broadcast OR register region
		+ - description: LLCC broadcast AND register region
	reg-names:	reg-names:
	items:	items:
	- const: llcc0_base	- const: llcc0_base
@@ -159,6 +211,7 @@ allOf:
	- const: llcc2_base	- const: llcc2_base
	- const: llcc3_base	- const: llcc3_base
	- const: llcc_broadcast_base	- const: llcc_broadcast_base
		+ - const: llcc_broadcast_and_base

	additionalProperties: false	additionalProperties: false

sys/contrib/device-tree/Bindings/cache/starfive,jh8100-starlink-cache.yaml
@@ -0,0 +1,66 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: StarFive StarLink Cache Controller
			+
			+maintainers:
			+ - Joshua Yeong <joshua.yeong@starfivetech.com>
			+
			+description:
			+ StarFive's StarLink Cache Controller manages the L3 cache shared between
			+ clusters of CPU cores. The cache driver enables RISC-V non-standard cache
			+ management as an alternative to instructions in the RISC-V Zicbom extension.
			+
			+allOf:
			+ - $ref: /schemas/cache-controller.yaml#
			+
			+# We need a select here so we don't match all nodes with 'cache'
			+select:
			+ properties:
			+ compatible:
			+ contains:
			+ enum:
			+ - starfive,jh8100-starlink-cache
			+
			+ required:
			+ - compatible
			+
			+properties:
			+ compatible:
			+ items:
			+ - const: starfive,jh8100-starlink-cache
			+ - const: cache
			+
			+ reg:
			+ maxItems: 1
			+
			+unevaluatedProperties: false
			+
			+required:
			+ - compatible
			+ - reg
			+ - cache-block-size
			+ - cache-level
			+ - cache-sets
			+ - cache-size
			+ - cache-unified
			+
			+examples:
			+ - \|
			+ soc {
			+ #address-cells = <2>;
			+ #size-cells = <2>;
			+
			+ cache-controller@15000000 {
			+ compatible = "starfive,jh8100-starlink-cache", "cache";
			+ reg = <0x0 0x15000000 0x0 0x278>;
			+ cache-block-size = <64>;
			+ cache-level = <3>;
			+ cache-sets = <8192>;
			+ cache-size = <0x400000>;
			+ cache-unified;
			+ };
			+ };

sys/contrib/device-tree/Bindings/clock/airoha,en7523-scu.yaml
@@ -29,10 +29,13 @@ description: \|
	properties:	properties:
	compatible:	compatible:
	items:	items:
	- - const: airoha,en7523-scu	+ - enum:
		+ - airoha,en7523-scu
		+ - airoha,en7581-scu

	reg:	reg:
	- ~~maxItems:~~ 2	+ minItems: 2
		+ maxItems: 4

	"#clock-cells":	"#clock-cells":
	description:	description:
@@ -40,11 +43,42 @@ properties:
	clocks.	clocks.
	const: 1	const: 1

		+ '#reset-cells':
		+ description: ID of the controller reset line
		+ const: 1
		+
	required:	required:
	- compatible	- compatible
	- reg	- reg
	- '#clock-cells'	- '#clock-cells'

		+allOf:
		+ - if:
		+ properties:
		+ compatible:
		+ const: airoha,en7523-scu
		+ then:
		+ properties:
		+ reg:
		+ items:
		+ - description: scu base address
		+ - description: misc scu base address
		+
		+ '#reset-cells': false
		+
		+ - if:
		+ properties:
		+ compatible:
		+ const: airoha,en7581-scu
		+ then:
		+ properties:
		+ reg:
		+ items:
		+ - description: scu base address
		+ - description: misc scu base address
		+ - description: reset base address
		+ - description: pb scu base address
		+
	additionalProperties: false	additionalProperties: false

	examples:	examples:
@@ -56,3 +90,19 @@ examples:
	<0x1fb00000 0x1000>;	<0x1fb00000 0x1000>;
	#clock-cells = <1>;	#clock-cells = <1>;
	};	};
		+
		+ - \|
		+ soc {
		+ #address-cells = <2>;
		+ #size-cells = <2>;
		+
		+ scuclk: clock-controller@1fa20000 {
		+ compatible = "airoha,en7581-scu";
		+ reg = <0x0 0x1fa20000 0x0 0x400>,
		+ <0x0 0x1fb00000 0x0 0x90>,
		+ <0x0 0x1fb00830 0x0 0x8>,
		+ <0x0 0x1fbe3400 0x0 0xfc>;
		+ #clock-cells = <1>;
		+ #reset-cells = <1>;
		+ };
		+ };

        - description: input fixed pll div7
        - description: input hifi pll
        - description: input oscillator (usually at 24MHz)
++      - description: input sys pll
++    minItems: 6 # sys_pll is optional
    clock-names:
      items:
        - const: fclk_div7
        - const: hifi_pll
        - const: xtal
++      - const: sys_pll
++    minItems: 6 # sys_pll is optional
  required:
    - compatible
                       <&clkc_pll CLKID_FCLK_DIV5>,
                       <&clkc_pll CLKID_FCLK_DIV7>,
                       <&clkc_pll CLKID_HIFI_PLL>,
--                     <&xtal>;
++                     <&xtal>,
++                     <&clkc_pll CLKID_SYS_PLL>;
              clock-names = "fclk_div2", "fclk_div3",
                            "fclk_div5", "fclk_div7",
--                          "hifi_pll", "xtal";
++                          "hifi_pll", "xtal", "sys_pll";
          };
      };

      items:
        - description: input fixpll_in
        - description: input hifipll_in
++      - description: input syspll_in
++    minItems: 2 # syspll_in is optional
    clock-names:
      items:
        - const: fixpll_in
        - const: hifipll_in
++      - const: syspll_in
++    minItems: 2 # syspll_in is optional
  required:
    - compatible
              reg = <0 0x7c80 0 0x18c>;
              #clock-cells = <1>;
              clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
--                     <&clkc_periphs CLKID_HIFIPLL_IN>;
++                     <&clkc_periphs CLKID_HIFIPLL_IN>,
--            clock-names = "fixpll_in", "hifipll_in";
++                     <&clkc_periphs CLKID_SYSPLL_IN>;
++            clock-names = "fixpll_in", "hifipll_in", "syspll_in";
          };
      };

sys/contrib/device-tree/Bindings/clock/amlogic,axg-audio-clkc.yaml
@@ -0,0 +1,201 @@
			+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Amlogic AXG Audio Clock Controller
			+
			+maintainers:
			+ - Neil Armstrong <neil.armstrong@linaro.org>
			+ - Jerome Brunet <jbrunet@baylibre.com>
			+
			+description:
			+ The Amlogic AXG audio clock controller generates and supplies clock to the
			+ other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
			+ devices.
			+
			+properties:
			+ compatible:
			+ enum:
			+ - amlogic,axg-audio-clkc
			+ - amlogic,g12a-audio-clkc
			+ - amlogic,sm1-audio-clkc
			+
			+ '#clock-cells':
			+ const: 1
			+
			+ '#reset-cells':
			+ const: 1
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ minItems: 1
			+ items:
			+ - description: main peripheral bus clock
			+ - description: input plls to generate clock signals N0
			+ - description: input plls to generate clock signals N1
			+ - description: input plls to generate clock signals N2
			+ - description: input plls to generate clock signals N3
			+ - description: input plls to generate clock signals N4
			+ - description: input plls to generate clock signals N5
			+ - description: input plls to generate clock signals N6
			+ - description: input plls to generate clock signals N7
			+ - description: slave bit clock N0 provided by external components
			+ - description: slave bit clock N1 provided by external components
			+ - description: slave bit clock N2 provided by external components
			+ - description: slave bit clock N3 provided by external components
			+ - description: slave bit clock N4 provided by external components
			+ - description: slave bit clock N5 provided by external components
			+ - description: slave bit clock N6 provided by external components
			+ - description: slave bit clock N7 provided by external components
			+ - description: slave bit clock N8 provided by external components
			+ - description: slave bit clock N9 provided by external components
			+ - description: slave sample clock N0 provided by external components
			+ - description: slave sample clock N1 provided by external components
			+ - description: slave sample clock N2 provided by external components
			+ - description: slave sample clock N3 provided by external components
			+ - description: slave sample clock N4 provided by external components
			+ - description: slave sample clock N5 provided by external components
			+ - description: slave sample clock N6 provided by external components
			+ - description: slave sample clock N7 provided by external components
			+ - description: slave sample clock N8 provided by external components
			+ - description: slave sample clock N9 provided by external components
			+
			+ clock-names:
			+ minItems: 1
			+ items:
			+ - const: pclk
			+ - const: mst_in0
			+ - const: mst_in1
			+ - const: mst_in2
			+ - const: mst_in3
			+ - const: mst_in4
			+ - const: mst_in5
			+ - const: mst_in6
			+ - const: mst_in7
			+ - const: slv_sclk0
			+ - const: slv_sclk1
			+ - const: slv_sclk2
			+ - const: slv_sclk3
			+ - const: slv_sclk4
			+ - const: slv_sclk5
			+ - const: slv_sclk6
			+ - const: slv_sclk7
			+ - const: slv_sclk8
			+ - const: slv_sclk9
			+ - const: slv_lrclk0
			+ - const: slv_lrclk1
			+ - const: slv_lrclk2
			+ - const: slv_lrclk3
			+ - const: slv_lrclk4
			+ - const: slv_lrclk5
			+ - const: slv_lrclk6
			+ - const: slv_lrclk7
			+ - const: slv_lrclk8
			+ - const: slv_lrclk9
			+
			+ resets:
			+ description: internal reset line
			+
			+required:
			+ - compatible
			+ - '#clock-cells'
			+ - reg
			+ - clocks
			+ - clock-names
			+ - resets
			+
			+allOf:
			+ - if:
			+ properties:
			+ compatible:
			+ contains:
			+ enum:
			+ - amlogic,g12a-audio-clkc
			+ - amlogic,sm1-audio-clkc
			+ then:
			+ required:
			+ - '#reset-cells'
			+ else:
			+ properties:
			+ '#reset-cells': false
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/axg-clkc.h>
			+ #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
			+ apb {
			+ #address-cells = <2>;
			+ #size-cells = <2>;
			+
			+ clkc_audio: clock-controller@0 {
			+ compatible = "amlogic,axg-audio-clkc";
			+ reg = <0x0 0x0 0x0 0xb4>;
			+ #clock-cells = <1>;
			+
			+ clocks = <&clkc CLKID_AUDIO>,
			+ <&clkc CLKID_MPLL0>,
			+ <&clkc CLKID_MPLL1>,
			+ <&clkc CLKID_MPLL2>,
			+ <&clkc CLKID_MPLL3>,
			+ <&clkc CLKID_HIFI_PLL>,
			+ <&clkc CLKID_FCLK_DIV3>,
			+ <&clkc CLKID_FCLK_DIV4>,
			+ <&clkc CLKID_GP0_PLL>,
			+ <&slv_sclk0>,
			+ <&slv_sclk1>,
			+ <&slv_sclk2>,
			+ <&slv_sclk3>,
			+ <&slv_sclk4>,
			+ <&slv_sclk5>,
			+ <&slv_sclk6>,
			+ <&slv_sclk7>,
			+ <&slv_sclk8>,
			+ <&slv_sclk9>,
			+ <&slv_lrclk0>,
			+ <&slv_lrclk1>,
			+ <&slv_lrclk2>,
			+ <&slv_lrclk3>,
			+ <&slv_lrclk4>,
			+ <&slv_lrclk5>,
			+ <&slv_lrclk6>,
			+ <&slv_lrclk7>,
			+ <&slv_lrclk8>,
			+ <&slv_lrclk9>;
			+ clock-names = "pclk",
			+ "mst_in0",
			+ "mst_in1",
			+ "mst_in2",
			+ "mst_in3",
			+ "mst_in4",
			+ "mst_in5",
			+ "mst_in6",
			+ "mst_in7",
			+ "slv_sclk0",
			+ "slv_sclk1",
			+ "slv_sclk2",
			+ "slv_sclk3",
			+ "slv_sclk4",
			+ "slv_sclk5",
			+ "slv_sclk6",
			+ "slv_sclk7",
			+ "slv_sclk8",
			+ "slv_sclk9",
			+ "slv_lrclk0",
			+ "slv_lrclk1",
			+ "slv_lrclk2",
			+ "slv_lrclk3",
			+ "slv_lrclk4",
			+ "slv_lrclk5",
			+ "slv_lrclk6",
			+ "slv_lrclk7",
			+ "slv_lrclk8",
			+ "slv_lrclk9";
			+ resets = <&reset RESET_AUDIO>;
			+ };
			+ };

sys/contrib/device-tree/Bindings/clock/amlogic,c3-peripherals-clkc.yaml
@@ -0,0 +1,120 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/amlogic,c3-peripherals-clkc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Amlogic C3 series Peripheral Clock Controller
			+
			+maintainers:
			+ - Neil Armstrong <neil.armstrong@linaro.org>
			+ - Jerome Brunet <jbrunet@baylibre.com>
			+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
			+ - Chuan Liu <chuan.liu@amlogic.com>
			+
			+properties:
			+ compatible:
			+ const: amlogic,c3-peripherals-clkc
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ minItems: 16
			+ items:
			+ - description: input oscillator (usually at 24MHz)
			+ - description: input oscillators multiplexer
			+ - description: input fix pll
			+ - description: input fclk div 2
			+ - description: input fclk div 2p5
			+ - description: input fclk div 3
			+ - description: input fclk div 4
			+ - description: input fclk div 5
			+ - description: input fclk div 7
			+ - description: input gp0 pll
			+ - description: input gp1 pll
			+ - description: input hifi pll
			+ - description: input sys clk
			+ - description: input axi clk
			+ - description: input sys pll div 16
			+ - description: input cpu clk div 16
			+ - description: input pad clock for rtc clk (optional)
			+
			+ clock-names:
			+ minItems: 16
			+ items:
			+ - const: xtal_24m
			+ - const: oscin
			+ - const: fix
			+ - const: fdiv2
			+ - const: fdiv2p5
			+ - const: fdiv3
			+ - const: fdiv4
			+ - const: fdiv5
			+ - const: fdiv7
			+ - const: gp0
			+ - const: gp1
			+ - const: hifi
			+ - const: sysclk
			+ - const: axiclk
			+ - const: sysplldiv16
			+ - const: cpudiv16
			+ - const: pad_osc
			+
			+ "#clock-cells":
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - clocks
			+ - clock-names
			+ - "#clock-cells"
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ apb {
			+ #address-cells = <2>;
			+ #size-cells = <2>;
			+
			+ clock-controller@0 {
			+ compatible = "amlogic,c3-peripherals-clkc";
			+ reg = <0x0 0x0 0x0 0x49c>;
			+ #clock-cells = <1>;
			+ clocks = <&xtal_24m>,
			+ <&scmi_clk 8>,
			+ <&scmi_clk 12>,
			+ <&clkc_pll 3>,
			+ <&clkc_pll 5>,
			+ <&clkc_pll 7>,
			+ <&clkc_pll 9>,
			+ <&clkc_pll 11>,
			+ <&clkc_pll 13>,
			+ <&clkc_pll 15>,
			+ <&scmi_clk 13>,
			+ <&clkc_pll 17>,
			+ <&scmi_clk 9>,
			+ <&scmi_clk 10>,
			+ <&scmi_clk 14>,
			+ <&scmi_clk 15>;
			+ clock-names = "xtal_24m",
			+ "oscin",
			+ "fix",
			+ "fdiv2",
			+ "fdiv2p5",
			+ "fdiv3",
			+ "fdiv4",
			+ "fdiv5",
			+ "fdiv7",
			+ "gp0",
			+ "gp1",
			+ "hifi",
			+ "sysclk",
			+ "axiclk",
			+ "sysplldiv16",
			+ "cpudiv16";
			+ };
			+ };

sys/contrib/device-tree/Bindings/clock/amlogic,c3-pll-clkc.yaml
@@ -0,0 +1,62 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Amlogic C3 series PLL Clock Controller
			+
			+maintainers:
			+ - Neil Armstrong <neil.armstrong@linaro.org>
			+ - Jerome Brunet <jbrunet@baylibre.com>
			+ - Chuan Liu <chuan.liu@amlogic.com>
			+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
			+
			+properties:
			+ compatible:
			+ const: amlogic,c3-pll-clkc
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ items:
			+ - description: input top pll
			+ - description: input mclk pll
			+ - description: input fix pll
			+
			+ clock-names:
			+ items:
			+ - const: top
			+ - const: mclk
			+ - const: fix
			+
			+ "#clock-cells":
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - clocks
			+ - clock-names
			+ - "#clock-cells"
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ apb {
			+ #address-cells = <2>;
			+ #size-cells = <2>;
			+
			+ clock-controller@8000 {
			+ compatible = "amlogic,c3-pll-clkc";
			+ reg = <0x0 0x8000 0x0 0x1a4>;
			+ clocks = <&scmi_clk 2>,
			+ <&scmi_clk 5>,
			+ <&scmi_clk 12>;
			+ clock-names = "top", "mclk", "fix";
			+ #clock-cells = <1>;
			+ };
			+ };

                - atmel,sama5d3-pmc
                - atmel,sama5d4-pmc
                - microchip,sam9x60-pmc
++              - microchip,sam9x7-pmc
                - microchip,sama7g5-pmc
            - const: syscon
            contains:
              enum:
                - microchip,sam9x60-pmc
++              - microchip,sam9x7-pmc
                - microchip,sama7g5-pmc
      then:
        properties:

            - atmel,sama5d4-sckc
            - microchip,sam9x60-sckc
        - items:
--          - const: microchip,sama7g5-sckc
++          - enum:
++              - microchip,sam9x7-sckc
++              - microchip,sama7g5-sckc
            - const: microchip,sam9x60-sckc
    reg:

sys/contrib/device-tree/Bindings/clock/baikal,bt1-ccu-div.yaml
@@ -134,9 +134,13 @@ properties:
	"#reset-cells":	"#reset-cells":
	const: 1	const: 1

	- clocks: ~~true~~	+ clocks:
		+ minItems: 3
		+ maxItems: 4

	- clock-names: ~~true~~	+ clock-names:
		+ minItems: 3
		+ maxItems: 4

	additionalProperties: false	additionalProperties: false

      minItems: 1
      maxItems: 19
--  clocks: true
++  clocks:
--  assigned-clocks: true
++    minItems: 1
--  assigned-clock-parents: true
++    maxItems: 19
  additionalProperties: false

sys/contrib/device-tree/Bindings/clock/fixed-clock.yaml
@@ -11,6 +11,15 @@ maintainers:
	- Stephen Boyd <sboyd@kernel.org>	- Stephen Boyd <sboyd@kernel.org>

	properties:	properties:
		+ $nodename:
		+ anyOf:
		+ - description:
		+ Preferred name is 'clock-<freq>' with <freq> being the output
		+ frequency as defined in the 'clock-frequency' property.
		+ pattern: "^clock-([0-9]+\|[a-z0-9-]+)$"
		+ - description: Any name allowed
		+ deprecated: true
		+
	compatible:	compatible:
	const: fixed-clock	const: fixed-clock

sys/contrib/device-tree/Bindings/clock/fixed-factor-clock.yaml
@@ -11,6 +11,15 @@ maintainers:
	- Stephen Boyd <sboyd@kernel.org>	- Stephen Boyd <sboyd@kernel.org>

	properties:	properties:
		+ $nodename:
		+ anyOf:
		+ - description:
		+ If the frequency is fixed, the preferred name is 'clock-<freq>' with
		+ <freq> being the output frequency.
		+ pattern: "^clock-([0-9]+\|[0-9a-z-]+)$"
		+ - description: Any name allowed
		+ deprecated: true
		+
	compatible:	compatible:
	enum:	enum:
	- fixed-factor-clock	- fixed-factor-clock

sys/contrib/device-tree/Bindings/clock/fsl,qoriq-clock-legacy.yaml
@@ -0,0 +1,84 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Legacy Clock Block on Freescale QorIQ Platforms
			+
			+maintainers:
			+ - Frank Li <Frank.Li@nxp.com>
			+
			+description: \|
			+ These nodes are deprecated. Kernels should continue to support
			+ device trees with these nodes, but new device trees should not use them.
			+
			+ Most of the bindings are from the common clock binding[1].
			+ [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
			+
			+properties:
			+ compatible:
			+ enum:
			+ - fsl,qoriq-core-pll-1.0
			+ - fsl,qoriq-core-pll-2.0
			+ - fsl,qoriq-core-mux-1.0
			+ - fsl,qoriq-core-mux-2.0
			+ - fsl,qoriq-sysclk-1.0
			+ - fsl,qoriq-sysclk-2.0
			+ - fsl,qoriq-platform-pll-1.0
			+ - fsl,qoriq-platform-pll-2.0
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ minItems: 1
			+ maxItems: 4
			+
			+ clock-names:
			+ minItems: 1
			+ maxItems: 4
			+
			+ clock-output-names:
			+ minItems: 1
			+ maxItems: 8
			+
			+ '#clock-cells':
			+ minimum: 0
			+ maximum: 1
			+
			+required:
			+ - compatible
			+ - '#clock-cells'
			+
			+additionalProperties: false
			+
			+allOf:
			+ - if:
			+ properties:
			+ compatible:
			+ contains:
			+ enum:
			+ - fsl,qoriq-sysclk-1.0
			+ - fsl,qoriq-sysclk-2.0
			+ then:
			+ properties:
			+ '#clock-cells':
			+ const: 0
			+
			+ - if:
			+ properties:
			+ compatible:
			+ contains:
			+ enum:
			+ - fsl,qoriq-core-pll-1.0
			+ - fsl,qoriq-core-pll-2.0
			+ then:
			+ properties:
			+ '#clock-cells':
			+ const: 1
			+ description: \|
			+ * 0 - equal to the PLL frequency
			+ * 1 - equal to the PLL frequency divided by 2
			+ * 2 - equal to the PLL frequency divided by 4
			+

sys/contrib/device-tree/Bindings/clock/fsl,qoriq-clock.yaml
@@ -0,0 +1,207 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Clock Block on Freescale QorIQ Platforms
			+
			+maintainers:
			+ - Frank Li <Frank.Li@nxp.com>
			+
			+description: \|
			+ Freescale QorIQ chips take primary clocking input from the external
			+ SYSCLK signal. The SYSCLK input (frequency) is multiplied using
			+ multiple phase locked loops (PLL) to create a variety of frequencies
			+ which can then be passed to a variety of internal logic, including
			+ cores and peripheral IP blocks.
			+ Please refer to the Reference Manual for details.
			+
			+ All references to "1.0" and "2.0" refer to the QorIQ chassis version to
			+ which the chip complies.
			+
			+ Chassis Version Example Chips
			+ --------------- -------------
			+ 1.0 p4080, p5020, p5040
			+ 2.0 t4240
			+
			+ Clock Provider
			+
			+ The clockgen node should act as a clock provider, though in older device
			+ trees the children of the clockgen node are the clock providers.
			+
			+properties:
			+ compatible:
			+ oneOf:
			+ - items:
			+ - enum:
			+ - fsl,p2041-clockgen
			+ - fsl,p3041-clockgen
			+ - fsl,p4080-clockgen
			+ - fsl,p5020-clockgen
			+ - fsl,p5040-clockgen
			+ - const: fsl,qoriq-clockgen-1.0
			+ - items:
			+ - enum:
			+ - fsl,t1023-clockgen
			+ - fsl,t1024-clockgen
			+ - fsl,t1040-clockgen
			+ - fsl,t1042-clockgen
			+ - fsl,t2080-clockgen
			+ - fsl,t2081-clockgen
			+ - fsl,t4240-clockgen
			+ - const: fsl,qoriq-clockgen-2.0
			+ - items:
			+ - enum:
			+ - fsl,b4420-clockgen
			+ - fsl,b4860-clockgen
			+ - const: fsl,b4-clockgen
			+ - items:
			+ - enum:
			+ - fsl,ls1012a-clockgen
			+ - fsl,ls1021a-clockgen
			+ - fsl,ls1028a-clockgen
			+ - fsl,ls1043a-clockgen
			+ - fsl,ls1046a-clockgen
			+ - fsl,ls1088a-clockgen
			+ - fsl,ls2080a-clockgen
			+ - fsl,lx2160a-clockgen
			+
			+ reg:
			+ maxItems: 1
			+
			+ ranges: true
			+
			+ '#address-cells':
			+ const: 1
			+
			+ '#size-cells':
			+ const: 1
			+
			+ '#clock-cells':
			+ const: 2
			+ description: \|
			+ The first cell of the clock specifier is the clock type, and the
			+ second cell is the clock index for the specified type.
			+
			+ Type# Name Index Cell
			+ 0 sysclk must be 0
			+ 1 cmux index (n in CLKCnCSR)
			+ 2 hwaccel index (n in CLKCGnHWACSR)
			+ 3 fman 0 for fm1, 1 for fm2
			+ 4 platform pll n=pll/(n+1). For example, when n=1,
			+ that means output_freq=PLL_freq/2.
			+ 5 coreclk must be 0
			+
			+ clock-frequency:
			+ description: Input system clock frequency (SYSCLK)
			+
			+ clocks:
			+ items:
			+ - description:
			+ sysclk may be provided as an input clock. Either clock-frequency
			+ or clocks must be provided.
			+ - description:
			+ A second input clock, called "coreclk", may be provided if
			+ core PLLs are based on a different input clock from the
			+ platform PLL.
			+ minItems: 1
			+
			+ clock-names:
			+ items:
			+ - const: sysclk
			+ - const: coreclk
			+
			+patternProperties:
			+ '^mux[0-9]@[a-f0-9]+$':
			+ deprecated: true
			+ $ref: fsl,qoriq-clock-legacy.yaml
			+
			+ '^sysclk(-[a-z0-9]+)?$':
			+ deprecated: true
			+ $ref: fsl,qoriq-clock-legacy.yaml
			+
			+ '^pll[0-9]@[a-f0-9]+$':
			+ deprecated: true
			+ $ref: fsl,qoriq-clock-legacy.yaml
			+
			+ '^platform\-pll@[a-f0-9]+$':
			+ deprecated: true
			+ $ref: fsl,qoriq-clock-legacy.yaml
			+
			+required:
			+ - compatible
			+ - reg
			+ - '#clock-cells'
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ /* clock provider example */
			+ global-utilities@e1000 {
			+ compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
			+ reg = <0xe1000 0x1000>;
			+ clock-frequency = <133333333>;
			+ #clock-cells = <2>;
			+ };
			+
			+ - \|
			+ /* Legacy example */
			+ global-utilities@e1000 {
			+ compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
			+ reg = <0xe1000 0x1000>;
			+ ranges = <0x0 0xe1000 0x1000>;
			+ clock-frequency = <133333333>;
			+ #address-cells = <1>;
			+ #size-cells = <1>;
			+ #clock-cells = <2>;
			+
			+ sysclk: sysclk {
			+ compatible = "fsl,qoriq-sysclk-1.0";
			+ clock-output-names = "sysclk";
			+ #clock-cells = <0>;
			+ };
			+
			+ pll0: pll0@800 {
			+ compatible = "fsl,qoriq-core-pll-1.0";
			+ reg = <0x800 0x4>;
			+ #clock-cells = <1>;
			+ clocks = <&sysclk>;
			+ clock-output-names = "pll0", "pll0-div2";
			+ };
			+
			+ pll1: pll1@820 {
			+ compatible = "fsl,qoriq-core-pll-1.0";
			+ reg = <0x820 0x4>;
			+ #clock-cells = <1>;
			+ clocks = <&sysclk>;
			+ clock-output-names = "pll1", "pll1-div2";
			+ };
			+
			+ mux0: mux0@0 {
			+ compatible = "fsl,qoriq-core-mux-1.0";
			+ reg = <0x0 0x4>;
			+ #clock-cells = <0>;
			+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
			+ clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
			+ clock-output-names = "cmux0";
			+ };
			+
			+ mux1: mux1@20 {
			+ compatible = "fsl,qoriq-core-mux-1.0";
			+ reg = <0x20 0x4>;
			+ #clock-cells = <0>;
			+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
			+ clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
			+ clock-output-names = "cmux1";
			+ };
			+
			+ platform-pll@c00 {
			+ #clock-cells = <1>;
			+ reg = <0xc00 0x4>;
			+ compatible = "fsl,qoriq-platform-pll-1.0";
			+ clocks = <&sysclk>;
			+ clock-output-names = "platform-pll", "platform-pll-div2";
			+ };
			+ };

sys/contrib/device-tree/Bindings/clock/google,gs101-clock.yaml
@@ -30,14 +30,18 @@ properties:
	- google,gs101-cmu-top	- google,gs101-cmu-top
	- google,gs101-cmu-apm	- google,gs101-cmu-apm
	- google,gs101-cmu-misc	- google,gs101-cmu-misc
		+ - google,gs101-cmu-hsi0
		+ - google,gs101-cmu-hsi2
		+ - google,gs101-cmu-peric0
		+ - google,gs101-cmu-peric1

	clocks:	clocks:
	minItems: 1	minItems: 1
	- maxItems: 2	+ maxItems: 5

	clock-names:	clock-names:
	minItems: 1	minItems: 1
	- maxItems: 2	+ maxItems: 5

	"#clock-cells":	"#clock-cells":
	const: 1	const: 1
@@ -70,6 +74,55 @@ allOf:
	items:	items:
	- const: oscclk	- const: oscclk

		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ const: google,gs101-cmu-hsi0
		+
		+ then:
		+ properties:
		+ clocks:
		+ items:
		+ - description: External reference clock (24.576 MHz)
		+ - description: HSI0 bus clock (from CMU_TOP)
		+ - description: DPGTC (from CMU_TOP)
		+ - description: USB DRD controller clock (from CMU_TOP)
		+ - description: USB Display Port debug clock (from CMU_TOP)
		+
		+ clock-names:
		+ items:
		+ - const: oscclk
		+ - const: bus
		+ - const: dpgtc
		+ - const: usb31drd
		+ - const: usbdpdbg
		+
		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ enum:
		+ - google,gs101-cmu-hsi2
		+
		+ then:
		+ properties:
		+ clocks:
		+ items:
		+ - description: External reference clock (24.576 MHz)
		+ - description: High Speed Interface bus clock (from CMU_TOP)
		+ - description: High Speed Interface pcie clock (from CMU_TOP)
		+ - description: High Speed Interface ufs clock (from CMU_TOP)
		+ - description: High Speed Interface mmc clock (from CMU_TOP)
		+
		+ clock-names:
		+ items:
		+ - const: oscclk
		+ - const: bus
		+ - const: pcie
		+ - const: ufs
		+ - const: mmc
		+
	- if:	- if:
	properties:	properties:
	compatible:	compatible:
@@ -88,6 +141,28 @@ allOf:
	- const: bus	- const: bus
	- const: sss	- const: sss

		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ enum:
		+ - google,gs101-cmu-peric0
		+ - google,gs101-cmu-peric1
		+
		+ then:
		+ properties:
		+ clocks:
		+ items:
		+ - description: External reference clock (24.576 MHz)
		+ - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
		+ - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
		+
		+ clock-names:
		+ items:
		+ - const: oscclk
		+ - const: bus
		+ - const: ip
		+
	additionalProperties: false	additionalProperties: false

	examples:	examples:

    - compatible
    - reg
    - '#clock-cells'
--  - idt,shutdown
--  - idt,output-enable-active
  allOf:
    - if:

  title: Freescale i.MX6 Quad Clock Controller
  maintainers:
--  - Anson Huang <Anson.Huang@nxp.com>
++  - Abel Vesa <abelvesa@kernel.org>
++  - Peng Fan <peng.fan@nxp.com>
  properties:
    compatible:

  title: Freescale i.MX6 SoloLite Clock Controller
  maintainers:
--  - Anson Huang <Anson.Huang@nxp.com>
++  - Abel Vesa <abelvesa@kernel.org>
++  - Peng Fan <peng.fan@nxp.com>
  properties:
    compatible:

  title: Freescale i.MX6 SLL Clock Controller
  maintainers:
--  - Anson Huang <Anson.Huang@nxp.com>
++  - Abel Vesa <abelvesa@kernel.org>
++  - Peng Fan <peng.fan@nxp.com>
  properties:
    compatible:

  title: Freescale i.MX6 SoloX Clock Controller
  maintainers:
--  - Anson Huang <Anson.Huang@nxp.com>
++  - Abel Vesa <abelvesa@kernel.org>
++  - Peng Fan <peng.fan@nxp.com>
  properties:
    compatible:

  title: Freescale i.MX6 UltraLite Clock Controller
  maintainers:
--  - Anson Huang <Anson.Huang@nxp.com>
++  - Abel Vesa <abelvesa@kernel.org>
++  - Peng Fan <peng.fan@nxp.com>
  properties:
    compatible:

  maintainers:
    - Frank Li <Frank.Li@nxp.com>
--  - Anson Huang <Anson.Huang@nxp.com>
  description: |
    The clock consumer should specify the desired clock by having the clock

  title: NXP i.MX8M Family Clock Control Module
  maintainers:
--  - Anson Huang <Anson.Huang@nxp.com>
++  - Abel Vesa <abelvesa@kernel.org>
++  - Peng Fan <peng.fan@nxp.com>
  description: |
    NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock

        ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h
        for the full list of i.MX8MP IMX8MP_CLK_AUDIOMIX_ clock IDs.
++  '#reset-cells':
++    const: 1
++
  required:
    - compatible
    - reg

sys/contrib/device-tree/Bindings/clock/keystone-gate.txt
@@ -1,5 +1,3 @@
	-Status: Unstable - ABI compatibility may be broken in the future
	-
	Binding for Keystone gate control driver which uses PSC controller IP.	Binding for Keystone gate control driver which uses PSC controller IP.

	This binding uses the common clock binding[1].	This binding uses the common clock binding[1].

sys/contrib/device-tree/Bindings/clock/keystone-pll.txt
@@ -1,5 +1,3 @@
	-Status: Unstable - ABI compatibility may be broken in the future
	-
	Binding for keystone PLLs. The main PLL IP typically has a multiplier,	Binding for keystone PLLs. The main PLL IP typically has a multiplier,
	a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL	a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
	and PAPLL are controlled by the memory mapped register where as the Main	and PAPLL are controlled by the memory mapped register where as the Main

  properties:
    compatible:
      enum:
--      - loongson,ls2k-clk
++      - loongson,ls2k0500-clk
++      - loongson,ls2k-clk  # This is for Loongson-2K1000
++      - loongson,ls2k2000-clk
    reg:
      maxItems: 1

                - mediatek,mt2701-apmixedsys
                - mediatek,mt2712-apmixedsys
                - mediatek,mt6765-apmixedsys
--              - mediatek,mt6779-apmixedsys
++              - mediatek,mt6779-apmixed
                - mediatek,mt6795-apmixedsys
                - mediatek,mt7629-apmixedsys
                - mediatek,mt8167-apmixedsys

sys/contrib/device-tree/Bindings/clock/mediatek,infracfg.yaml
@@ -0,0 +1,85 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/mediatek,infracfg.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MediaTek Infrastructure System Configuration Controller
			+
			+maintainers:
			+ - Matthias Brugger <matthias.bgg@gmail.com>
			+
			+description:
			+ The Mediatek infracfg controller provides various clocks and reset outputs
			+ to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
			+ and reset values in <dt-bindings/reset/mt*-reset.h> and
			+ <dt-bindings/reset/mt*-resets.h>.
			+
			+properties:
			+ compatible:
			+ oneOf:
			+ - items:
			+ - enum:
			+ - mediatek,mt2701-infracfg
			+ - mediatek,mt2712-infracfg
			+ - mediatek,mt6765-infracfg
			+ - mediatek,mt6795-infracfg
			+ - mediatek,mt6779-infracfg_ao
			+ - mediatek,mt6797-infracfg
			+ - mediatek,mt7622-infracfg
			+ - mediatek,mt7629-infracfg
			+ - mediatek,mt7981-infracfg
			+ - mediatek,mt7986-infracfg
			+ - mediatek,mt7988-infracfg
			+ - mediatek,mt8135-infracfg
			+ - mediatek,mt8167-infracfg
			+ - mediatek,mt8173-infracfg
			+ - mediatek,mt8183-infracfg
			+ - mediatek,mt8516-infracfg
			+ - const: syscon
			+ - items:
			+ - const: mediatek,mt7623-infracfg
			+ - const: mediatek,mt2701-infracfg
			+ - const: syscon
			+
			+ reg:
			+ maxItems: 1
			+
			+ '#clock-cells':
			+ const: 1
			+
			+ '#reset-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - '#clock-cells'
			+
			+if:
			+ properties:
			+ compatible:
			+ contains:
			+ enum:
			+ - mediatek,mt2701-infracfg
			+ - mediatek,mt2712-infracfg
			+ - mediatek,mt6795-infracfg
			+ - mediatek,mt7622-infracfg
			+ - mediatek,mt7986-infracfg
			+ - mediatek,mt8135-infracfg
			+ - mediatek,mt8173-infracfg
			+ - mediatek,mt8183-infracfg
			+then:
			+ required:
			+ - '#reset-cells'
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ infracfg: clock-controller@10001000 {
			+ compatible = "mediatek,mt8173-infracfg", "syscon";
			+ reg = <0x10001000 0x1000>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ };

sys/contrib/device-tree/Bindings/clock/mediatek,mt2701-hifsys.yaml
@@ -0,0 +1,50 @@
			+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/mediatek,mt2701-hifsys.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MediaTek HIFSYS clock and reset controller
			+
			+description:
			+ The MediaTek HIFSYS controller provides various clocks and reset outputs to
			+ the system.
			+
			+maintainers:
			+ - Matthias Brugger <matthias.bgg@gmail.com>
			+
			+properties:
			+ compatible:
			+ oneOf:
			+ - enum:
			+ - mediatek,mt2701-hifsys
			+ - mediatek,mt7622-hifsys
			+ - items:
			+ - enum:
			+ - mediatek,mt7623-hifsys
			+ - const: mediatek,mt2701-hifsys
			+
			+ reg:
			+ maxItems: 1
			+
			+ "#clock-cells":
			+ const: 1
			+ description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
			+
			+ "#reset-cells":
			+ const: 1
			+
			+required:
			+ - reg
			+ - "#clock-cells"
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ clock-controller@1a000000 {
			+ compatible = "mediatek,mt2701-hifsys";
			+ reg = <0x1a000000 0x1000>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ };

sys/contrib/device-tree/Bindings/clock/mediatek,mt7622-pciesys.yaml
@@ -0,0 +1,47 @@
			+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/mediatek,mt7622-pciesys.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MediaTek PCIESYS clock and reset controller
			+
			+description:
			+ The MediaTek PCIESYS controller provides various clocks to the system.
			+
			+maintainers:
			+ - Matthias Brugger <matthias.bgg@gmail.com>
			+
			+properties:
			+ compatible:
			+ oneOf:
			+ - items:
			+ - const: mediatek,mt7622-pciesys
			+ - const: syscon
			+ - const: mediatek,mt7629-pciesys
			+
			+ reg:
			+ maxItems: 1
			+
			+ "#clock-cells":
			+ const: 1
			+ description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
			+
			+ "#reset-cells":
			+ const: 1
			+
			+required:
			+ - reg
			+ - "#clock-cells"
			+ - "#reset-cells"
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ clock-controller@1a100800 {
			+ compatible = "mediatek,mt7622-pciesys", "syscon";
			+ reg = <0x1a100800 0x1000>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ };

sys/contrib/device-tree/Bindings/clock/mediatek,mt7622-ssusbsys.yaml
@@ -0,0 +1,45 @@
			+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/mediatek,mt7622-ssusbsys.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MediaTek SSUSBSYS clock and reset controller
			+
			+description:
			+ The MediaTek SSUSBSYS controller provides various clocks to the system.
			+
			+maintainers:
			+ - Matthias Brugger <matthias.bgg@gmail.com>
			+
			+properties:
			+ compatible:
			+ enum:
			+ - mediatek,mt7622-ssusbsys
			+ - mediatek,mt7629-ssusbsys
			+
			+ reg:
			+ maxItems: 1
			+
			+ "#clock-cells":
			+ const: 1
			+ description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
			+
			+ "#reset-cells":
			+ const: 1
			+
			+required:
			+ - reg
			+ - "#clock-cells"
			+ - "#reset-cells"
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ clock-controller@1a000000 {
			+ compatible = "mediatek,mt7622-ssusbsys";
			+ reg = <0x1a000000 0x1000>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ };

sys/contrib/device-tree/Bindings/clock/mediatek,mt8186-clock.yaml
@@ -0,0 +1,56 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/mediatek,mt8186-clock.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MediaTek Functional Clock Controller for MT8186
			+
			+maintainers:
			+ - Chun-Jie Chen <chun-jie.chen@mediatek.com>
			+
			+description: \|
			+ The clock architecture in MediaTek like below
			+ PLLs -->
			+ dividers -->
			+ muxes
			+ -->
			+ clock gate
			+
			+ The devices provide clock gate control in different IP blocks.
			+
			+properties:
			+ compatible:
			+ items:
			+ - enum:
			+ - mediatek,mt8186-imp_iic_wrap
			+ - mediatek,mt8186-mfgsys
			+ - mediatek,mt8186-wpesys
			+ - mediatek,mt8186-imgsys1
			+ - mediatek,mt8186-imgsys2
			+ - mediatek,mt8186-vdecsys
			+ - mediatek,mt8186-vencsys
			+ - mediatek,mt8186-camsys
			+ - mediatek,mt8186-camsys_rawa
			+ - mediatek,mt8186-camsys_rawb
			+ - mediatek,mt8186-mdpsys
			+ - mediatek,mt8186-ipesys
			+ reg:
			+ maxItems: 1
			+
			+ '#clock-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ imp_iic_wrap: clock-controller@11017000 {
			+ compatible = "mediatek,mt8186-imp_iic_wrap";
			+ reg = <0x11017000 0x1000>;
			+ #clock-cells = <1>;
			+ };

sys/contrib/device-tree/Bindings/clock/mediatek,mt8186-sys-clock.yaml
@@ -0,0 +1,57 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MediaTek System Clock Controller for MT8186
			+
			+maintainers:
			+ - Chun-Jie Chen <chun-jie.chen@mediatek.com>
			+
			+description: \|
			+ The clock architecture in MediaTek like below
			+ PLLs -->
			+ dividers -->
			+ muxes
			+ -->
			+ clock gate
			+
			+ The apmixedsys provides most of PLLs which generated from SoC 26m.
			+ The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
			+ The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
			+ The mcusys provides mux control to select the clock source in AP MCU.
			+ The device nodes also provide the system control capacity for configuration.
			+
			+properties:
			+ compatible:
			+ items:
			+ - enum:
			+ - mediatek,mt8186-mcusys
			+ - mediatek,mt8186-topckgen
			+ - mediatek,mt8186-infracfg_ao
			+ - mediatek,mt8186-apmixedsys
			+ - const: syscon
			+
			+ reg:
			+ maxItems: 1
			+
			+ '#clock-cells':
			+ const: 1
			+
			+ '#reset-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ topckgen: syscon@10000000 {
			+ compatible = "mediatek,mt8186-topckgen", "syscon";
			+ reg = <0x10000000 0x1000>;
			+ #clock-cells = <1>;
			+ };

    '#clock-cells':
      const: 1
++  '#reset-cells':
++    const: 1
++
  required:
    - compatible
    - reg

sys/contrib/device-tree/Bindings/clock/mediatek,mt8192-clock.yaml
@@ -0,0 +1,191 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MediaTek Functional Clock Controller for MT8192
			+
			+maintainers:
			+ - Chun-Jie Chen <chun-jie.chen@mediatek.com>
			+
			+description:
			+ The Mediatek functional clock controller provides various clocks on MT8192.
			+
			+properties:
			+ compatible:
			+ items:
			+ - enum:
			+ - mediatek,mt8192-scp_adsp
			+ - mediatek,mt8192-imp_iic_wrap_c
			+ - mediatek,mt8192-imp_iic_wrap_e
			+ - mediatek,mt8192-imp_iic_wrap_s
			+ - mediatek,mt8192-imp_iic_wrap_ws
			+ - mediatek,mt8192-imp_iic_wrap_w
			+ - mediatek,mt8192-imp_iic_wrap_n
			+ - mediatek,mt8192-msdc_top
			+ - mediatek,mt8192-mfgcfg
			+ - mediatek,mt8192-imgsys
			+ - mediatek,mt8192-imgsys2
			+ - mediatek,mt8192-vdecsys_soc
			+ - mediatek,mt8192-vdecsys
			+ - mediatek,mt8192-vencsys
			+ - mediatek,mt8192-camsys
			+ - mediatek,mt8192-camsys_rawa
			+ - mediatek,mt8192-camsys_rawb
			+ - mediatek,mt8192-camsys_rawc
			+ - mediatek,mt8192-ipesys
			+ - mediatek,mt8192-mdpsys
			+
			+ reg:
			+ maxItems: 1
			+
			+ '#clock-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ scp_adsp: clock-controller@10720000 {
			+ compatible = "mediatek,mt8192-scp_adsp";
			+ reg = <0x10720000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ imp_iic_wrap_c: clock-controller@11007000 {
			+ compatible = "mediatek,mt8192-imp_iic_wrap_c";
			+ reg = <0x11007000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ imp_iic_wrap_e: clock-controller@11cb1000 {
			+ compatible = "mediatek,mt8192-imp_iic_wrap_e";
			+ reg = <0x11cb1000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ imp_iic_wrap_s: clock-controller@11d03000 {
			+ compatible = "mediatek,mt8192-imp_iic_wrap_s";
			+ reg = <0x11d03000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ imp_iic_wrap_ws: clock-controller@11d23000 {
			+ compatible = "mediatek,mt8192-imp_iic_wrap_ws";
			+ reg = <0x11d23000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ imp_iic_wrap_w: clock-controller@11e01000 {
			+ compatible = "mediatek,mt8192-imp_iic_wrap_w";
			+ reg = <0x11e01000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ imp_iic_wrap_n: clock-controller@11f02000 {
			+ compatible = "mediatek,mt8192-imp_iic_wrap_n";
			+ reg = <0x11f02000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ msdc_top: clock-controller@11f10000 {
			+ compatible = "mediatek,mt8192-msdc_top";
			+ reg = <0x11f10000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ mfgcfg: clock-controller@13fbf000 {
			+ compatible = "mediatek,mt8192-mfgcfg";
			+ reg = <0x13fbf000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ imgsys: clock-controller@15020000 {
			+ compatible = "mediatek,mt8192-imgsys";
			+ reg = <0x15020000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ imgsys2: clock-controller@15820000 {
			+ compatible = "mediatek,mt8192-imgsys2";
			+ reg = <0x15820000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ vdecsys_soc: clock-controller@1600f000 {
			+ compatible = "mediatek,mt8192-vdecsys_soc";
			+ reg = <0x1600f000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ vdecsys: clock-controller@1602f000 {
			+ compatible = "mediatek,mt8192-vdecsys";
			+ reg = <0x1602f000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ vencsys: clock-controller@17000000 {
			+ compatible = "mediatek,mt8192-vencsys";
			+ reg = <0x17000000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ camsys: clock-controller@1a000000 {
			+ compatible = "mediatek,mt8192-camsys";
			+ reg = <0x1a000000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ camsys_rawa: clock-controller@1a04f000 {
			+ compatible = "mediatek,mt8192-camsys_rawa";
			+ reg = <0x1a04f000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ camsys_rawb: clock-controller@1a06f000 {
			+ compatible = "mediatek,mt8192-camsys_rawb";
			+ reg = <0x1a06f000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ camsys_rawc: clock-controller@1a08f000 {
			+ compatible = "mediatek,mt8192-camsys_rawc";
			+ reg = <0x1a08f000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ ipesys: clock-controller@1b000000 {
			+ compatible = "mediatek,mt8192-ipesys";
			+ reg = <0x1b000000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ mdpsys: clock-controller@1f000000 {
			+ compatible = "mediatek,mt8192-mdpsys";
			+ reg = <0x1f000000 0x1000>;
			+ #clock-cells = <1>;
			+ };

sys/contrib/device-tree/Bindings/clock/mediatek,mt8192-sys-clock.yaml
@@ -0,0 +1,68 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/mediatek,mt8192-sys-clock.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MediaTek System Clock Controller for MT8192
			+
			+maintainers:
			+ - Chun-Jie Chen <chun-jie.chen@mediatek.com>
			+
			+description:
			+ The Mediatek system clock controller provides various clocks and system configuration
			+ like reset and bus protection on MT8192.
			+
			+properties:
			+ compatible:
			+ items:
			+ - enum:
			+ - mediatek,mt8192-topckgen
			+ - mediatek,mt8192-infracfg
			+ - mediatek,mt8192-pericfg
			+ - mediatek,mt8192-apmixedsys
			+ - const: syscon
			+
			+ reg:
			+ maxItems: 1
			+
			+ '#clock-cells':
			+ const: 1
			+
			+ '#reset-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ topckgen: syscon@10000000 {
			+ compatible = "mediatek,mt8192-topckgen", "syscon";
			+ reg = <0x10000000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ infracfg: syscon@10001000 {
			+ compatible = "mediatek,mt8192-infracfg", "syscon";
			+ reg = <0x10001000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ pericfg: syscon@10003000 {
			+ compatible = "mediatek,mt8192-pericfg", "syscon";
			+ reg = <0x10003000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ apmixedsys: syscon@1000c000 {
			+ compatible = "mediatek,mt8192-apmixedsys", "syscon";
			+ reg = <0x1000c000 0x1000>;
			+ #clock-cells = <1>;
			+ };

sys/contrib/device-tree/Bindings/clock/mediatek,mt8195-clock.yaml
@@ -0,0 +1,238 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MediaTek Functional Clock Controller for MT8195
			+
			+maintainers:
			+ - Chun-Jie Chen <chun-jie.chen@mediatek.com>
			+
			+description:
			+ The clock architecture in Mediatek like below
			+ PLLs -->
			+ dividers -->
			+ muxes
			+ -->
			+ clock gate
			+
			+ The devices except apusys_pll provide clock gate control in different IP blocks.
			+ The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
			+
			+properties:
			+ compatible:
			+ items:
			+ - enum:
			+ - mediatek,mt8195-scp_adsp
			+ - mediatek,mt8195-imp_iic_wrap_s
			+ - mediatek,mt8195-imp_iic_wrap_w
			+ - mediatek,mt8195-mfgcfg
			+ - mediatek,mt8195-wpesys
			+ - mediatek,mt8195-wpesys_vpp0
			+ - mediatek,mt8195-wpesys_vpp1
			+ - mediatek,mt8195-imgsys
			+ - mediatek,mt8195-imgsys1_dip_top
			+ - mediatek,mt8195-imgsys1_dip_nr
			+ - mediatek,mt8195-imgsys1_wpe
			+ - mediatek,mt8195-ipesys
			+ - mediatek,mt8195-camsys
			+ - mediatek,mt8195-camsys_rawa
			+ - mediatek,mt8195-camsys_yuva
			+ - mediatek,mt8195-camsys_rawb
			+ - mediatek,mt8195-camsys_yuvb
			+ - mediatek,mt8195-camsys_mraw
			+ - mediatek,mt8195-ccusys
			+ - mediatek,mt8195-vdecsys_soc
			+ - mediatek,mt8195-vdecsys
			+ - mediatek,mt8195-vdecsys_core1
			+ - mediatek,mt8195-vencsys
			+ - mediatek,mt8195-vencsys_core1
			+ - mediatek,mt8195-apusys_pll
			+ reg:
			+ maxItems: 1
			+
			+ '#clock-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ scp_adsp: clock-controller@10720000 {
			+ compatible = "mediatek,mt8195-scp_adsp";
			+ reg = <0x10720000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ imp_iic_wrap_s: clock-controller@11d03000 {
			+ compatible = "mediatek,mt8195-imp_iic_wrap_s";
			+ reg = <0x11d03000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ imp_iic_wrap_w: clock-controller@11e05000 {
			+ compatible = "mediatek,mt8195-imp_iic_wrap_w";
			+ reg = <0x11e05000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ mfgcfg: clock-controller@13fbf000 {
			+ compatible = "mediatek,mt8195-mfgcfg";
			+ reg = <0x13fbf000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ wpesys: clock-controller@14e00000 {
			+ compatible = "mediatek,mt8195-wpesys";
			+ reg = <0x14e00000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ wpesys_vpp0: clock-controller@14e02000 {
			+ compatible = "mediatek,mt8195-wpesys_vpp0";
			+ reg = <0x14e02000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ wpesys_vpp1: clock-controller@14e03000 {
			+ compatible = "mediatek,mt8195-wpesys_vpp1";
			+ reg = <0x14e03000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ imgsys: clock-controller@15000000 {
			+ compatible = "mediatek,mt8195-imgsys";
			+ reg = <0x15000000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ imgsys1_dip_top: clock-controller@15110000 {
			+ compatible = "mediatek,mt8195-imgsys1_dip_top";
			+ reg = <0x15110000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ imgsys1_dip_nr: clock-controller@15130000 {
			+ compatible = "mediatek,mt8195-imgsys1_dip_nr";
			+ reg = <0x15130000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ imgsys1_wpe: clock-controller@15220000 {
			+ compatible = "mediatek,mt8195-imgsys1_wpe";
			+ reg = <0x15220000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ ipesys: clock-controller@15330000 {
			+ compatible = "mediatek,mt8195-ipesys";
			+ reg = <0x15330000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ camsys: clock-controller@16000000 {
			+ compatible = "mediatek,mt8195-camsys";
			+ reg = <0x16000000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ camsys_rawa: clock-controller@1604f000 {
			+ compatible = "mediatek,mt8195-camsys_rawa";
			+ reg = <0x1604f000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ camsys_yuva: clock-controller@1606f000 {
			+ compatible = "mediatek,mt8195-camsys_yuva";
			+ reg = <0x1606f000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ camsys_rawb: clock-controller@1608f000 {
			+ compatible = "mediatek,mt8195-camsys_rawb";
			+ reg = <0x1608f000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ camsys_yuvb: clock-controller@160af000 {
			+ compatible = "mediatek,mt8195-camsys_yuvb";
			+ reg = <0x160af000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ camsys_mraw: clock-controller@16140000 {
			+ compatible = "mediatek,mt8195-camsys_mraw";
			+ reg = <0x16140000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ ccusys: clock-controller@17200000 {
			+ compatible = "mediatek,mt8195-ccusys";
			+ reg = <0x17200000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ vdecsys_soc: clock-controller@1800f000 {
			+ compatible = "mediatek,mt8195-vdecsys_soc";
			+ reg = <0x1800f000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ vdecsys: clock-controller@1802f000 {
			+ compatible = "mediatek,mt8195-vdecsys";
			+ reg = <0x1802f000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ vdecsys_core1: clock-controller@1803f000 {
			+ compatible = "mediatek,mt8195-vdecsys_core1";
			+ reg = <0x1803f000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ vencsys: clock-controller@1a000000 {
			+ compatible = "mediatek,mt8195-vencsys";
			+ reg = <0x1a000000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ vencsys_core1: clock-controller@1b000000 {
			+ compatible = "mediatek,mt8195-vencsys_core1";
			+ reg = <0x1b000000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ apusys_pll: clock-controller@190f3000 {
			+ compatible = "mediatek,mt8195-apusys_pll";
			+ reg = <0x190f3000 0x1000>;
			+ #clock-cells = <1>;
			+ };

sys/contrib/device-tree/Bindings/clock/mediatek,mt8195-sys-clock.yaml
@@ -0,0 +1,76 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/mediatek,mt8195-sys-clock.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MediaTek System Clock Controller for MT8195
			+
			+maintainers:
			+ - Chun-Jie Chen <chun-jie.chen@mediatek.com>
			+
			+description:
			+ The clock architecture in Mediatek like below
			+ PLLs -->
			+ dividers -->
			+ muxes
			+ -->
			+ clock gate
			+
			+ The apmixedsys provides most of PLLs which generated from SoC 26m.
			+ The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
			+ The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
			+
			+properties:
			+ compatible:
			+ items:
			+ - enum:
			+ - mediatek,mt8195-topckgen
			+ - mediatek,mt8195-infracfg_ao
			+ - mediatek,mt8195-apmixedsys
			+ - mediatek,mt8195-pericfg_ao
			+ - const: syscon
			+
			+ reg:
			+ maxItems: 1
			+
			+ '#clock-cells':
			+ const: 1
			+
			+ '#reset-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ topckgen: syscon@10000000 {
			+ compatible = "mediatek,mt8195-topckgen", "syscon";
			+ reg = <0x10000000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ infracfg_ao: syscon@10001000 {
			+ compatible = "mediatek,mt8195-infracfg_ao", "syscon";
			+ reg = <0x10001000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ apmixedsys: syscon@1000c000 {
			+ compatible = "mediatek,mt8195-apmixedsys", "syscon";
			+ reg = <0x1000c000 0x1000>;
			+ #clock-cells = <1>;
			+ };
			+
			+ - \|
			+ pericfg_ao: syscon@11003000 {
			+ compatible = "mediatek,mt8195-pericfg_ao", "syscon";
			+ reg = <0x11003000 0x1000>;
			+ #clock-cells = <1>;
			+ };

sys/contrib/device-tree/Bindings/clock/mediatek,pericfg.yaml
@@ -0,0 +1,71 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/mediatek,pericfg.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MediaTek Peripheral Configuration Controller
			+
			+maintainers:
			+ - Bartosz Golaszewski <bgolaszewski@baylibre.com>
			+
			+description:
			+ The Mediatek pericfg controller provides various clocks and reset outputs
			+ to the system.
			+
			+properties:
			+ compatible:
			+ oneOf:
			+ - items:
			+ - enum:
			+ - mediatek,mt2701-pericfg
			+ - mediatek,mt2712-pericfg
			+ - mediatek,mt6765-pericfg
			+ - mediatek,mt6795-pericfg
			+ - mediatek,mt7622-pericfg
			+ - mediatek,mt7629-pericfg
			+ - mediatek,mt8135-pericfg
			+ - mediatek,mt8173-pericfg
			+ - mediatek,mt8183-pericfg
			+ - mediatek,mt8186-pericfg
			+ - mediatek,mt8188-pericfg
			+ - mediatek,mt8195-pericfg
			+ - mediatek,mt8516-pericfg
			+ - const: syscon
			+ - items:
			+ # Special case for mt7623 for backward compatibility
			+ - const: mediatek,mt7623-pericfg
			+ - const: mediatek,mt2701-pericfg
			+ - const: syscon
			+
			+ reg:
			+ maxItems: 1
			+
			+ '#clock-cells':
			+ const: 1
			+
			+ '#reset-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ pericfg@10003000 {
			+ compatible = "mediatek,mt8173-pericfg", "syscon";
			+ reg = <0x10003000 0x1000>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ };
			+
			+ - \|
			+ pericfg@10003000 {
			+ compatible = "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon";
			+ reg = <0x10003000 0x1000>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ };

sys/contrib/device-tree/Bindings/clock/mediatek,syscon.yaml
@@ -0,0 +1,93 @@
			+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/mediatek,syscon.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: MediaTek Clock controller syscon's
			+
			+maintainers:
			+ - Matthias Brugger <matthias.bgg@gmail.com>
			+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
			+
			+description:
			+ The MediaTek clock controller syscon's provide various clocks to the system.
			+
			+properties:
			+ compatible:
			+ oneOf:
			+ - items:
			+ - enum:
			+ - mediatek,mt2701-bdpsys
			+ - mediatek,mt2701-imgsys
			+ - mediatek,mt2701-vdecsys
			+ - mediatek,mt2712-bdpsys
			+ - mediatek,mt2712-imgsys
			+ - mediatek,mt2712-jpgdecsys
			+ - mediatek,mt2712-mcucfg
			+ - mediatek,mt2712-mfgcfg
			+ - mediatek,mt2712-vdecsys
			+ - mediatek,mt2712-vencsys
			+ - mediatek,mt6765-camsys
			+ - mediatek,mt6765-imgsys
			+ - mediatek,mt6765-mipi0a
			+ - mediatek,mt6765-vcodecsys
			+ - mediatek,mt6779-camsys
			+ - mediatek,mt6779-imgsys
			+ - mediatek,mt6779-ipesys
			+ - mediatek,mt6779-mfgcfg
			+ - mediatek,mt6779-vdecsys
			+ - mediatek,mt6779-vencsys
			+ - mediatek,mt6797-imgsys
			+ - mediatek,mt6797-vdecsys
			+ - mediatek,mt6797-vencsys
			+ - mediatek,mt8167-imgsys
			+ - mediatek,mt8167-mfgcfg
			+ - mediatek,mt8167-vdecsys
			+ - mediatek,mt8173-imgsys
			+ - mediatek,mt8173-vdecsys
			+ - mediatek,mt8173-vencltsys
			+ - mediatek,mt8173-vencsys
			+ - mediatek,mt8183-camsys
			+ - mediatek,mt8183-imgsys
			+ - mediatek,mt8183-ipu_conn
			+ - mediatek,mt8183-ipu_adl
			+ - mediatek,mt8183-ipu_core0
			+ - mediatek,mt8183-ipu_core1
			+ - mediatek,mt8183-mcucfg
			+ - mediatek,mt8183-mfgcfg
			+ - mediatek,mt8183-vdecsys
			+ - mediatek,mt8183-vencsys
			+ - const: syscon
			+ - items:
			+ - const: mediatek,mt7623-bdpsys
			+ - const: mediatek,mt2701-bdpsys
			+ - const: syscon
			+ - items:
			+ - const: mediatek,mt7623-imgsys
			+ - const: mediatek,mt2701-imgsys
			+ - const: syscon
			+ - items:
			+ - const: mediatek,mt7623-vdecsys
			+ - const: mediatek,mt2701-vdecsys
			+ - const: syscon
			+
			+ reg:
			+ maxItems: 1
			+
			+ '#clock-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - '#clock-cells'
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ clock-controller@11220000 {
			+ compatible = "mediatek,mt2701-bdpsys", "syscon";
			+ reg = <0x11220000 0x2000>;
			+ #clock-cells = <1>;
			+ };

sys/contrib/device-tree/Bindings/clock/milbeaut-clock.yaml
@@ -40,38 +40,11 @@ required:
	additionalProperties: false	additionalProperties: false

	examples:	examples:
	- # Clock controller node:
	- \|	- \|
	- ~~m10v~~-~~clk-ctrl@1d021000~~ {	+ clock-controller@1d021000 {
	compatible = "socionext,milbeaut-m10v-ccu";	compatible = "socionext,milbeaut-m10v-ccu";
	reg = <0x1d021000 0x4000>;	reg = <0x1d021000 0x4000>;
	#clock-cells = <1>;	#clock-cells = <1>;
	clocks = <&clki40mhz>;	clocks = <&clki40mhz>;
	};	};
	-
	- # Required an external clock for Clock controller node:
	- - \|
	- clocks {
	- clki40mhz: clki40mhz {
	- compatible = "fixed-clock";
	- #clock-cells = <0>;
	- clock-frequency = <40000000>;
	- };
	- /* other clocks */
	- };
	-
	- # The clock consumer shall specify the desired clock-output of the clock
	- # controller as below by specifying output-id in its "clk" phandle cell.
	- # 2: uart
	- # 4: 32-bit timer
	- # 7: UHS-I/II
	- - \|
	- serial@1e700010 {
	- compatible = "socionext,milbeaut-usio-uart";
	- reg = <0x1e700010 0x10>;
	- interrupts = <0 141 0x4>, <0 149 0x4>;
	- interrupt-names = "rx", "tx";
	- clocks = <&clk 2>;
	- };
	-
	...	...

sys/contrib/device-tree/Bindings/clock/mobileye,eyeq5-clk.yaml
@@ -0,0 +1,51 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Mobileye EyeQ5 clock controller
			+
			+description:
			+ The EyeQ5 clock controller handles 10 read-only PLLs derived from the main
			+ crystal clock. It also exposes one divider clock, a child of one of the PLLs.
			+ Its registers live in a shared region called OLB.
			+
			+maintainers:
			+ - Grégory Clement <gregory.clement@bootlin.com>
			+ - Théo Lebrun <theo.lebrun@bootlin.com>
			+ - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
			+
			+properties:
			+ compatible:
			+ const: mobileye,eyeq5-clk
			+
			+ reg:
			+ maxItems: 2
			+
			+ reg-names:
			+ items:
			+ - const: plls
			+ - const: ospi
			+
			+ "#clock-cells":
			+ const: 1
			+
			+ clocks:
			+ maxItems: 1
			+ description:
			+ Input parent clock to all PLLs. Expected to be the main crystal.
			+
			+ clock-names:
			+ items:
			+ - const: ref
			+
			+required:
			+ - compatible
			+ - reg
			+ - reg-names
			+ - "#clock-cells"
			+ - clocks
			+ - clock-names
			+
			+additionalProperties: false

sys/contrib/device-tree/Bindings/clock/nxp,imx95-blk-ctl.yaml
@@ -0,0 +1,57 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/nxp,imx95-blk-ctl.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: NXP i.MX95 Block Control
			+
			+maintainers:
			+ - Peng Fan <peng.fan@nxp.com>
			+
			+properties:
			+ compatible:
			+ items:
			+ - enum:
			+ - nxp,imx95-lvds-csr
			+ - nxp,imx95-display-csr
			+ - nxp,imx95-camera-csr
			+ - nxp,imx95-netcmix-blk-ctrl
			+ - nxp,imx95-vpu-csr
			+ - const: syscon
			+
			+ reg:
			+ maxItems: 1
			+
			+ power-domains:
			+ maxItems: 1
			+
			+ clocks:
			+ maxItems: 1
			+
			+ '#clock-cells':
			+ const: 1
			+ description:
			+ The clock consumer should specify the desired clock by having the clock
			+ ID in its "clocks" phandle cell. See
			+ include/dt-bindings/clock/nxp,imx95-clock.h
			+
			+required:
			+ - compatible
			+ - reg
			+ - '#clock-cells'
			+ - power-domains
			+ - clocks
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ syscon@4c410000 {
			+ compatible = "nxp,imx95-vpu-csr", "syscon";
			+ reg = <0x4c410000 0x10000>;
			+ #clock-cells = <1>;
			+ clocks = <&scmi_clk 114>;
			+ power-domains = <&scmi_devpd 21>;
			+ };
			+...

sys/contrib/device-tree/Bindings/clock/nxp,imx95-display-master-csr.yaml
@@ -0,0 +1,64 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: NXP i.MX95 Display Master Block Control
			+
			+maintainers:
			+ - Peng Fan <peng.fan@nxp.com>
			+
			+properties:
			+ compatible:
			+ items:
			+ - const: nxp,imx95-display-master-csr
			+ - const: syscon
			+
			+ reg:
			+ maxItems: 1
			+
			+ power-domains:
			+ maxItems: 1
			+
			+ clocks:
			+ maxItems: 1
			+
			+ '#clock-cells':
			+ const: 1
			+ description:
			+ The clock consumer should specify the desired clock by having the clock
			+ ID in its "clocks" phandle cell. See
			+ include/dt-bindings/clock/nxp,imx95-clock.h
			+
			+ mux-controller:
			+ type: object
			+ $ref: /schemas/mux/reg-mux.yaml
			+
			+required:
			+ - compatible
			+ - reg
			+ - '#clock-cells'
			+ - mux-controller
			+ - power-domains
			+ - clocks
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ syscon@4c410000 {
			+ compatible = "nxp,imx95-display-master-csr", "syscon";
			+ reg = <0x4c410000 0x10000>;
			+ #clock-cells = <1>;
			+ clocks = <&scmi_clk 62>;
			+ power-domains = <&scmi_devpd 3>;
			+
			+ mux: mux-controller {
			+ compatible = "mmio-mux";
			+ #mux-control-cells = <1>;
			+ mux-reg-masks = <0x4 0x00000001>; /* Pixel_link_sel */
			+ idle-states = <0>;
			+ };
			+ };
			+...

sys/contrib/device-tree/Bindings/clock/nxp,lpc3220-clk.yaml
@@ -0,0 +1,51 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/nxp,lpc3220-clk.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: NXP LPC32xx Clock Controller
			+
			+maintainers:
			+ - Animesh Agarwal <animeshagarwal28@gmail.com>
			+
			+properties:
			+ compatible:
			+ const: nxp,lpc3220-clk
			+
			+ reg:
			+ maxItems: 1
			+
			+ '#clock-cells':
			+ const: 1
			+
			+ clocks:
			+ minItems: 1
			+ items:
			+ - description: External 32768 Hz oscillator.
			+ - description: Optional high frequency oscillator.
			+
			+ clock-names:
			+ minItems: 1
			+ items:
			+ - const: xtal_32k
			+ - const: xtal
			+
			+required:
			+ - compatible
			+ - reg
			+ - '#clock-cells'
			+ - clocks
			+ - clock-names
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ clock-controller@0 {
			+ compatible = "nxp,lpc3220-clk";
			+ reg = <0x00 0x114>;
			+ #clock-cells = <1>;
			+ clocks = <&xtal_32k>, <&xtal>;
			+ clock-names = "xtal_32k", "xtal";
			+ };

sys/contrib/device-tree/Bindings/clock/nxp,lpc3220-usb-clk.yaml
@@ -0,0 +1,35 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/nxp,lpc3220-usb-clk.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: NXP LPC32xx USB Clock Controller
			+
			+maintainers:
			+ - Animesh Agarwal <animeshagarwal28@gmail.com>
			+
			+properties:
			+ compatible:
			+ const: nxp,lpc3220-usb-clk
			+
			+ reg:
			+ maxItems: 1
			+
			+ '#clock-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - '#clock-cells'
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ clock-controller@f00 {
			+ compatible = "nxp,lpc3220-usb-clk";
			+ reg = <0xf00 0x100>;
			+ #clock-cells = <1>;
			+ };

        - qcom,ipq6018-a53pll
        - qcom,ipq8074-a53pll
        - qcom,ipq9574-a73pll
++      - qcom,msm8226-a7pll
        - qcom,msm8916-a53pll
        - qcom,msm8939-a53pll
    operating-points-v2: true
++  opp-table:
++    type: object
++
  required:
    - compatible
    - reg

sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sc8280xp.yaml
@@ -40,31 +40,19 @@ properties:
	- description: DSI 1 PLL byte clock	- description: DSI 1 PLL byte clock
	- description: DSI 1 PLL DSI clock	- description: DSI 1 PLL DSI clock

	- '#clock-cells':
	- const: 1
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1
	-
	power-domains:	power-domains:
	items:	items:
	- description: MMCX power domain	- description: MMCX power domain

	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+allOf:
		+ - $ref: qcom,gcc.yaml#
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm6350.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
	title: Qualcomm Display Clock & Reset Controller on SM6350	title: Qualcomm Display Clock & Reset Controller on SM6350

	maintainers:	maintainers:
	- - Konrad Dybcio ~~<konrad~~.~~dybcio@somainline.~~org>	+ - Konrad Dybcio <konradybcio@kernel.org>

	description: \|	description: \|
	Qualcomm display clock control module provides the clocks, resets and power	Qualcomm display clock control module provides the clocks, resets and power
@@ -37,28 +37,16 @@ properties:
	- const: dp_phy_pll_link_clk	- const: dp_phy_pll_link_clk
	- const: dp_phy_pll_vco_div_clk	- const: dp_phy_pll_vco_div_clk

	- '#clock-cells':
	- const: 1
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1
	-
	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- clock-names	- clock-names
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+allOf:
		+ - $ref: qcom,gcc.yaml#
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm8x50.yaml
@@ -27,6 +27,7 @@ properties:
	- qcom,sm8350-dispcc	- qcom,sm8350-dispcc

	clocks:	clocks:
		+ minItems: 7
	items:	items:
	- description: Board XO source	- description: Board XO source
	- description: Byte clock from DSI PHY0	- description: Byte clock from DSI PHY0
@@ -35,8 +36,15 @@ properties:
	- description: Pixel clock from DSI PHY1	- description: Pixel clock from DSI PHY1
	- description: Link clock from DP PHY	- description: Link clock from DP PHY
	- description: VCO DIV clock from DP PHY	- description: VCO DIV clock from DP PHY
		+ - description: Link clock from eDP PHY
		+ - description: VCO DIV clock from eDP PHY
		+ - description: Link clock from DP1 PHY
		+ - description: VCO DIV clock from DP1 PHY
		+ - description: Link clock from DP2 PHY
		+ - description: VCO DIV clock from DP2 PHY

	clock-names:	clock-names:
		+ minItems: 7
	items:	items:
	- const: bi_tcxo	- const: bi_tcxo
	- const: dsi0_phy_pll_out_byteclk	- const: dsi0_phy_pll_out_byteclk
@@ -45,18 +53,12 @@ properties:
	- const: dsi1_phy_pll_out_dsiclk	- const: dsi1_phy_pll_out_dsiclk
	- const: dp_phy_pll_link_clk	- const: dp_phy_pll_link_clk
	- const: dp_phy_pll_vco_div_clk	- const: dp_phy_pll_vco_div_clk
	-	+ - const: edp_phy_pll_link_clk
	- '#clock-cells':	+ - const: edp_phy_pll_vco_div_clk
	- const: 1	+ - const: dptx1_phy_pll_link_clk
	-	+ - const: dptx1_phy_pll_vco_div_clk
	- '#reset-cells':	+ - const: dptx2_phy_pll_link_clk
	- const: 1	+ - const: dptx2_phy_pll_vco_div_clk
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1

	power-domains:	power-domains:
	description:	description:
@@ -70,14 +72,26 @@ properties:

	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- clock-names	- clock-names
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+allOf:
		+ - $ref: qcom,gcc.yaml#
		+ - if:
		+ not:
		+ properties:
		+ compatible:
		+ contains:
		+ const: qcom,sc8180x-dispcc
		+ then:
		+ properties:
		+ clocks:
		+ maxItems: 7
		+ clock-names:
		+ maxItems: 7
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

      const: 1
      deprecated: true
++  '#power-domain-cells': false
++
  required:
    - compatible
        reg = <0x00900000 0x4000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
--      #power-domain-cells = <1>;
        thermal-sensor {
          compatible = "qcom,msm8960-tsens";

  required:
    - compatible
++  - '#power-domain-cells'
  unevaluatedProperties: false

        - const: xo
        - const: sleep_clk
++  '#power-domain-cells': false
++
  required:
    - compatible
        compatible = "qcom,gcc-ipq4019";
        reg = <0x1800000 0x60000>;
        #clock-cells = <1>;
--      #power-domain-cells = <1>;
        #reset-cells = <1>;
        clocks = <&xo>, <&sleep_clk>;
        clock-names = "xo", "sleep_clk";

        - const: xo
        - const: sleep_clk
++  '#power-domain-cells': false
++
  required:
    - compatible
    - clocks
        clocks = <&xo>, <&sleep_clk>;
        clock-names = "xo", "sleep_clk";
        #clock-cells = <1>;
--      #power-domain-cells = <1>;
        #reset-cells = <1>;
      };
  ...

      allOf:
        - $ref: /schemas/thermal/qcom-tsens.yaml#
++  '#power-domain-cells': false
++
  required:
    - compatible
    - clocks
        clock-names = "pxo", "cxo", "pll4";
        #clock-cells = <1>;
        #reset-cells = <1>;
--      #power-domain-cells = <1>;
        tsens: thermal-sensor {
          compatible = "qcom,ipq8064-tsens";

  required:
    - compatible
++  - '#power-domain-cells'
  unevaluatedProperties: false

sys/contrib/device-tree/Bindings/clock/qcom,gcc-mdm9607.yaml
@@ -0,0 +1,43 @@
			+# SPDX-License-Identifier: GPL-2.0-only
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9607.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm Global Clock & Reset Controller
			+
			+maintainers:
			+ - Stephen Boyd <sboyd@kernel.org>
			+ - Taniya Das <quic_tdas@quicinc.com>
			+
			+description: \|
			+ Qualcomm global clock control module provides the clocks, resets and power
			+ domains.
			+
			+ See also::
			+ include/dt-bindings/clock/qcom,gcc-mdm9607.h
			+
			+allOf:
			+ - $ref: qcom,gcc.yaml#
			+
			+properties:
			+ compatible:
			+ enum:
			+ - qcom,gcc-mdm9607
			+
			+required:
			+ - compatible
			+ - '#power-domain-cells'
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ clock-controller@900000 {
			+ compatible = "qcom,gcc-mdm9607";
			+ reg = <0x900000 0x4000>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ #power-domain-cells = <1>;
			+ };
			+...

sys/contrib/device-tree/Bindings/clock/qcom,gcc-mdm9615.yaml
@@ -0,0 +1,50 @@
			+# SPDX-License-Identifier: GPL-2.0-only
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9615.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm Global Clock & Reset Controller
			+
			+maintainers:
			+ - Stephen Boyd <sboyd@kernel.org>
			+ - Taniya Das <quic_tdas@quicinc.com>
			+
			+description: \|
			+ Qualcomm global clock control module provides the clocks, resets and power
			+ domains.
			+
			+ See also::
			+ include/dt-bindings/clock/qcom,gcc-mdm9615.h
			+
			+allOf:
			+ - $ref: qcom,gcc.yaml#
			+
			+properties:
			+ compatible:
			+ enum:
			+ - qcom,gcc-mdm9615
			+
			+ clocks:
			+ items:
			+ - description: CXO clock
			+ - description: PLL4 from LLC
			+
			+ '#power-domain-cells': false
			+
			+required:
			+ - compatible
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ clock-controller@900000 {
			+ compatible = "qcom,gcc-mdm9615";
			+ reg = <0x900000 0x4000>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ clocks = <&cxo_board>,
			+ <&lcc_pll4>;
			+ };
			+...

        - const: pxo
        - const: cxo
++  '#power-domain-cells': false
++
  required:
    - compatible
        reg = <0x900000 0x4000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
--      #power-domain-cells = <1>;
        clocks = <&pxo_board>, <&cxo_board>;
        clock-names = "pxo", "cxo";
      };

    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

  required:
    - compatible
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

  required:
    - compatible
++  - '#power-domain-cells'
  unevaluatedProperties: false

    - clocks
    - clock-names
    - vdd_gfx-supply
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

  title: Qualcomm Global Clock & Reset Controller on MSM8994
  maintainers:
--  - Konrad Dybcio <konrad.dybcio@somainline.org>
++  - Konrad Dybcio <konradybcio@kernel.org>
  description: |
    Qualcomm global clock control module provides the clocks, resets and power
    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

  required:
    - compatible
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

  required:
    - compatible
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

        - const: bi_tcxo_ao
        - const: sleep_clk
++  power-domains:
++    items:
++      - description: CX domain
++
  required:
    - compatible
    - clocks
    - clock-names
++  - power-domains
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#
  examples:
    - |
      #include <dt-bindings/clock/qcom,rpmh.h>
++    #include <dt-bindings/power/qcom-rpmpd.h>
      clock-controller@100000 {
        compatible = "qcom,gcc-sc8180x";
        reg = <0x00100000 0x1f0000>;
                 <&rpmhcc RPMH_CXO_CLK_A>,
                 <&sleep_clk>;
        clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
++      power-domains = <&rpmhpd SC8180X_CX>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        #power-domain-cells = <1>;

  required:
    - compatible
    - clocks
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

  required:
    - compatible
++  - '#power-domain-cells'
  unevaluatedProperties: false

  required:
    - compatible
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

  title: Qualcomm Global Clock & Reset Controller on SM6125
  maintainers:
--  - Konrad Dybcio <konrad.dybcio@somainline.org>
++  - Konrad Dybcio <konradybcio@kernel.org>
  description: |
    Qualcomm global clock control module provides the clocks, resets and power
    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

  title: Qualcomm Global Clock & Reset Controller on SM6350
  maintainers:
--  - Konrad Dybcio <konrad.dybcio@somainline.org>
++  - Konrad Dybcio <konradybcio@kernel.org>
  description: |
    Qualcomm global clock control module provides the clocks, resets and power
    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    - compatible
    - clocks
    - clock-names
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    - reg
    - '#clock-cells'
    - '#reset-cells'
--  - '#power-domain-cells'
  additionalProperties: true

sys/contrib/device-tree/Bindings/clock/qcom,gpucc-sdm660.yaml
@@ -33,28 +33,16 @@ properties:
	- const: gcc_gpu_gpll0_clk	- const: gcc_gpu_gpll0_clk
	- const: gcc_gpu_gpll0_div_clk	- const: gcc_gpu_gpll0_div_clk

	- '#clock-cells':
	- const: 1
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1
	-
	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- clock-names	- clock-names
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+allOf:
		+ - $ref: qcom,gcc.yaml#
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

sys/contrib/device-tree/Bindings/clock/qcom,gpucc.yaml
@@ -53,28 +53,25 @@ properties:
	power-domains:	power-domains:
	maxItems: 1	maxItems: 1

	- '#clock-cells':	+ vdd-gfx-supply:
	- const: 1	+ description: Regulator supply for the VDD_GFX pads
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1

	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- clock-names	- clock-names
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+# Require that power-domains and vdd-gfx-supply are not both present
		+not:
		+ required:
		+ - power-domains
		+ - vdd-gfx-supply
		+
		+allOf:
		+ - $ref: qcom,gcc.yaml#
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

sys/contrib/device-tree/Bindings/clock/qcom,hfpll.yaml
@@ -0,0 +1,69 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/qcom,hfpll.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm High-Frequency PLL
			+
			+maintainers:
			+ - Bjorn Andersson <andersson@kernel.org>
			+
			+description:
			+ The HFPLL is used as CPU PLL on various Qualcomm SoCs.
			+
			+properties:
			+ compatible:
			+ oneOf:
			+ - enum:
			+ - qcom,msm8974-hfpll
			+ - qcom,msm8976-hfpll-a53
			+ - qcom,msm8976-hfpll-a72
			+ - qcom,msm8976-hfpll-cci
			+ - qcom,qcs404-hfpll
			+ - const: qcom,hfpll
			+ deprecated: true
			+
			+ reg:
			+ items:
			+ - description: HFPLL registers
			+ - description: Alias register region
			+ minItems: 1
			+
			+ '#clock-cells':
			+ const: 0
			+
			+ clocks:
			+ items:
			+ - description: board XO clock
			+
			+ clock-names:
			+ items:
			+ - const: xo
			+
			+ clock-output-names:
			+ description:
			+ Name of the PLL. Typically hfpllX where X is a CPU number starting at 0.
			+ Otherwise hfpll_Y where Y is more specific such as "l2".
			+ maxItems: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - '#clock-cells'
			+ - clocks
			+ - clock-names
			+ - clock-output-names
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ clock-controller@f908a000 {
			+ compatible = "qcom,msm8974-hfpll";
			+ reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
			+ #clock-cells = <0>;
			+ clock-output-names = "hfpll0";
			+ clocks = <&xo_board>;
			+ clock-names = "xo";
			+ };

        - description: UNIPHY RX clock source
        - description: UNIPHY TX clk source
++  '#power-domain-cells': false
++
  required:
    - compatible
    - clocks
                 <&uniphy_tx_clk>;
        #clock-cells = <1>;
        #reset-cells = <1>;
--      #power-domain-cells = <1>;
      };
  ...

        - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
        - description: USB PCIE wrapper pipe clock source
++  '#power-domain-cells': false
++  '#interconnect-cells':
++    const: 1
++
  required:
    - compatible
    - clocks
                 <&pcie_2lane_phy_pipe_clk_x1>,
                 <&usb_pcie_wrapper_pipe_clk>;
        #clock-cells = <1>;
--      #power-domain-cells = <1>;
        #reset-cells = <1>;
      };
  ...

        - description: PCIE30 PHY3 pipe clock source
        - description: USB3 PHY pipe clock source
++  '#power-domain-cells': false
++
++  '#interconnect-cells':
++    const: 1
++
  required:
    - compatible
    - clocks
                 <&usb3phy_0_cc_pipe_clk>;
        #clock-cells = <1>;
        #reset-cells = <1>;
--      #power-domain-cells = <1>;
      };
  ...

sys/contrib/device-tree/Bindings/clock/qcom,msm8998-gpucc.yaml
@@ -29,28 +29,16 @@ properties:
	- const: xo	- const: xo
	- const: gpll0	- const: gpll0

	- '#clock-cells':
	- const: 1
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1
	-
	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- clock-names	- clock-names
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+allOf:
		+ - $ref: qcom,gcc.yaml#
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

  title: Q6SSTOP clock Controller
  maintainers:
--  - Govind Singh <govinds@codeaurora.org>
++  - Bjorn Andersson <andersson@kernel.org>
  properties:
    compatible:

sys/contrib/device-tree/Bindings/clock/qcom,qca8k-nsscc.yaml
@@ -0,0 +1,86 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
			+
			+maintainers:
			+ - Bjorn Andersson <andersson@kernel.org>
			+ - Luo Jie <quic_luoj@quicinc.com>
			+
			+description: \|
			+ Qualcomm NSS clock control module provides the clocks and resets
			+ on QCA8386(switch mode)/QCA8084(PHY mode)
			+
			+ See also::
			+ include/dt-bindings/clock/qcom,qca8k-nsscc.h
			+ include/dt-bindings/reset/qcom,qca8k-nsscc.h
			+
			+properties:
			+ compatible:
			+ oneOf:
			+ - const: qcom,qca8084-nsscc
			+ - items:
			+ - enum:
			+ - qcom,qca8082-nsscc
			+ - qcom,qca8085-nsscc
			+ - qcom,qca8384-nsscc
			+ - qcom,qca8385-nsscc
			+ - qcom,qca8386-nsscc
			+ - const: qcom,qca8084-nsscc
			+
			+ clocks:
			+ items:
			+ - description: Chip reference clock source
			+ - description: UNIPHY0 RX 312P5M/125M clock source
			+ - description: UNIPHY0 TX 312P5M/125M clock source
			+ - description: UNIPHY1 RX 312P5M/125M clock source
			+ - description: UNIPHY1 TX 312P5M/125M clock source
			+ - description: UNIPHY1 RX 312P5M clock source
			+ - description: UNIPHY1 TX 312P5M clock source
			+
			+ reg:
			+ items:
			+ - description: MDIO bus address for Clock & Reset Controller register
			+
			+ reset-gpios:
			+ description: GPIO connected to the chip
			+ maxItems: 1
			+
			+required:
			+ - compatible
			+ - clocks
			+ - reg
			+ - reset-gpios
			+
			+allOf:
			+ - $ref: qcom,gcc.yaml#
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/gpio/gpio.h>
			+ mdio {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ clock-controller@18 {
			+ compatible = "qcom,qca8084-nsscc";
			+ reg = <0x18>;
			+ reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
			+ clocks = <&pcs0_pll>,
			+ <&qca8k_uniphy0_rx>,
			+ <&qca8k_uniphy0_tx>,
			+ <&qca8k_uniphy1_rx>,
			+ <&qca8k_uniphy1_tx>,
			+ <&qca8k_uniphy1_rx312p5m>,
			+ <&qca8k_uniphy1_tx312p5m>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ #power-domain-cells = <1>;
			+ };
			+ };
			+...

sys/contrib/device-tree/Bindings/clock/qcom,qcm2290-dispcc.yaml
@@ -37,28 +37,16 @@ properties:
	- const: dsi0_phy_pll_out_byteclk	- const: dsi0_phy_pll_out_byteclk
	- const: dsi0_phy_pll_out_dsiclk	- const: dsi0_phy_pll_out_dsiclk

	- '#clock-cells':
	- const: 1
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1
	-
	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- clock-names	- clock-names
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+allOf:
		+ - $ref: qcom,gcc.yaml#
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

sys/contrib/device-tree/Bindings/clock/qcom,qcm2290-gpucc.yaml
@@ -0,0 +1,77 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm Graphics Clock & Reset Controller on QCM2290
			+
			+maintainers:
			+ - Konrad Dybcio <konradybcio@kernel.org>
			+
			+description: \|
			+ Qualcomm graphics clock control module provides the clocks, resets and power
			+ domains on Qualcomm SoCs.
			+
			+ See also::
			+ include/dt-bindings/clock/qcom,qcm2290-gpucc.h
			+
			+properties:
			+ compatible:
			+ const: qcom,qcm2290-gpucc
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ items:
			+ - description: AHB interface clock,
			+ - description: SoC CXO clock
			+ - description: GPLL0 main branch source
			+ - description: GPLL0 div branch source
			+
			+ power-domains:
			+ description:
			+ A phandle and PM domain specifier for the CX power domain.
			+ maxItems: 1
			+
			+ required-opps:
			+ description:
			+ A phandle to an OPP node describing required CX performance point.
			+ maxItems: 1
			+
			+required:
			+ - compatible
			+ - clocks
			+ - power-domains
			+
			+allOf:
			+ - $ref: qcom,gcc.yaml#
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
			+ #include <dt-bindings/clock/qcom,rpmcc.h>
			+ #include <dt-bindings/power/qcom-rpmpd.h>
			+
			+ soc {
			+ #address-cells = <2>;
			+ #size-cells = <2>;
			+
			+ clock-controller@5990000 {
			+ compatible = "qcom,qcm2290-gpucc";
			+ reg = <0x0 0x05990000 0x0 0x9000>;
			+ clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
			+ <&rpmcc RPM_SMD_XO_CLK_SRC>,
			+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
			+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
			+ power-domains = <&rpmpd QCM2290_VDDCX>;
			+ required-opps = <&rpmpd_opp_low_svs>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ #power-domain-cells = <1>;
			+ };
			+ };
			+...

sys/contrib/device-tree/Bindings/clock/qcom,qcs404-turingcc.yaml
@@ -0,0 +1,47 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/qcom,qcs404-turingcc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm Turing Clock & Reset Controller on QCS404
			+
			+maintainers:
			+ - Bjorn Andersson <andersson@kernel.org>
			+
			+properties:
			+ compatible:
			+ const: qcom,qcs404-turingcc
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ maxItems: 1
			+
			+ '#clock-cells':
			+ const: 1
			+
			+ '#reset-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - clocks
			+ - '#clock-cells'
			+ - '#reset-cells'
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/qcom,gcc-qcs404.h>
			+ clock-controller@800000 {
			+ compatible = "qcom,qcs404-turingcc";
			+ reg = <0x00800000 0x30000>;
			+ clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
			+
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ };

  required:
    - compatible
    - clocks
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    - |
      rpm {
          rpm-requests {
--            compatible = "qcom,rpm-msm8916";
++            compatible = "qcom,rpm-msm8916", "qcom,smd-rpm";
              qcom,smd-channels = "rpm_requests";
              clock-controller {

  required:
    - compatible
    - clocks
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

sys/contrib/device-tree/Bindings/clock/qcom,sc7180-dispcc.yaml
@@ -37,28 +37,16 @@ properties:
	- const: dp_phy_pll_link_clk	- const: dp_phy_pll_link_clk
	- const: dp_phy_pll_vco_div_clk	- const: dp_phy_pll_vco_div_clk

	- '#clock-cells':
	- const: 1
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1
	-
	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- clock-names	- clock-names
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+allOf:
		+ - $ref: qcom,gcc.yaml#
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

sys/contrib/device-tree/Bindings/clock/qcom,sc7280-dispcc.yaml
@@ -41,28 +41,16 @@ properties:
	- const: edp_phy_pll_link_clk	- const: edp_phy_pll_link_clk
	- const: edp_phy_pll_vco_div_clk	- const: edp_phy_pll_vco_div_clk

	- '#clock-cells':
	- const: 1
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1
	-
	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- clock-names	- clock-names
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+allOf:
		+ - $ref: qcom,gcc.yaml#
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

sys/contrib/device-tree/Bindings/clock/qcom,sc8280xp-lpasscc.yaml
@@ -18,9 +18,16 @@ description: \|

	properties:	properties:
	compatible:	compatible:
	- ~~enum:~~	+ oneOf:
	- - qcom,sc8280xp-lpassaudiocc	+ - enum:
	- - qcom,sc8280xp-~~lpasscc~~	+ - qcom,sc8280xp-lpassaudiocc
		+ - qcom,sc8280xp-lpasscc
		+ - items:
		+ - const: qcom,x1e80100-lpassaudiocc
		+ - const: qcom,sc8280xp-lpassaudiocc
		+ - items:
		+ - const: qcom,x1e80100-lpasscc
		+ - const: qcom,sc8280xp-lpasscc

	reg:	reg:
	maxItems: 1	maxItems: 1

sys/contrib/device-tree/Bindings/clock/qcom,sdm845-dispcc.yaml
@@ -46,28 +46,16 @@ properties:
	- const: dp_link_clk_divsel_ten	- const: dp_link_clk_divsel_ten
	- const: dp_vco_divided_clk_src_mux	- const: dp_vco_divided_clk_src_mux

	- '#clock-cells':
	- const: 1
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1
	-
	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- clock-names	- clock-names
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+allOf:
		+ - $ref: qcom,gcc.yaml#
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

  required:
    - compatible
    - clocks
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

sys/contrib/device-tree/Bindings/clock/qcom,sm4450-camcc.yaml
@@ -0,0 +1,63 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm Camera Clock & Reset Controller on SM4450
			+
			+maintainers:
			+ - Ajit Pandey <quic_ajipan@quicinc.com>
			+ - Taniya Das <quic_tdas@quicinc.com>
			+
			+description: \|
			+ Qualcomm camera clock control module provides the clocks, resets and power
			+ domains on SM4450
			+
			+ See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
			+
			+properties:
			+ compatible:
			+ const: qcom,sm4450-camcc
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ items:
			+ - description: Board XO source
			+ - description: Camera AHB clock source from GCC
			+
			+ '#clock-cells':
			+ const: 1
			+
			+ '#reset-cells':
			+ const: 1
			+
			+ '#power-domain-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - clocks
			+ - '#clock-cells'
			+ - '#reset-cells'
			+ - '#power-domain-cells'
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/qcom,rpmh.h>
			+ #include <dt-bindings/clock/qcom,sm4450-gcc.h>
			+ clock-controller@ade0000 {
			+ compatible = "qcom,sm4450-camcc";
			+ reg = <0x0ade0000 0x20000>;
			+ clocks = <&rpmhcc RPMH_CXO_CLK>,
			+ <&gcc GCC_CAMERA_AHB_CLK>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ #power-domain-cells = <1>;
			+ };
			+...

sys/contrib/device-tree/Bindings/clock/qcom,sm4450-dispcc.yaml
@@ -0,0 +1,71 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm Display Clock & Reset Controller on SM4450
			+
			+maintainers:
			+ - Ajit Pandey <quic_ajipan@quicinc.com>
			+ - Taniya Das <quic_tdas@quicinc.com>
			+
			+description: \|
			+ Qualcomm display clock control module provides the clocks, resets and power
			+ domains on SM4450
			+
			+ See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
			+
			+properties:
			+ compatible:
			+ const: qcom,sm4450-dispcc
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ items:
			+ - description: Board XO source
			+ - description: Board active XO source
			+ - description: Display AHB clock source from GCC
			+ - description: sleep clock source
			+ - description: Byte clock from DSI PHY0
			+ - description: Pixel clock from DSI PHY0
			+
			+ '#clock-cells':
			+ const: 1
			+
			+ '#reset-cells':
			+ const: 1
			+
			+ '#power-domain-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - clocks
			+ - '#clock-cells'
			+ - '#reset-cells'
			+ - '#power-domain-cells'
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/qcom,rpmh.h>
			+ #include <dt-bindings/clock/qcom,sm4450-gcc.h>
			+ clock-controller@af00000 {
			+ compatible = "qcom,sm4450-dispcc";
			+ reg = <0x0af00000 0x20000>;
			+ clocks = <&rpmhcc RPMH_CXO_CLK>,
			+ <&rpmhcc RPMH_CXO_CLK_A>,
			+ <&gcc GCC_DISP_AHB_CLK>,
			+ <&sleep_clk>,
			+ <&dsi0_phy_pll_out_byteclk>,
			+ <&dsi0_phy_pll_out_dsiclk>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ #power-domain-cells = <1>;
			+ };
			+...

  required:
    - compatible
    - clocks
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

sys/contrib/device-tree/Bindings/clock/qcom,sm6115-dispcc.yaml
@@ -28,27 +28,15 @@ properties:
	- description: Pixel clock from DSI PHY0	- description: Pixel clock from DSI PHY0
	- description: GPLL0 DISP DIV clock from GCC	- description: GPLL0 DISP DIV clock from GCC

	- '#clock-cells':
	- const: 1
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1
	-
	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+allOf:
		+ - $ref: qcom,gcc.yaml#
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

  title: Qualcomm Graphics Clock & Reset Controller on SM6115
  maintainers:
--  - Konrad Dybcio <konrad.dybcio@linaro.org>
++  - Konrad Dybcio <konradybcio@kernel.org>
  description: |
    Qualcomm graphics clock control module provides clocks, resets and power

  title: Qualcomm Graphics Clock & Reset Controller on SM6125
  maintainers:
--  - Konrad Dybcio <konrad.dybcio@linaro.org>
++  - Konrad Dybcio <konradybcio@kernel.org>
  description: |
    Qualcomm graphics clock control module provides clocks and power domains on

  title: Qualcomm Camera Clock & Reset Controller on SM6350
  maintainers:
--  - Konrad Dybcio <konrad.dybcio@linaro.org>
++  - Konrad Dybcio <konradybcio@kernel.org>
  description: |
    Qualcomm camera clock control module provides the clocks, resets and  power

  title: Qualcomm Display Clock & Reset Controller on SM6375
  maintainers:
--  - Konrad Dybcio <konrad.dybcio@linaro.org>
++  - Konrad Dybcio <konradybcio@kernel.org>
  description: |
    Qualcomm display clock control module provides the clocks, resets and power

  title: Qualcomm Global Clock & Reset Controller on SM6375
  maintainers:
--  - Konrad Dybcio <konrad.dybcio@somainline.org>
++  - Konrad Dybcio <konradybcio@kernel.org>
  description: |
    Qualcomm global clock control module provides the clocks, resets and power
  required:
    - compatible
    - clocks
++  - '#power-domain-cells'
  unevaluatedProperties: false

  title: Qualcomm Graphics Clock & Reset Controller on SM6375
  maintainers:
--  - Konrad Dybcio <konrad.dybcio@linaro.org>
++  - Konrad Dybcio <konradybcio@kernel.org>
  description: |
    Qualcomm graphics clock control module provides clocks, resets and power

sys/contrib/device-tree/Bindings/clock/qcom,sm7150-camcc.yaml
@@ -0,0 +1,60 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/qcom,sm7150-camcc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm Camera Clock & Reset Controller on SM7150
			+
			+maintainers:
			+ - Danila Tikhonov <danila@jiaxyga.com>
			+ - David Wronek <david@mainlining.org>
			+ - Jens Reidel <adrian@travitia.xyz>
			+
			+description: \|
			+ Qualcomm camera clock control module provides the clocks, resets and power
			+ domains on SM7150.
			+
			+ See also:: include/dt-bindings/clock/qcom,sm7150-camcc.h
			+
			+properties:
			+ compatible:
			+ const: qcom,sm7150-camcc
			+
			+ clocks:
			+ items:
			+ - description: Board XO source
			+ - description: Board XO Active-Only source
			+ - description: Sleep clock source
			+
			+ power-domains:
			+ maxItems: 1
			+ description:
			+ CX power domain.
			+
			+required:
			+ - compatible
			+ - clocks
			+ - power-domains
			+
			+allOf:
			+ - $ref: qcom,gcc.yaml#
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/qcom,rpmh.h>
			+ #include <dt-bindings/power/qcom,rpmhpd.h>
			+ clock-controller@ad00000 {
			+ compatible = "qcom,sm7150-camcc";
			+ reg = <0xad00000 0x10000>;
			+ clocks = <&rpmhcc RPMH_CXO_CLK>,
			+ <&rpmhcc RPMH_CXO_CLK_A>,
			+ <&sleep_clk>;
			+ power-domains = <&rpmhpd RPMHPD_CX>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ #power-domain-cells = <1>;
			+ };
			+...

sys/contrib/device-tree/Bindings/clock/qcom,sm7150-dispcc.yaml
@@ -0,0 +1,75 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/qcom,sm7150-dispcc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm Display Clock & Reset Controller for SM7150
			+
			+maintainers:
			+ - Danila Tikhonov <danila@jiaxyga.com>
			+ - David Wronek <david@mainlining.org>
			+ - Jens Reidel <adrian@travitia.xyz>
			+
			+description: \|
			+ Qualcomm display clock control module provides the clocks, resets and power
			+ domains on SM7150.
			+
			+ See also:: include/dt-bindings/clock/qcom,sm7150-dispcc.h
			+
			+properties:
			+ compatible:
			+ const: qcom,sm7150-dispcc
			+
			+ clocks:
			+ items:
			+ - description: Board XO source
			+ - description: Board Always On XO source
			+ - description: GPLL0 source from GCC
			+ - description: Sleep clock source
			+ - description: Byte clock from MDSS DSI PHY0
			+ - description: Pixel clock from MDSS DSI PHY0
			+ - description: Byte clock from MDSS DSI PHY1
			+ - description: Pixel clock from MDSS DSI PHY1
			+ - description: Link clock from DP PHY
			+ - description: VCO DIV clock from DP PHY
			+
			+ power-domains:
			+ maxItems: 1
			+ description:
			+ CX power domain.
			+
			+required:
			+ - compatible
			+ - clocks
			+ - power-domains
			+
			+allOf:
			+ - $ref: qcom,gcc.yaml#
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/qcom,sm7150-gcc.h>
			+ #include <dt-bindings/clock/qcom,rpmh.h>
			+ #include <dt-bindings/power/qcom,rpmhpd.h>
			+ clock-controller@af00000 {
			+ compatible = "qcom,sm7150-dispcc";
			+ reg = <0x0af00000 0x200000>;
			+ clocks = <&rpmhcc RPMH_CXO_CLK>,
			+ <&rpmhcc RPMH_CXO_CLK_A>,
			+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
			+ <&sleep_clk>,
			+ <&mdss_dsi0_phy 0>,
			+ <&mdss_dsi0_phy 1>,
			+ <&mdss_dsi1_phy 0>,
			+ <&mdss_dsi1_phy 1>,
			+ <&dp_phy 0>,
			+ <&dp_phy 1>;
			+ power-domains = <&rpmhpd RPMHPD_CX>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ #power-domain-cells = <1>;
			+ };
			+...

  required:
    - compatible
    - clocks
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

sys/contrib/device-tree/Bindings/clock/qcom,sm7150-videocc.yaml
@@ -0,0 +1,58 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/qcom,sm7150-videocc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm Video Clock & Reset Controller on SM7150
			+
			+maintainers:
			+ - Danila Tikhonov <danila@jiaxyga.com>
			+ - David Wronek <david@mainlining.org>
			+ - Jens Reidel <adrian@travitia.xyz>
			+
			+description: \|
			+ Qualcomm video clock control module provides the clocks, resets and power
			+ domains on SM7150.
			+
			+ See also:: include/dt-bindings/clock/qcom,videocc-sm7150.h
			+
			+properties:
			+ compatible:
			+ const: qcom,sm7150-videocc
			+
			+ clocks:
			+ items:
			+ - description: Board XO source
			+ - description: Board Always On XO source
			+
			+ power-domains:
			+ maxItems: 1
			+ description:
			+ CX power domain.
			+
			+required:
			+ - compatible
			+ - clocks
			+ - power-domains
			+
			+allOf:
			+ - $ref: qcom,gcc.yaml#
			+
			+unevaluatedProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/qcom,rpmh.h>
			+ #include <dt-bindings/power/qcom,rpmhpd.h>
			+ videocc: clock-controller@ab00000 {
			+ compatible = "qcom,sm7150-videocc";
			+ reg = <0x0ab00000 0x10000>;
			+ clocks = <&rpmhcc RPMH_CXO_CLK>,
			+ <&rpmhcc RPMH_CXO_CLK_A>;
			+ power-domains = <&rpmhpd RPMHPD_CX>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ #power-domain-cells = <1>;
			+ };
			+...

sys/contrib/device-tree/Bindings/clock/qcom,sm8150-camcc.yaml
@@ -0,0 +1,77 @@
			+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			+%YAML 1.2
			+---
			+$id: http://devicetree.org/schemas/clock/qcom,sm8150-camcc.yaml#
			+$schema: http://devicetree.org/meta-schemas/core.yaml#
			+
			+title: Qualcomm Camera Clock & Reset Controller on SM8150
			+
			+maintainers:
			+ - Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
			+
			+description: \|
			+ Qualcomm camera clock control module provides the clocks, resets and
			+ power domains on SM8150.
			+
			+ See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h
			+
			+properties:
			+ compatible:
			+ const: qcom,sm8150-camcc
			+
			+ reg:
			+ maxItems: 1
			+
			+ clocks:
			+ items:
			+ - description: Board XO source
			+ - description: Camera AHB clock from GCC
			+
			+ power-domains:
			+ maxItems: 1
			+ description:
			+ A phandle and PM domain specifier for the MMCX power domain.
			+
			+ required-opps:
			+ maxItems: 1
			+ description:
			+ A phandle to an OPP node describing required MMCX performance point.
			+
			+ '#clock-cells':
			+ const: 1
			+
			+ '#reset-cells':
			+ const: 1
			+
			+ '#power-domain-cells':
			+ const: 1
			+
			+required:
			+ - compatible
			+ - reg
			+ - clocks
			+ - power-domains
			+ - required-opps
			+ - '#clock-cells'
			+ - '#reset-cells'
			+ - '#power-domain-cells'
			+
			+additionalProperties: false
			+
			+examples:
			+ - \|
			+ #include <dt-bindings/clock/qcom,gcc-sm8150.h>
			+ #include <dt-bindings/clock/qcom,rpmh.h>
			+ #include <dt-bindings/power/qcom-rpmpd.h>
			+ clock-controller@ad00000 {
			+ compatible = "qcom,sm8150-camcc";
			+ reg = <0x0ad00000 0x10000>;
			+ clocks = <&rpmhcc RPMH_CXO_CLK>,
			+ <&gcc GCC_CAMERA_AHB_CLK>;
			+ power-domains = <&rpmhpd SM8150_MMCX>;
			+ required-opps = <&rpmhpd_opp_low_svs>;
			+ #clock-cells = <1>;
			+ #reset-cells = <1>;
			+ #power-domain-cells = <1>;
			+ };
			+...

  title: Qualcomm SM8350 Video Clock & Reset Controller
  maintainers:
--  - Konrad Dybcio <konrad.dybcio@linaro.org>
++  - Konrad Dybcio <konradybcio@kernel.org>
  description: |
    Qualcomm video clock control module provides the clocks, resets and power

sys/contrib/device-tree/Bindings/clock/qcom,sm8450-camcc.yaml
@@ -8,18 +8,18 @@ title: Qualcomm Camera Clock & Reset Controller on SM8450

	maintainers:	maintainers:
	- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>	- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
		+ - Jagadeesh Kona <quic_jkona@quicinc.com>

	description: \|	description: \|
	Qualcomm camera clock control module provides the clocks, resets and power	Qualcomm camera clock control module provides the clocks, resets and power
	domains on SM8450.	domains on SM8450.

	- See ~~also::~~	+ See also:
		+ include/dt-bindings/clock/qcom,sc8280xp-camcc.h
	include/dt-bindings/clock/qcom,sm8450-camcc.h	include/dt-bindings/clock/qcom,sm8450-camcc.h
	include/dt-bindings/clock/qcom,sm8550-camcc.h	include/dt-bindings/clock/qcom,sm8550-camcc.h
	- include/dt-bindings/clock/qcom,~~sc8280xp~~-camcc.h	+ include/dt-bindings/clock/qcom,sm8650-camcc.h
	-	+ include/dt-bindings/clock/qcom,x1e80100-camcc.h
	-allOf:
	- - $ref: qcom,gcc.yaml#

	properties:	properties:
	compatible:	compatible:
@@ -27,6 +27,8 @@ properties:
	- qcom,sc8280xp-camcc	- qcom,sc8280xp-camcc
	- qcom,sm8450-camcc	- qcom,sm8450-camcc
	- qcom,sm8550-camcc	- qcom,sm8550-camcc
		+ - qcom,sm8650-camcc
		+ - qcom,x1e80100-camcc

	clocks:	clocks:
	items:	items:
@@ -52,7 +54,21 @@ required:
	- compatible	- compatible
	- clocks	- clocks
	- power-domains	- power-domains
	- - required-opps	+
		+allOf:
		+ - $ref: qcom,gcc.yaml#
		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ enum:
		+ - qcom,sc8280xp-camcc
		+ - qcom,sm8450-camcc
		+ - qcom,sm8550-camcc
		+ - qcom,x1e80100-camcc
		+ then:
		+ required:
		+ - required-opps

	unevaluatedProperties: false	unevaluatedProperties: false

sys/contrib/device-tree/Bindings/clock/qcom,sm8450-dispcc.yaml
@@ -40,18 +40,6 @@ properties:
	- description: Link clock from DP PHY3	- description: Link clock from DP PHY3
	- description: VCO DIV clock from DP PHY3	- description: VCO DIV clock from DP PHY3

	- '#clock-cells':
	- const: 1
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1
	-
	power-domains:	power-domains:
	description:	description:
	A phandle and PM domain specifier for the MMCX power domain.	A phandle and PM domain specifier for the MMCX power domain.
@@ -64,13 +52,13 @@ properties:

	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+allOf:
		+ - $ref: qcom,gcc.yaml#
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

sys/contrib/device-tree/Bindings/clock/qcom,sm8450-gpucc.yaml
@@ -7,24 +7,28 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
	title: Qualcomm Graphics Clock & Reset Controller on SM8450	title: Qualcomm Graphics Clock & Reset Controller on SM8450

	maintainers:	maintainers:
	- - Konrad Dybcio ~~<konrad~~.~~dybcio@linaro.~~org>	+ - Konrad Dybcio <konradybcio@kernel.org>

	description: \|	description: \|
	Qualcomm graphics clock control module provides the clocks, resets and power	Qualcomm graphics clock control module provides the clocks, resets and power
	domains on Qualcomm SoCs.	domains on Qualcomm SoCs.

	See also::	See also::
		+ include/dt-bindings/clock/qcom,sm4450-gpucc.h
	include/dt-bindings/clock/qcom,sm8450-gpucc.h	include/dt-bindings/clock/qcom,sm8450-gpucc.h
	include/dt-bindings/clock/qcom,sm8550-gpucc.h	include/dt-bindings/clock/qcom,sm8550-gpucc.h
	include/dt-bindings/reset/qcom,sm8450-gpucc.h	include/dt-bindings/reset/qcom,sm8450-gpucc.h
	include/dt-bindings/reset/qcom,sm8650-gpucc.h	include/dt-bindings/reset/qcom,sm8650-gpucc.h
		+ include/dt-bindings/reset/qcom,x1e80100-gpucc.h

	properties:	properties:
	compatible:	compatible:
	enum:	enum:
		+ - qcom,sm4450-gpucc
	- qcom,sm8450-gpucc	- qcom,sm8450-gpucc
	- qcom,sm8550-gpucc	- qcom,sm8550-gpucc
	- qcom,sm8650-gpucc	- qcom,sm8650-gpucc
		+ - qcom,x1e80100-gpucc

	clocks:	clocks:
	items:	items:
@@ -32,27 +36,15 @@ properties:
	- description: GPLL0 main branch source	- description: GPLL0 main branch source
	- description: GPLL0 div branch source	- description: GPLL0 div branch source

	- '#clock-cells':
	- const: 1
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1
	-
	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+allOf:
		+ - $ref: qcom,gcc.yaml#
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

sys/contrib/device-tree/Bindings/clock/qcom,sm8450-videocc.yaml
@@ -8,21 +8,22 @@ title: Qualcomm Video Clock & Reset Controller on SM8450

	maintainers:	maintainers:
	- Taniya Das <quic_tdas@quicinc.com>	- Taniya Das <quic_tdas@quicinc.com>
		+ - Jagadeesh Kona <quic_jkona@quicinc.com>

	description: \|	description: \|
	Qualcomm video clock control module provides the clocks, resets and power	Qualcomm video clock control module provides the clocks, resets and power
	domains on SM8450.	domains on SM8450.

	- See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h	+ See also:
		+ include/dt-bindings/clock/qcom,sm8450-videocc.h
		+ include/dt-bindings/clock/qcom,sm8650-videocc.h

	properties:	properties:
	compatible:	compatible:
	enum:	enum:
	- qcom,sm8450-videocc	- qcom,sm8450-videocc
	- qcom,sm8550-videocc	- qcom,sm8550-videocc
	-	+ - qcom,sm8650-videocc
	- reg:
	- maxItems: 1

	clocks:	clocks:
	items:	items:
@@ -39,26 +40,26 @@ properties:
	description:	description:
	A phandle to an OPP node describing required MMCX performance point.	A phandle to an OPP node describing required MMCX performance point.

	- '#clock-cells':
	- const: 1
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- power-domains	- power-domains
	- - required-opps
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+allOf:
		+ - $ref: qcom,gcc.yaml#
		+ - if:
		+ properties:
		+ compatible:
		+ contains:
		+ enum:
		+ - qcom,sm8450-videocc
		+ - qcom,sm8550-videocc
		+ then:
		+ required:
		+ - required-opps
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

sys/contrib/device-tree/Bindings/clock/qcom,sm8550-dispcc.yaml
@@ -14,12 +14,17 @@ description: \|
	Qualcomm display clock control module provides the clocks, resets and power	Qualcomm display clock control module provides the clocks, resets and power
	domains on SM8550.	domains on SM8550.

	- See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h	+ See also:
		+ - include/dt-bindings/clock/qcom,sm8550-dispcc.h
		+ - include/dt-bindings/clock/qcom,sm8650-dispcc.h
		+ - include/dt-bindings/clock/qcom,x1e80100-dispcc.h

	properties:	properties:
	compatible:	compatible:
	enum:	enum:
	- qcom,sm8550-dispcc	- qcom,sm8550-dispcc
		+ - qcom,sm8650-dispcc
		+ - qcom,x1e80100-dispcc

	clocks:	clocks:
	items:	items:
@@ -40,18 +45,6 @@ properties:
	- description: Link clock from DP PHY3	- description: Link clock from DP PHY3
	- description: VCO DIV clock from DP PHY3	- description: VCO DIV clock from DP PHY3

	- '#clock-cells':
	- const: 1
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1
	-
	power-domains:	power-domains:
	description:	description:
	A phandle and PM domain specifier for the MMCX power domain.	A phandle and PM domain specifier for the MMCX power domain.
@@ -64,13 +57,13 @@ properties:

	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	-additionalProperties: false	+allOf:
		+ - $ref: qcom,gcc.yaml#
		+
		+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

  required:
    - compatible
    - clocks
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

        - enum:
            - qcom,sm8550-tcsr
            - qcom,sm8650-tcsr
++          - qcom,x1e80100-tcsr
        - const: syscon
    clocks:

  required:
    - compatible
    - clocks
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

sys/contrib/device-tree/Bindings/clock/qcom,videocc.yaml
@@ -37,18 +37,6 @@ properties:
	minItems: 1	minItems: 1
	maxItems: 3	maxItems: 3

	- '#clock-cells':
	- const: 1
	-
	- '#reset-cells':
	- const: 1
	-
	- '#power-domain-cells':
	- const: 1
	-
	- reg:
	- maxItems: 1
	-
	power-domains:	power-domains:
	description:	description:
	A phandle and PM domain specifier for the MMCX power domain.	A phandle and PM domain specifier for the MMCX power domain.
@@ -61,21 +49,19 @@ properties:

	required:	required:
	- compatible	- compatible
	- - reg
	- clocks	- clocks
	- clock-names	- clock-names
	- - '#clock-cells'
	- - '#reset-cells'
	- '#power-domain-cells'	- '#power-domain-cells'

	allOf:	allOf:
		+ - $ref: qcom,gcc.yaml#
		+
	- if:	- if:
	properties:	properties:
	compatible:	compatible:
	enum:	enum:
	- qcom,sc7180-videocc	- qcom,sc7180-videocc
	- qcom,sdm845-videocc	- qcom,sdm845-videocc
	- - qcom,sm8150-videocc
	then:	then:
	properties:	properties:
	clocks:	clocks:
@@ -101,6 +87,22 @@ allOf:
	- const: bi_tcxo	- const: bi_tcxo
	- const: bi_tcxo_ao	- const: bi_tcxo_ao

		+ - if:
		+ properties:
		+ compatible:
		+ enum:
		+ - qcom,sm8150-videocc
		+ then:
		+ properties:
		+ clocks:
		+ items:
		+ - description: AHB
		+ - description: Board XO source
		+ clock-names:
		+ items:
		+ - const: iface
		+ - const: bi_tcxo
		+
	- if:	- if:
	properties:	properties:
	compatible:	compatible:
@@ -119,7 +121,7 @@ allOf:
	- const: bi_tcxo	- const: bi_tcxo
	- const: bi_tcxo_ao	- const: bi_tcxo_ao

	-~~additionalProperties:~~ false	+unevaluatedProperties: false

	examples:	examples:
	- \|	- \|

    - compatible
    - clocks
    - power-domains
++  - '#power-domain-cells'
  allOf:
    - $ref: qcom,gcc.yaml#

    reg:
      maxItems: 1
--  clocks: true
++  clocks:
++    minItems: 1
++    maxItems: 3
    '#clock-cells':
      const: 1
--  clock-output-names: true
++  clock-output-names:
++    minItems: 3
++    maxItems: 17
    renesas,mode:
      description: Board-specific settings of the MD_CK* bits on R-Mobile A1

sys/contrib/device-tree/Bindings/clock/renesas,cpg-mssr.yaml
[diff truncated]
@@ -31,6 +31,7 @@ properties:
	- renesas,r8a7745-cpg-mssr # RZ/G1E		- renesas,r8a7745-cpg-mssr # RZ/G1E