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riscv: Fix and generalise saving TP (PCPU pointer) whilst in userspace

In cpu_fork, we allocate sizeof(struct pcb) + sizeof(struct trapframe)
space on the stack, then round it for stack alignment. This not only
fails to include the space needed for TP but also doesn't round up the
trapframe allocation to be stack-aligned, yet TF_SIZE does, as is the
expectation of fork_trampoline and cpu_exception_handler. Given that
sizeof(struct pcb) + sizeof(struct trapframe) is a multiple of 16, this
causes the saved TP to be stored in the PCB's pcb_sp (the intended
trapframe padding aliasing pcb_ra), which is probably harmless in
practice as the PCB isn't expected to be current, but definitely not
intended.

In cpu_thread_alloc, we do include the 8 bytes for TP and then stack
align that. This again fails to include the padding for trapframe as
present in TF_SIZE, but sizeof(struct pcb) + sizeof(struct trapframe)
happens to be a multiple of 16, as above, so adding 8 then rounding to
stack alignment (16) includes an extra 8 bytes of padding, giving the
right result for the wrong reason (and could be broken by future struct

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sys: Remove $FreeBSD$: one-line .c pattern

Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/

Similar commit in current:
(cherry picked from commit 685dc743dc3b)

sys: Remove $FreeBSD$: one-line .c pattern

Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/

riscv: remove unused string from swtch.S

MFC after:      3 days
Sponsored by:   The FreeBSD Foundation

(cherry picked from commit f5d39047b094d5164b85ae7e2a6a9a8342269815)

riscv: retire the FPE kernel option

We always build the kernel floating point support. Now that the
riscv64sf userspace variant has been removed the option is required for
correct operation.

Reviewed by:    jhb
Sponsored by:   The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D39851

riscv: remove unused string from swtch.S

MFC after:      3 days
Sponsored by:   The FreeBSD Foundation

Merge ^/head r358269 through r358399.

Only compile clear_fpu state code when we're building with options FPE.

Soft float kernels build without floating point, and will fail to build if we
try to include floating point code.

Obtained from: kp@

MFC 348835-348836:
Fix global pointer relaxations in the RISC-V kernel

The gp register is intended to used by the linker as another means of
performing relaxations, and should point to the small data section (.sdata).

Currently gp is being used as the pcpu pointer within the kernel, but the more
appropriate choice for this is the tp register, which is unused.

Swap existing usage of gp with tp within the kernel, and set up gp properly
at boot with the value of __global_pointer$ for all harts.

Approved by:    markj (mentor, implicit)

MFHead @349234

Sponsored by:   The FreeBSD Foundation

Fix global pointer relaxations in the RISC-V kernel

The gp register is intended to used by the linker as another means of
performing relaxations, and should point to the small data section (.sdata).

Currently gp is being used as the pcpu pointer within the kernel, but the more
appropriate choice for this is the tp register, which is unused.

Swap existing usage of gp with tp within the kernel, and set up gp properly
at boot with the value of __global_pointer$ for all harts.

Additionally, remove some cases of accessing tp from the PCB, as it is not
part of the per-thread state. The user's tp and gp should be tracked only
through the trapframe.

Reviewed by:    markj, jhb
Approved by:    markj (mentor)
MFC after:      2 weeks
Differential Revision:  https://reviews.freebsd.org/D19893

MFC r344108:
Implement per-CPU pmap activation tracking for RISC-V.

MFhead at r344270

Merge ^/head r343956 through r344177.

Implement per-CPU pmap activation tracking for RISC-V.

This reduces the overhead of TLB invalidations by ensuring that we
only interrupt CPUs which are using the given pmap.  Tracking is
performed in pmap_activate(), which gets called during context switches:
from cpu_throw(), if a thread is exiting or an AP is starting, or
cpu_switch() for a regular context switch.

For now, pmap_sync_icache() still must interrupt all CPUs.

Reviewed by:    kib (earlier version), jhb
Sponsored by:   The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D18874

MFC r341693:
Rename sptbr to satp per v1.10 of the privileged architecture spec.

Merge ^/head r340918 through r341763.

Rename sptbr to satp per v1.10 of the privileged architecture spec.

Add a subroutine for updating satp, for use when updating the
active pmap.  No functional change intended.

Reviewed by:    jhb
MFC after:      1 week
Sponsored by:   The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D18462

MFH r338661 through r339200.

Sponsored by:   The FreeBSD Foundation

Merge ^/head r338731 through r338987.

Various fixes for floating point on RISC-V.

- Explicitly load an empty initial state into FP registers when taking
  the fault on the first FP instruction in a thread.  Setting
  SSTATE.FS to INITIAL is just a marker to let context switch restore
  code know that it can load FP registers with zeroes instead of
  memory loads.  It does not imply that the hardware will reset all
  registers to zero on first access.  In addition, set the state to
  CLEAN instead of INITIAL after the first FP instruction.
  cpu_switch() doesn't do anything for INITIAL and only restores from
  the pcb if the state is CLEAN.  We could perhaps change cpu_switch
  to call fpe_state_clear if the state was INITIAL and leave SSTATE.FS
  set to INITIAL instead of CLEAN after the first FP instruction.
  However, adding this complexity to cpu_switch() doesn't seem worth
  the supposed gain.
- Only save the current FPU registers in fill_fpregs() if the request
  is made to save the current thread's registers.  Previously if a
  debugger requested FP registers via ptrace() it was getting a copy
  of the debugger's FP registers rather than the debugee's.

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MFH @ r337607, in preparation for boarding

Merge ^/head r336870 through r337285, and resolve conflicts.

o Don't overwrite tp in fork_trampoline().
o Save and restore tp in cpu_switch().
o Restore tp in cpu_throw().
o Save tp in savectx().

This makes libthr tests happy. In particular fork_test:fork.

Sponsored by:   DARPA, AFRL

Remove unused string.

Reported by:    markj@
Sponsored by:   DARPA, AFRL

Rename assym.s to assym.inc

assym is only to be included by other .s files, and should never
actually be assembled by itself.

Reviewed by:    imp, bdrewery (earlier)
Sponsored by:   The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D14180

MFhead at r322451

Merge ^/head r321383 through r322397.

Support for v1.10 (latest) of RISC-V privilege specification.

New version is not compatible on supervisor mode with v1.9.1
(previous version).

Highlights:
    o BBL (Berkeley Boot Loader) provides no initial page tables
      anymore allowing us to choose VM, to build page tables manually
      and enable MMU in S-mode.
    o SBI interface changed.
    o GENERIC kernel.
      FDT is now chosen standard for RISC-V hardware description.
      DTB is now provided by Spike (golden model simulator). This
      allows us to introduce GENERIC kernel. However, description
      for console and timer devices is not provided in DTB, so move
      these devices temporary to nexus bus.
    o Supervisor can't access userspace by default. Solution is to
      set SUM (permit Supervisor User Memory access) bit in sstatus
      register.

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Merge ^/head r308491 through r308841.